STMicroelectronics VND5160AJ-E Datasheet

VND5160AJ-E

Double channel high side driver with analog current sense for automotive applications

Features

Max supply voltage

Operating voltage range

V

CC

V

CC

Max on-state resistance (per ch.) R

ON

Current limitation (typ) I

LIMH

Off state supply current I

S

1.

Typical value with all loads connected.

41 V

4.5 to 36V

160 m



5 A

2 µA

(1)

■

■

■

General features

– Inrush current active management by power limitation

– Very low stand-by current

– 3.0V CMOS compatible input

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– In compliance with the 2002/95/EC

European directive

Diagnostic functions

– Proportional load current sense

– High current sense precision for wide range currents

– Current sense disable

– Thermal shutdown indication

– Very low current sense leakage

Protection

– Undervoltage shut-down

– Overvoltage clamp

– Load current limitation

– Self limiting of fast thermal transients

– Protection against loss of ground and loss of V cc

– Thermal shut down

Table 1.

Device summary

Package

PowerSSO-12

Tube

VND5160AJ-E

PowerSSO-12

– Reverse battery protection (see Application schematic

)

– Electrostatic discharge protection

Application

■

■

All types of resistive, inductive and capacitive loads

Suitable as LED driver

Description

The VND5160AJ-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V

CC

pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the

CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.

Order codes

Tape and Reel

VND5160AJTR-E

September 2013 Rev 6 1/31 www.st.com

31

1

2

Contents

Contents

3

4

5

6

VND5160AJ-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1

3.1.2

Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21

Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4

Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1

PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

ECOPACK

®

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31

VND5160AJ-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9.

Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 10.

Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12.

Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14.

PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 15.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/31

List of figures

List of figures

VND5160AJ-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

Delay response time between rising edge of ouput current and rising edge of current sense

(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6.

Iout/isense vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.

Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11.

Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14.

Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15.

Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17.

On state resistance vs. T case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18.

On state resistance vs. V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20.

Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 21.

I

LIMH

vs. T case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22.

Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23.

CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24.

CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25.

CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27.

Maximum turn-Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23

Figure 28.

PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29.

Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 24

Figure 30.

PowerSSO-12™ thermal impedance junction ambient single pulse (one channel ON) . . . 25

Figure 31.

Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25

Figure 32.

PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 33.

PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 34.

PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/31

VND5160AJ-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

V

CC

GND

INPUT1

INPUT2

V

CC

CLAMP

LOGIC

UNDERVOLTAGE

PwCLAMP 1

DRIVER 1

I

LIM

1

V

DSLIM

1

Pwr

LIM

1

OVERTEMP. 1

I

OUT1

K 1

Pwr

LIM

2

CS_DIS

PwCLAMP 2

DRIVER 2

I

OUT2

I

LIM

2

V

DSLIM

2

OVERTEMP. 2

K 2

OUTPUT1

CURRENT

SENSE1

OUTPUT2

CURRENT

SENSE2

Table 2.

Name

Pin function

Function

V

CC

OUTPUT

GND

INPUT n n

Battery connection.

Power output.

Ground connection. Must be reverse battery protected by an external diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.

CURRENT SENSE n

Analog current sense pin, delivers a current proportional to the load current.

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

5/31

Block diagram and pin description

Figure 2.

Configuration diagram (top view)

GND

INPUT2

INPUT1

CURRENT SENSE1

CURRENT SENSE2

CS_DIS

3

4

5

6

1

2

12

11

10

9

8

7

TAB = V cc

N.C.

OUTPUT2

OUTPUT2

OUTPUT1

OUTPUT1

N.C.

VND5160AJ-E

PowerSSO-12

Note: The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The new pinout is backaward compatible with existing PCB layouts where pins #7 and 12 are connected to Vcc. For new PCB designs, these pins should be left unconnected.

Table 3.

Suggested connections for unused and N.C. pins

Connection / Pin

Floating

Current Sense

N.R.

(1)

N.C.

X

Output

X

To ground Through 1k

 resistor X N.R.

(1)

Input CS_DIS

X X

Through 10k

 resistor

Through 10k

 resistor

1.

Not recommended.

6/31

VND5160AJ-E Electrical specifications

Figure 3.

Current and voltage conventions

V

CSD

V

CC

OUTPUTn

V

Fn

(1)

I

S

I

OUTn

V

I

CSD

CS_DIS

I

INn

INn

INPUTn

GND

CURRENT

SENSEn

I

GND

I

SENSEn

V

SENSEn

V

OUTn

V

CC

Note:

2.1

V

Fn

= V

OUTn

- V

CC

during reverse battery condition.

Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

Table 4.

Symbol

Absolute maximum ratings

Parameter

V

CC

-V

CC

- I

GND

I

OUT

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

DC output current

- I

OUT

I

IN

I

CSD

-I

CSENSE

Reverse DC output current

DC input current

DC current sense disable input current

DC reverse CS pin current

V

CSENSE

Current sense maximum voltage

E

MAX

Maximum switching energy (single pulse)

(L=12mH; R

L

=0



; V bat

=13.5V; T jstart

=150ºC; I

OUT

= I limL

(Typ.) )

Value Unit

41

0.3

V

V

200 mA

Internally limited A

6

-1 to 10

-1 to 10

200

V

CC

-41

+V

CC

A mA mA mA

V

V

34 mJ

7/31

Electrical specifications

Table 4.

Symbol

V

ESD

V

ESD

T j

T stg

Absolute maximum ratings (continued)

Parameter

Electrostatic discharge (Human Body Model: R=1.5K



C=100pF)

- INPUT

- CURRENT SENSE

- CS_DIS

- OUTPUT

- V

CC

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

VND5160AJ-E

Value Unit

4000

2000

4000

5000

5000

750

-40 to 150

-55 to 150

V

V

V

V

V

V

°C

°C

8/31

Table 5.

Symbol

Thermal data

Parameter

R thj-case

R thj-amb

Thermal resistance junction-case (MAX) (With one channel ON)

Thermal resistance junction-ambient (MAX)

Max value Unit

8 °C/W

See

Figure 29

°C/W

VND5160AJ-E Electrical specifications

The values specified in this section are for 8V<V

CC

<36V; -40°C<T j

<150°C, unless otherwise stated.

Table 6.

Symbol

Power section

Parameter

V

CC

V

USD

Operating supply voltage

Undervoltage shutdown

V

USDhyst

Undervoltage shut-down hysteresis

R

ON

I

S

On state resistance

(1)

V clamp

Clamp voltage

Supply current

I

L(off)

V

F

Off state output current

(1)

Output - V

CC

diode voltage

(1)

1.

For each channel.

2.

PowerMOS leakage included.

Test conditions

-I

OUT

= 0.6A; T j

=150°C

Min. Typ. Max. Unit

4.5

13 36

3.5

4.5

V

V

0.5

V

I

OUT

= 0.5A; T j

= 25°C

I

OUT

= 0.5A; T j

= 150°C

I

OUT

= 0.5A; V

CC

= 5V; T j

= 25°C

I

S

= 20 mA

Off State; V

CC

= 13V; T j

= 25°C;

V

IN

=V

OUT

=V

SENSE

=V

CSD

=0V

On State; V

CC

=13V; V

IN

=5V; I

OUT

=0A

V

IN

=V

OUT

=0V; V

CC

=13V; T j

=25°C

V

IN

=V

OUT

=0V; V

CC

=13V; T j

=125°C

41 46

0

0

2

(2)

3

5

(2)

6

0.01

3

5

160

320

210

52 m

 m

 m



V

µA mA

µA

0.7

V

Table 7.

Symbol

Switching (V

CC

=13V, T j

=25°C)

Parameter Test conditions t d(on) t d(off)

Turn- On delay time

Turn- Off delay time

(dV

OUT

/dt) on

Turn- On voltage slope

R

L

= 26



(see Figure 8.

)

R

L

= 26



(see Figure 8.

)

R

L

= 26



(dV

OUT

/dt) off

Turn- Off voltage slope

W

W

ON

OFF

Switching energy losses during t won

Switching energy losses during t woff

R

L

= 26



R

L

= 26



(see Figure 8.

)

R

L

= 26



(see Figure 8.

)

Min.

Typ.

10

15

See

Figure 20.

See

Figure 22.

Max.

Unit

µs

µs

V/µs

V/µs

0.03

0.02

mJ mJ

9/31

Electrical specifications VND5160AJ-E

Table 8.

Symbol

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

V

ICL

Logic input

Parameter

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

Input clamp voltage

V

CSDL

I

CSDL

V

CSDH

I

CSDH

V

CSD(hyst)

CS_DIS low level voltage

Low level CS_DIS current

CS_DIS high level voltage

High level CS_DIS current

CS_DIS hysteresis voltage

Test conditions

V

IN

= 0.9V

V

IN

= 2.1V

I

IN

= 1mA

I

IN

= -1mA

V

CSD

= 0.9V

V

CSD

= 2.1V

Min.

Typ.

Max.

Unit

0.9

1

2.1

0.25

5.5

1

2.1

0.25

5.5

-0.7

-0.7

10

7

0.9

10

7

V

µA

V

µA

V

V

V

µA

V

V

V

V

µA

V

V

CSCL

CS_DIS clamp voltage

I

CSD

= 1mA

I

CSD

= -1mA

Table 9.

Symbol

Protection and diagnostics

Parameter

(1)

Test conditions Min.

Typ.

Max.

Unit

I limH

DC short circuit current

V

CC

= 13V

5V<V

CC

<36V

I limL

Short circuit current during thermal cycling

V

CC

= 13V; T

R

<T j

<T

T

TSD

T

R

T

RS

T

HYST

Shutdown temperature

Reset temperature

Thermal reset of STATUS

Thermal hysteresis (T

TSD

-T

R

)

V

DEMAG

Turn-Off output voltage clamp

I

OUT

= 1A; V

IN

= 0;

L= 20mH

TSD

3.8

150

5

2

175

T

RS

+ 1 T

RS

+ 5

135

V

CC

-41 V

7

CC

-46 V

7.5

7.5

200

A

A

A

°C

°C

°C

°C

CC

-52 V

V

ON

Output voltage drop limitation

I

OUT

= 0.03A;

T j

= -40°C...150°C

(see Figure 9.

)

25 mV

1.

To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.

10/31

VND5160AJ-E Electrical specifications

Table 10.

Current sense (8V<VCC<16V)

Symbol Parameter Test conditions

K

0

K

1 dK

1

/K

1

(1)

K

2 dK

2

/K

2

(1)

K

3 dK

3

/K

3

(1)

I

SENSE0

I

OL

V

SENSE

V

SENSEH

I

SENSEH

Min. Typ. Max. Unit

I

I

OUT

OUT

/I

/I

SENSE

SENSE

I

OUT

= 0.025A; V

SENSE

= 0.5V; V

CSD

=0V;

T j

= -40°C...150°C

I

OUT

= 0.35A; V

SENSE

=0.5V; V

CSD

=0V;

T j

= -40°C...150°C

I

OUT

=0.35A; V

SENSE

=0.5V; V

CSD

=0V;

T j

= 25°C...150°C

Current sense ratio drift

I

OUT

= 0.35A; V

SENSE

= 0.5V;

V

CSD

=0V;

T

J

= -40 °C to 150 °C

I

OUT

/I

SENSE

Current sense ratio drift

I

OUT

= 0.5A; V

SENSE

= 4V; V

CSD

= 0V;

T j

= -40°C...150°C

I

OUT

= 0.5A; V

SENSE

= 4V; V

CSD

= 0V;

T j

= 25°C...150°C

I

OUT

= 0.5 A; V

SENSE

= 4 V;

V

CSD

= 0V;

T

J

= -40 °C to 150 °C

I

OUT

/I

SENSE

Current sense ratio drift

I

OUT

= 1.5A; V

SENSE

=4V; V

CSD

=0V;

T j

= -40°C...150°C

I

OUT

=1.5A; V

SENSE

=4V; V

CSD

=0V;

T j

= 25°C...150°C

I

OUT

= 1.5 A; V

SENSE

= 4 V;

V

CSD

=0V;

T

J

= -40 °C to 150 °C

I

OUT

=0A; V

SENSE

=0V;

V

CSD

=5V; V

IN

=0V; T j

=-40°C...150°C

V

CSD

=0V; V

IN

=5V; T j

=-40°C...150°C Analog sense leakage current

I

OUT

=0.6A; V

SENSE

=0V;

V

CSD

=5V; V

IN

=5V; T j

= -40°C...150°C

Openload ON state current detection threshold

V

IN

= 5V, I

SENSE

= 5 µA

260 500 750

320

360

-13

360

380

-8

410

420

-4

0

0

0

1

450

450

440

440

440

440

590

540

+13

540

510

+8

480

460

+4

1

2

1

5

%

%

%

µA

µA

µA mA

Max analog senseoutput voltage

I

OUT

=1.5A; V

CSD

=0V; 5 V

Analog sense output voltage in overtemperature condition

Analog sense output current in overtemperature condition

V

V

CC

CC

=13V; R

=13V; V

SENSE

SENSE

= 3.9K

= 5V;



9

8

V mA

11/31

Electrical specifications

Table 10.

Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions t

DSENSE1H

Delay response time from falling edge of CS_DIS pin t

DSENSE1L

Delay response time from rising edge of CS_DIS pin

V

I

SENSE

(see

V

SENSE

=90% of I

SENSE

Figure 4.

SENSE

I

SENSE

(see

<4V, 0.08A<Iout<1.5A

)

max

<4V, 0.08A<Iout<1.5A

=10% of I

SENSE

Figure 4.

)

max t t

DSENSE2H

DSENSE2L

Delay response time from rising edge of INPUT pin

Delay response time from falling edge of INPUT pin

V

SENSE

<4V, 0.08A<Iout<1.5A

I

SENSE

=90% of I

SENSE max

(see

Figure 4.

)

 t

DSENSE2H

Delay response time between rising edge of output current and rising edge of current sense

V

SENSE

< 4V,

I

SENSE

= 90% of I

SENSEMAX,

I

OUT

= 90% of I

OUTMAX

I

OUTMAX

=2A (see

Figure 5

)

V

SENSE

<4V, 0.08A<Iout<1.5A

I

SENSE

=10% of I

SENSE max

(see

Figure 4.

)

1.

Parameter guaranteed by design; it is not tested.

Figure 4.

Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT t

DSENSE2H t

DSENSE1L

VND5160AJ-E

Min. Typ. Max. Unit

50 100 µs

5 20 µs

80 150 µs

20 s

µ

100 250 µs t

DSENSE1H t

DSENSE2L

12/31

VND5160AJ-E Electrical specifications

Figure 5.

Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)

V

IN

 t

DSENSE2H t

I

OUT

90% I

OUTMAX

I

OUTMAX t

I

SENSE I

SENSEMAX

90% I

SENSEMAX t

13/31

Electrical specifications

Figure 6.

I out

/ I sense

vs. I out

(see

Table 10

for details)

I out

/ I sense

700

650

600

550

500

450 max Tj = -40 °C to 150 °C max Tj = 25 °C to 150 °C

400

350

300

250

200

0,35 min Tj = 25 °C to 150 °C min Tj = -40 °C to 150 °C

0,58 0,81 typical value

I

OUT

(A)

1,04

Note:

Figure 7.

Maximum current sense ratio drift vs load current dk/k(%)

15

10

5

0

-5

-10

-15

0,1 0,3 0,5 0,7 0,9 1,1 1,3 1,5 1,7

I

OUT

(A)

Parameter guaranteed by design; it is not tested.

1,27

VND5160AJ-E

1,5

14/31

VND5160AJ-E Electrical specifications

Table 11.

Truth table

Conditions

Normal operation

Overtemperature

Undervoltage

Short circuit to GND

(R sc



10 m



)

Short circuit to V

CC

Negative output voltage clamp

INPUT

L

H

L

L

H

L

H

H

L

H

L

H

OUTPUT

H

H

L

L

L

L

L

L

L

L

L

H

SENSE (V

CSD

=0V)

(1)

0

Nominal

0

V

SENSEH

0

0

0

0 if T j

< T

TSD

V

SENSEH

if T j

> T

TSD

0

< Nominal

0

1.

If the V

CSD

is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.

Figure 8.

Switching characteristics

V

OUT t

Won

80% t

Woff

90% dV

OUT

/dt

(on) dV

OUT

/dt

(off) t r

10% t f t

INPUT t d(on) t d(off) t

Figure 9.

Output voltage drop limitation

Vcc-Vout

Tj=150 o

C

Tj=25 o

C

Tj=-40 o

C

Von

Von/Ron(T)

Iout

15/31

Electrical specifications VND5160AJ-E

Table 12.

Electrical transient requirements

ISO 7637-2:

2004(E)

Test pulse

Test levels

(1)

III IV

Number of pulses or test times

1

2a

-75V

+37V

-100V

+50V

5000 pulses

5000 pulses

3a -100V -150V 1h

3b

4

5b

(2)

+75V

-6V

+65V

+100V

-7V

+87V

1h

1 pulse

1 pulse

Burst cycle/pulse repetition time

0.5 s

0.2 s

90 ms

90 ms

5 s

5 s

100 ms

100 ms

Delays and impedance

2 ms, 10



50 µs, 2



0.1 µs, 50



0.1 µs, 50



100 ms, 0.01



400 ms, 2



ISO 7637-2:

2004(E)

Test pulse

1

III

Test level results

(1)

IV

C

C 2a

3a C

C 3b

4

5b

(2)

C

C

1.

The above test levels must be considered referred to V

CC

= 13.5V except for pulse 5b.

2.

Valid in case of external load dump clamp: 40V maximum referred to ground.

C

C

C

C

C

C

Class

C

E

Contents

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

16/31

VND5160AJ-E

Figure 10.

Waveforms

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

NORMAL OPERATION

V

CC

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

V

USD

UNDERVOLTAGE

V

USDhyst

SHORT TO V

CC

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

<Nominal

Electrical specifications

<Nominal

OVERLOAD OPERATION

T j

T

R

T

TSD

T

RS

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT current limitation power limitation thermal cycling

SHORTED LOAD

I

I

LIMH

V

LIML

SENSEH

NORMAL LOAD

17/31

Electrical specifications VND5160AJ-E

Figure 11. Off state output current

Iloff (uA)

0.3

0.25

0.2

0.15

0.1

Off State

Vcc=13V

Vin=Vout=0V

0.05

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 13. Input clamp voltage

Vicl (V)

7

6.8

6.6

6.4

6.2

6

5.8

5.6

5.4

5.2

5

-50 -25 lin=1mA

0 25 50 75

Tc (°C)

Figure 15. Input high level

100 125 150 175

Vih (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 12. High level input current

Iih (uA)

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25

Vin=2.1V

0 25 50 75

Tc (°C)

Figure 14. Input low level

100 125 150 175

Vil (V)

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-50 -25 0 25 50 75

Tc (°C)

100 125

Figure 16. Input hysteresis voltage

150 175

Vihyst (V)

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

18/31

VND5160AJ-E

Figure 17. On state resistance vs. T case

Ron (mOhm)

300

200

180

160

140

280

260

240

220

120

100

80

-50 -25

Iout=0.5A

Vcc=13V

0 25 50 75

Tc (°C)

100 125 150 175

Figure 19. Undervoltage shutdown

Vusd (V)

16

14

12

10

8

6

4

2

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 21. I

LIMH

vs. T case

Ilimh (A)

16

14

12

10

8

6

4

2

0

-50 -25

Vcc=13V

0 25 50 75

Tc (°C)

100 125 150 175

Electrical specifications

Figure 18. On state resistance vs. V

CC

Ron (mOhm)

300

275

250

225

200

175

150

125

100

75

0 5 10 15 20

Vcc (V)

25

Figure 20. Turn-On voltage slope

Tc=150°C

Tc=125°C

Tc=25°C

Tc=-40°C

30 35 40

(dVout/dt)on (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25

Vcc=13V

RI=26Ohm

0 25 50 75

Tc (°C)

100 125 150 175

Figure 22. Turn-Off voltage slope

(dVout/dt)off (V/ms)

1000

900

800

700

600

500

400

300

200

100

0

-50 -25 0

Vcc=13V

RI=26Ohm

25 50 75

Tc (°C)

100 125 150 175

19/31

Electrical specifications

Figure 23. CS_DIS high level voltage

Vcsdh (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

Figure 25.

CS_DIS low level voltage

Vcsdl (V)

4

3.5

3

2.5

2

1.5

1

0.5

0

-50 -25 0 25 50 75

Tc (°C)

100 125 150 175

VND5160AJ-E

Figure 24. CS_DIS clamp voltage

Vcsdcl (V)

8

7.5

7

6.5

6

5.5

5

4.5

4

-50 -25

Icsd=1mA

0 25 50 75

Tc (°C)

100 125 150 175

20/31

VND5160AJ-E Application information

Figure 26.

Application schematic

+5V

V

CC



C

R prot

CS_DIS

R prot

R prot

C

EXT

IINPUT

R

CURRENT SENSE

SENSE

GND

V

GND

R

GND

D

GND

OUTPUT

D ld

Note:

3.1

3.1.1

Channel 2 has the same internal circuit as channel 1.

GND protection network against reverse battery

Solution 1 : resistor in the ground line (R

GND

only)

This can be used with any type of load.

The following is an indication on how to dimension the R

GND resistor.

1.

R

GND



600mV / (I

S(on)max

).

2. R

GND



V

CC

) / (-I

GND

) where -I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power Dissipation in R

GND

(when V

CC

<0: during reverse battery situations) is:

P

D

= (-V

CC

)

2

/R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the

R

GND will produce a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R

GND

.

If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).

21/31

Application information

3.1.2

VND5160AJ-E

Solution 2 : diode (D

GND

) in the ground line

A resistor (R

GND

=1k

 inductive load.

should be inserted in parallel to D

GND

if the device drives an

This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (



600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

3.3

D ld

is necessary ( Voltage Transient Suppressor ) if the load dump peak voltage exceeds the

V

CC

max DC rating. The same applies if the device is subject to transients on the V

CC

line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

MCU I/Os protection

If a ground protection network is used and negative transient are present on the V

CC

line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot

) in line to prevent the MCU I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of MCU and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of MCU

I/Os.

-V

CCpeak

/I latchup



R prot



(V

OHµC

-V

IH

-V

GND

) / I

IHmax

Calculation example:

For V

CCpeak

= - 100V and I latchup



20mA; V

OHµC



4.5V

5k

 

R prot



180k



.

Recommended values: R prot

=10k



C

EXT

=10nF .

22/31

VND5160AJ-E

3.4

Application information

Maximum demagnetization energy (V

CC

= 13.5V)

Figure 27.

Maximum turn-Off current versus inductance (for each channel)

10

C

A

B

1

0,1

0,1 1 L (mH) 10 100

A: T jstart

= 150°C single pulse

B: T jstart

= 100°C repetitive pulse

C: T jstart

= 125°C repetitive pulse

V

IN

, I

L

Demagnetization Demagnetization Demagnetization

Note: t

Values are generated with R

L

= 0



In case of repetitive pulses, T jstart

(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

23/31

Package and PC board thermal data

4 Package and PC board thermal data

4.1 PowerSSO-12 ™ thermal data

Figure 28.

PowerSSO-12 ™ PC board

VND5160AJ-E

Note: Layout condition of R th

and Z th

measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),

Copper areas: from minimum pad lay-out to 8cm

2

).

Figure 29.

R thj-amb

vs. PCB copper area in open box free air condition (one channel ON)

RTHj_amb(°C/ W)

70

65

60

55

50

45

40

0 2 4 6

PCB Cu heatsink area (cm^ 2)

8 10

24/31

VND5160AJ-E Package and PC board thermal data

Figure 30.

PowerSSO-12™ thermal impedance junction ambient single pulse (one channel ON)

ZTH (°C/ W)

100

Footprint

2 cm

2

8 cm

2

10

1

0,001 0,01 0,1 1

Time ( s)

10 100 1000

Equation 1: pulse calculation formula

Z

TH



= R

TH where



= t

P

/T

  + Z

THtp



1 –  

Figure 31.

Thermal fitting model of a double channel HSD in PowerSSO-12™ (a) a.

The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

25/31

Package and PC board thermal data

Table 13.

Thermal parameters

Area/island (cm

2

)

R1= R7 (°C/W)

R2= R8 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1= C7 (W.s/°C)

C2= C8 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

Footprint

0.0008

0.0016

0.0166

0.2

0.27

3

1.2

6

3

8

22

26

0.1

0.8

6

8

15

20

2

VND5160AJ-E

8

0.1

1

9

7

10

15

26/31

VND5160AJ-E

5

Package and packing information

Package and packing information

5.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in ECOPACK

® packages. These packages have a Lead-free second-level interconnect. The category of

Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 Package mechanical data

Figure 32.

PowerSSO-12™ package dimensions

27/31

Package and packing information

Table 14.

PowerSSO-12™ mechanical data

Symbol k

X

Y ddd e

H h

L

B

C

D

E

A

A1

A2

5.800

0.250

0.400

0°

2.200

2.900

Min.

1.250

0.000

1.100

0.230

0.190

4.800

3.800

Millimeters

Typ.

0.800

VND5160AJ-E

6.200

0.500

1.270

8°

2.800

3.500

0.100

Max.

1.620

0.100

1.650

0.410

0.250

5.000

4.000

28/31

VND5160AJ-E Package and packing information

Figure 33.

PowerSSO-12™ tube shipment (no suffix)

A

B

C

Base Q.ty

Bulk Q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

100

2000

532

1.85

6.75

0.6

All dimensions are in mm.

Figure 34.

PowerSSO-12™ tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

2500

2500

330

1.5

13

20.2

12.4

60

18.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (± 0.1)

P

D (± 0.05)

D1 (min)

F (± 0.1)

K (max)

P1 (± 0.1)

12

4

8

1.5

1.5

5.5

4.5

2

All dimensions are in mm.

End

Top cover tape

No components Components No components

500mm min 500mm min

Empty components pockets saled with cover tape.

Start

User direction of feed

29/31

Revision history VND5160AJ-E

Table 15.

Document revision history

Date Revision

13-Sep-2004

10-Apr-2006

01-Mar-2007

10-Dec-2007

12-Feb-2008

24-Sep-2013

1

2

3

4

5

6

Changes

Initial release.

Layout changed.

Major update to Section 2: Electrical specifications .

Reformatted.

Contents, List of tables and List of figures added.

Added

Section 3.4: Maximum demagnetization energy

(VCC = 13.5V)

.

ECOPACK

®

package information added.

Document reformatted and restructured.

Updated

Figure 2: Configuration diagram (top view) : pins 7-12 left

unconnected (N.C) and added note.

Table 4: Absolute maximum ratings

: corrected E

MAX

value from 14 to 34 mJ.

Added

Figure 5: Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)

.

Updated

Figure 6: Iout/ Isense vs. Iout (see Table 10 for details) .

Added

Figure 7: Maximum current sense ratio drift vs load current .

Updated

Table 10: Current sense (8V<VCC<16V) :

– changed t

DSENSE2H max value from 300 µs to 150 µs.

– added dk1/k1, dk2/k2, dk3/k3,

 t

DSENSE2H

, I

OL parameters.

Table 12: Electrical transient requirements

: updated test level values

III and IV for test pulse 5b and notes.

Updated

Section 4.1: PowerSSO-12™ thermal data

:

– changed Figure 29: Rthj-amb vs. PCB copper area in open box free air condition (one channel ON)

.

– changed Figure 30: PowerSSO-12™ thermal impedance junction ambient single pulse (one channel ON) .

–

Figure 31: Thermal fitting model of a double channel HSD in

PowerSSO-12™

: added note.

– updated Table 13: Thermal parameters :

R3 value changed from 7 to 3 °C/W.

R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.

C3 value changed from 0.05 to 0.0166 W.s/°C.

Corrected typing error in Table 10: Current sense (8V<VCC<16V)

: changed I

OL test condition from V

IN

= 0V to V

IN

= 5V.

Updated disclaimer.

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VND5160AJ-E

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