STMicroelectronics VND5T035LAK-E Datasheet

VND5T035LAK-E

Double channel high-side driver with analog current sense

for 24 V automotive applications

Datasheet

−

production data

Features

Max transient supply voltage

Operating voltage range

Typ on-state resistance (per ch.)

Current limitation (typ)

Off-state supply current

V

CC

V

CC

R

ON

I

LIM

I

S

58 V

8 to 36 V

35 m Ω

42 A

2 µA

0OWER33/

("1($'5

Application

All types of resistive, inductive and capacitive loads

■

■

■

General

– Very low standby current

– 3.0 V CMOS compatible input

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– In compliance with the 2002/95/EC

European directive

– Fault reset standby pin (FR_Stby)

– Optimized for LED application

Diagnostic functions

– Proportional load current sense

– High current sense precision for wide range currents

– Off-state open load detection

– Output short to V

CC

detection

– Overload and short to ground latch off

– Thermal shutdown latch-off

– Very low current sense leakage

Protections

– Undervoltage shutdown

– Overvoltage clamp

– Load current limitation

– Self limiting of fast thermal transients

– Protection against loss of ground and loss of V

CC

– Thermal shutdown

– Electrostatic discharge protection

Description

The VND5T035LAK-E is a monolithic device made using STMicroelectronics

®

VIPower

® technology, intended for driving resistive or inductive loads with one side connected to ground. Active V

CC

pin voltage clamp protects the device against low energy spikes.

The device integrates an analog current sense which delivers a current proportional to the load current.

Fault conditions such as overload, overtemperature or short to V

CC

are reported via the current sense pin.

Output current limitation protects the device in overload conditions. The device latches off in case of overload or thermal shutdown.

The device is reset by a low level pass on the fault reset standby pin.

A permanent low level on the inputs and on the fault reset standby pins disables all outputs and sets the device in standby mode.

September 2013

This is information on a product in full production.

Doc ID 023333 Rev. 3 1/32 www.st.com

1

6

7

1

2

Contents

Contents

3

4

5

VND5T035LAK-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1

3.1.2

Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21

Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4

Maximum demagnetization energy (V

CC

= 24 V) . . . . . . . . . . . . . . . . . . . 23

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1

PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

ECOPACK

®

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2

PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3

PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 Doc ID 023333 Rev. 3

VND5T035LAK-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5.

Table 6.

Table 7.

Table 8.

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching (VCC = 24 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9.

Current sense (8 V < V

CC

< 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 10.

Open-load detection (V

FR_Stby

= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 12.

Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 13.

Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 14.

Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 15.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16.

PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Doc ID 023333 Rev. 3 3/32

List of figures

List of figures

VND5T035LAK-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram PowerSSO-24 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

Treset definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5.

Tstby definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.

Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9.

Output stuck to V

CC

detection delay time at FR

STBY

activation . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.

Delay response time between rising edge of output current and rising edge of current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.

Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13.

Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.

High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16.

High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17.

Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19.

On-state resistance vs T

case

Figure 21.

I

LIMH

vs T case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 20.

On-state resistance vs V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 22.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 23.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 25.

Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 26.

PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 27.

Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24

Figure 28.

PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 25

Figure 29.

Thermal fitting model of a double channel HSD in PowerSSO-24

(1)

. . . . . . . . . . . . . . . . . 25

Figure 30.

PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 31.

PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 32.

PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/32 Doc ID 023333 Rev. 3

VND5T035LAK-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

V

CC

Signal Clamp

IN1

IN2

FR_Stby

CS1

CS2

Undervoltage

Control & Diagnostic 2

Control & Diagnostic 1

Power

Clamp

DRIVER

V

ON

Limitation

Over

Temperature

Current

Limitation

V

SENSEH

Current

Sense

OVERLOAD PROTECTION

(ACTIVE POWER LIMITATION)

OFF-state

Open-load

CH1

CH2

LOGIC

GND

GAPGCFT00643

Table 1.

Name

V

CC

OUTn

GND

INn

CSn

FR_Stby

Pin function

Function

Battery connection

Power output

Ground connection

Voltage controlled input pin with hysteresis, CMOS compatible. It controls output switch state

Analog current sense pin; it delivers a current proportional to the load current

In case of latch-off for overtemperature/overcurrent condition, a low pulse on the

FR_Stby pin is needed to reset the channel.

The device enters in standby mode if all inputs and the FR_Stby pin are low.

OUT2

OUT1

Doc ID 023333 Rev. 3 5/32

Block diagram and pin description

Figure 2.

Configuration diagram PowerSSO-24 (top view)

9

&&

1&

&6

,1

1&

)5B6WE\

*1'

1&

,1

&6

6

1&

&&

287

287

287

287

287

287

287

287

287

287

287

287

7$% 9

&&

VND5T035LAK-E

*$3*&)7

Table 2.

Suggested connections for unused and not connected pins

Connection / pin CurrentSense N.C.

Output Input

Floating X

(1)

X

To ground

Not allowed

Through 10 K

Ω resistor

X Not allowed

FR_Stby

X

Through 10 K

Ω resistor

X

Through 10 K Ω

1.

X: do not care.

6/32 Doc ID 023333 Rev. 3

VND5T035LAK-E Electrical specifications

Figure 3.

Current and voltage conventions

V

FR_Stby

I

FR_Stby

V

INn

I

INn

FR_Stby

INPUTn

V

CC

I

OUTn

OUTPUTn

CURRENT

SENSEn

I

SENSEn

I

S

V

Fn

V

SENSEn

V

OUTn

V

CC

Note:

GND

I

GND

V

Fn

= V

OUTn

- V

CC

during reverse battery condition.

Stressing the device above the ratings listed in Table 3

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied.

Table 3.

Symbol

Absolute maximum ratings

Parameter

V

CC

-V

CC

-I

GND

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

I

OUT

-I

OUT

I

IN

DC output current

Reverse DC output current

DC input current

I

FR_Stby

Fault reset standby DC input current

-I

CSENSE

DC reverse CS pin current

V

CSENSE

Current sense maximum voltage

E

MAX

Maximum switching energy

(L = 2.3 mH; V

BAT

= 32 V; T jstart

= 150 °C; I

OUT

= I limL (typ)

)

Value

58

0.3

200

Unit

V

V mA

Internally limited A

40 A

-1 to 10

-1 to 1.5

mA mA

200

V

CC

- 58 to

+V

CC mA

V

250 mJ

Doc ID 023333 Rev. 3 7/32

Electrical specifications

Table 3.

Symbol

L smax

V

ESD

V

ESD

Absolute maximum ratings (continued)

Parameter

Maximum strain inductance in short circuit condition

R

L

= 300 m Ω , V

BAT

= 32 V, T jstart

= 150 °C, l

OUT

= I

LMHmax

Electrostatic discharge

(Human Body Model: R = 1.5 K Ω; C = 100 pF)

– INPUT

– CURRENT SENSE

– FR_Stby

– OUTPUT

– V

CC

Charge device model (CDM-AEC-Q100-011)

T j

T stg

Junction operating temperature

Storage temperature

VND5T035LAK-E

Value Unit

40 µH

4000

2000

4000

5000

5000

750

-40 to 150

-55 to 150

°C

°C

V

V

V

V

V

V

Table 4.

Symbol

Thermal data

Parameter Value Unit

R thj-case

R thj-amb

Thermal resistance junction-case (max) (with one channel ON)

Thermal resistance junction-ambient (max)

2 °C/W

See Figure 27

°C/W

8/32 Doc ID 023333 Rev. 3

VND5T035LAK-E Electrical specifications

8 V < V

CC

< 36 V; -40°C < T j

< 150°C, unless otherwise specified.

Table 5.

Symbol

Power section

Parameter Test conditions

V

V

V

CC

USD

USDhyst

Operating supply voltage

Undervoltage shutdown

Undervoltage shutdown hysteresis

V

I

R

I

ON clamp

S

L(off)

On-state resistance

Clamp voltage

Supply current

(1)

Off-state output current

I

OUT

= 3 A; T j

= 25°C

I

OUT

= 3 A; T j

= 150°C

I

S

= 20 mA

Off-state; V

V

IN

= V

OUT

CC

= V

= 24 V; T j

SENSE

= 25°C;

= 0 V

I

On-state; V

CC

OUT

= 0 A

= 24 V; V

IN

= 5 V;

V

IN

T j

= V

OUT

= 25°C

= 0 V; V

CC

= 24 V;

V

IN

T j

= V

OUT

= 125°C

= 0 V; V

CC

= 24 V;

V

F

Output - V

CC

diode voltage

1.

For each channel

2.

PowerMOS leakage included

-I

OUT

= 3 A; T j

= 150°C

Min.

Typ.

Max.

Unit

8

58

24

3.5

0.5

35

64

2

(2)

4.2

0 0.01

0

36

5

70

70

5

(2)

6

3

5

0.7

V

V

V m Ω

V

µA mA

µA

V

Table 6.

Symbol t d(on) t d(off) dV

OUT

/dt

(on) dV

OUT

/dt

(off)

W

ON

W

OFF

Switching (V

CC

= 24 V; T j

= 25 °C)

Parameter Test conditions

Turn-on delay time

Turn-off delay time

Turn-on voltage slope

Turn-off voltage slope

R

L

= 8 Ω

R

L

= 8

Ω

R

L

= 8 Ω

R

L

= 8

Ω

Switching energy losses during t won

Switching energy losses during t woff

R

L

= 8 Ω

R

L

= 8 Ω

Min.

Typ.

Max.

Unit

46

54

0.55

0.46

µs

µs

V/µs

V/µs

1 mJ

0.65

mJ

Doc ID 023333 Rev. 3 9/32

Electrical specifications

Table 7.

Symbol

Logic inputs

Parameter Test conditions

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

Input low level voltage

Low level input current V

IN

= 0.9 V

Input high level voltage

High level input current V

IN

= 2.1 V

Input hysteresis voltage

V

FR_Stby_L

I

V

ICL

FR_Stby_L

Input clamp voltage

I

IN

= 1 mA

I

IN

= -1 mA

Fault_reset_standby low level voltage

Low level fault_reset_standby current

V

FR_Stby

= 0.9 V

V

FR_Stby_H

Fault_reset_standby high level voltage

I

FR_Stby_H

High level fault_reset_standby current

V

FR_Stby

(hyst)

Fault_reset_standby hysteresis voltage

V

FR_Stby

= 2.1 V

V

FR_Stby_CL

Fault_reset_standby clamp voltage

I

FR_Stby

= 15 mA (10 ms)

I

FR_Stby

= -1 mA t t reset stby

Overload latch-off reset time

Standby delay

See

See

Figure 4

Figure 5

Figure 4.

Treset definition

VND5T035LAK-E

Min.

Typ.

Max.

Unit

0.9

1

2.1

0.25

5.5

-0.7

10

7

V

µA

V

µA

V

V

V

0.9

V

1

2.1

µA

V

10 µA

0.25

V

11

2

120

-0.7

15 V

V

µs 24

1200 µs

7BUHVHW

)5B67%<

,1

287387

&6

2YHUORDG

&KDQQHO

*$3*&)7

10/32 Doc ID 023333 Rev. 3

VND5T035LAK-E

Figure 5.

Tstby definition

)5B6WGE\

Electrical specifications

,1387Q

,*1'

W

VWE\

W

VWE\

*$3*&)7

Table 8.

Symbol

Protections and diagnostics

Parameter Test conditions Min.

Typ.

Max.

Unit

I

I limH limL

DC short circuit current

V

CC

= 24V

5 V < V

CC

< 36 V

Short circuit current during thermal cycling

V

CC

= 24 V; T

R

< T j

< T

TSD

T

TSD

T

R

T

RS

Shutdown temperature

Reset temperature

Thermal reset of status

T

HYST

Thermal hysteresis

(T

TSD

-T

R

)

V

DEMAG

Turn-off output voltage clamp

I

OUT

= 3 A; V

L = 6 mH

IN

= 0;

T

30

150

RS

+ 1 T

135

42

10.5

175

RS

7

+ 5

55

55

200

A

A

A

°C

°C

°C

°C

V

CC

- 58 V

CC

- 64 V

CC

- 70 V

V

ON

Output voltage drop limitation

I

OUT

T j

= 150 mA;

= -40°C to 150°C

25 mV

Doc ID 023333 Rev. 3 11/32

Electrical specifications VND5T035LAK-E

Table 9.

Symbol

Current sense (8 V < V

CC

< 36 V)

Parameter Test conditions dK

LED

/K dK dK dK dK dK

0

1

2

3

4

LEDTOT

(1)

/K

/K

/K

/K

/K

0

(1)

1

(1)

2

(1)

3

(1)

4

(1) dK

BULB

/K

BULBTOT

(1)

I

V

V

K

K

LED

K

K

K

K

K

OL

0

1

2

3

4

SENSE0

SENSE

SENSEH

I

I

I

I

I

I

I

OUT

OUT

Current sense ratio drift

Current sense ratio drift

Current sense ratio drift

Current sense ratio drift

Current sense ratio drift

/I

/I

SENSE

SENSE

Current sense ratio drift

OUT

OUT

OUT

/I

/I

/I

SENSE

SENSE

SENSE

Current sense ratio drift

OUT

OUT

/I

/I

SENSE

SENSE

Analog sense leakage current

I

OUT

T j

= 12 mA; V

SENSE

= -40°C to 150°C

= 0.5 V;

I

OUT

T j

= 12 mA; V

SENSE

= 25°C to 150°C

= 0.5 V;

I

OUT

T j

= 60 mA; V

SENSE

= -40°C to 150°C

= 0.5 V;

I

OUT

T j

= 60 mA; V

SENSE

= 25°C to 150°C

= 0.5 V;

I

OUT

I

CAL

T j

= 12 mA to 60 mA;

= 35 mA; V

SENSE

= -40°C to 150°C

= 0.5 V;

I

OUT

T j

= 100 mA; V

SENSE

= -40°C to 150°C

= 0.5 V;

I

OUT

T j

= 100 mA; V

SENSE

= -40°C to 150°C

= 0.5 V;

I

OUT

T j

= 0.8 A; V

SENSE

= -40°C to 150°C

= 1 V;

I

OUT

T j

= 0.8 A; V

SENSE

= -40°C to 150°C

= 1 V;

I

OUT

T j

= 1.6 A; V

SENSE

= -40°C to 150°C

= 2 V;

I

OUT

T j

= 1.6 A; V

SENSE

= -40°C to 150°C

= 2 V;

I

OUT

T j

= 2.4 A; V

SENSE

= -40°C to 150°C

= 4 V;

I

OUT

T j

= 2.4 A; V

SENSE

= -40°C to 150°C

= 4 V;

I

OUT

T j

= 12 A; V

SENSE

= -40°C to 150°C

= 4 V;

I

OUT

T j

= 12 A; V

SENSE

= -40°C to 150°C

= 4 V;

I

OUT

= 1.3 A to 3.2 A;

I

OUTCAL

T j

= 2.2 A; V

SENSE

= -40°C to 150°C

= 2 V;

I

OUT

V

IN

= 0 A; V

SENSE

= 0 V; T j

= 0 V;

= -40°C to 150°C

I

OUT

V

IN

= 0 A; V

SENSE

= 5 V; T j

= 0 V;

= -40°C to 150°C

Max analog sense output voltage

I

OUT

= 12 A; R

SENSE

= 3.9 K Ω

Analog sense output voltage in fault condition

(2)

V

CC

= 24 V; R

SENSE

= 3.9 K Ω

Min.

820

1357

1690

2040

-40

2215

-20

2210

-18

2541

-14

2706

-10

3055

-4

-18

0

0

5

7.5

Typ.

Max.

Unit

4160

7210

6460

40

8.5

9.5

%

4030 6305

20 %

3400 4590

18 %

3385 4059

14 %

3360 3894

10 %

3313 3445

4 %

18

1

2

%

µA

µA

V

V

12/32 Doc ID 023333 Rev. 3

VND5T035LAK-E Electrical specifications

Table 9.

Symbol

Current sense (8 V < V

CC

< 36 V) (continued)

Parameter Test conditions Min.

Δ t t

I

SENSEH

DSENSE2H t

DSENSE2H

DSENSE2L

Analog sense output current in fault condition

(2)

V

CC

= 24 V; V

SENSE

= 5 V

Delay response time from rising edge of

INPUT pin

V

SENSE

< 4 V;

0.2 A < I

OUT

I

SENSE

< 12 A;

= 90 % of I

SENSE max

;

(see Figure 6

)

Delay response time between rising edge of output current and rising edge of current sense

V

SENSE

< 4 V;

I

SENSE

= 90 % of I

SENSEMAX

;

I

OUT

= 90 % of I

I

OUTMAX

OUTMAX

= 3 A (see

;

Figure 10

)

Delay response time from falling edge of

INPUT pin

V

SENSE

< 4 V;

0.2 A < I

OUT

< 12 A;

I

SENSE

= 10 % of I

(see

Figure 6

)

SENSE max

;

4.9

1.

Parameter guaranteed by design; it is not tested.

2.

Fault condition includes: power limitation, overtemperature and open load in off-state condition.

Typ.

Max.

Unit

9

200

5

12

400

250

20 mA

µs

µs

µs

Table 10.

Open-load detection (V

FR_Stby

= 5 V)

Symbol Parameter Test conditions Min.

Typ.

Max.

Unit t

V

OL

DSTKON

Open-load off-state voltage detection threshold

Output short circuit to

V

CC

detection delay at turn off

V

IN

See

= 0 V; 8 V < V

CC

Figure 7

< 36 V 2

180

I

L(off2) td_vol

Off-state output current at V

OUT

= 4V

V

IN

= 0 V; V

SENSE

= 0 V;

V

OUT rising from 0 V to 4 V

Delay response from output rising edge to

V

SENSE rising edge in open-load

V

V

R

OUT

= 4 V; V

SENSE

SENSE

IN

= 0 V;

= 90 % of V

= 3.9 K

SENSEH

; t

DFRSTK_ON

Output short circuit to

V

CC

detection delay at

FRSTBY activation

See

Figure 9

; Input

1,2

= low

-120

4

1800

0

20

50

V

µs

µA

µs

µs

Doc ID 023333 Rev. 3 13/32

Electrical specifications

Figure 6.

Current sense delay characteristics

,1387

/2$'&855(17

6(16(&855(17

W

'6(16(+

Figure 7.

Open-load off-state delay timing

VND5T035LAK-E

W

'6(16(/

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9

,1

9

&6

9

287

!9

2/

9

6(16(+

W

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Note: Vfr_stby = high

Figure 8.

Switching characteristics

9

287

W

:RQ

G9

287

GW

RQ

W

U

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7

GRQ

7

GRII

W

:RII

W

I

G9

287

GW

RII

W

W

*$3*&)7

14/32 Doc ID 023333 Rev. 3

VND5T035LAK-E Electrical specifications

Figure 9.

Output stuck to V

CC

detection delay time at FR

STBY

activation

)5

67%<

9

VHQVH+

9

&6

W

')567.B21

,QSXW /RZ

*$3*&)7

Figure 10.

Delay response time between rising edge of output current and rising edge of current sense

9

,1 ǻW

'6(16(+

W

,

287

,

2870$;

,

2870$;

W

,

6(16(

,

6(16(0$;

,

6(16(0$;

W

*$3*&)7

Doc ID 023333 Rev. 3 15/32

Electrical specifications

Figure 11.

Output voltage drop limitation

9

&&

9

287

7

M

ƒ& 7

M

ƒ&

7

M

ƒ&

9

21

9

21

5

21

7

,

287

$*9

Figure 12.

Device behavior in overload condition

WBUHVHW

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287387

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29(5/2$'

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287387

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9

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16/32 Doc ID 023333 Rev. 3

VND5T035LAK-E

Table 11.

Truth table

Conditions

Fault reset standby

Standby

Normal operation

Overload

Overtemperature / short to ground

Undervoltage

Short to V

BAT

Open load off-state

(with pull-up)

X

X

X

L

H

X

L

H

X

L

H

X

L

X

X

Negative output voltage clamp

X

Input

L

H

L

H

H

X

L

L

H

L

L

H

L

L

H

L

Output

L

H

L

Cycling

Latched

L

H

H

H

H

H

H

L

L

H

Negative

Electrical specifications

Sense

0

0

Nominal

0

> Nominal

0

V

SENSEH

V

SENSEH

0

0

V

SENSEH

< Nominal

0

V

SENSEH

0

0

Doc ID 023333 Rev. 3 17/32

Electrical specifications VND5T035LAK-E

Table 12.

Electrical transient requirements (part 1)

Test levels

(1)

ISO 7637-2:

2004(E)

Test pulse

III IV

Number of pulses or test times

Burst cycle/pulse repetition time

1

2a

3a

- 450 V

+ 37 V

- 150 V

- 600 V

+ 50 V

- 200 V

5000 pulses

5000 pulses

1h

0.5 s

0.2 s

90 ms

5 s

5 s

100 ms

3b + 150 V + 200 V 1h 90 ms

4

5b

(1)

- 12 V

+ 123 V

- 16 V

+ 174 V

1 pulse

1 pulse

1.

Valid in case of external load dump clamp: 58 V maximum referred to ground.

100 ms

Delays and impedance

1 ms, 50 Ω

50 µs, 2 Ω

0.1 µs, 50 Ω

0.1 µs, 50 Ω

100 ms, 0.01

Ω

350 ms, 1

Ω

Table 13.

Electrical transient requirements (part 2)

(1)

Test level results ISO 7637-2:

2004(E)

Test pulse

III IV

1

2a

C

C

C

C

3a

3b

(2)

3b

(3)

C

E

C

C

E

C

4

5b

(4)

C C

C C

1.

In order to guarantee the ISO transient classes a minimum 10K

Ω

protection resistors are needed on logic pins

2.

Without capacitor between V

CC

and GND.

3.

With 10 nF between V

CC

and GND.

4.

External load dump clamp, 58 V maximum, referred to ground.

Table 14.

Electrical transient requirements (part 3)

Class Contents

C

E

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

18/32 Doc ID 023333 Rev. 3

VND5T035LAK-E

Figure 13.

Off-state output current

,ORII>Q$@

Electrical specifications

Figure 14.

High-level input current

,LK>X$@

9FF 9

9LQ 9RXW

9LQ 9

7F> ƒ&@

Figure 15. Input clamp voltage

9LFO>9@

*$3*&)7

7F> ƒ&@

Figure 16. High-level input voltage

9LK>9@

*$3*&)7

,LQ P$

7F> ƒ&@

Figure 17. Low-level input voltage

9LO>9@

*$3*&)7

7F> ƒ&@

Figure 18. Input hysteresis voltage

9LK\VW>9@

*$3*&)7

7F> ƒ&@

*$3*&)7

Doc ID 023333 Rev. 3

7F> ƒ&@

*$3*&)7

19/32

Electrical specifications VND5T035LAK-E

Figure 19. On-state resistance vs T case

5RQ>P2KP@

Figure 20. On-state resistance vs V

CC

5RQ>P2KP@

7F &

7F &

7F &

7F> ƒ&@

Figure 21. I

LIMH

vs T case

,OLP+>$@

,RXW $

9FF 9

*$3*&)7

7F &

,RXW $

9FF>9@

Figure 22. Turn-on voltage slope

G9RXWGW2Q>9XV@

*$3*&)7

9FF 9

5/ 2KP

7F> ƒ&@

*$3*&)7

7F> ƒ&@

Figure 23. Turn-off voltage slope

G9RXWGW2II>9XV@

*$3*&)7

20/32

9FF 9

5/ 2KP

7F> ƒ&@

*$3*&)7

Doc ID 023333 Rev. 3

VND5T035LAK-E Application information

Figure 24.

Application schematic

9

0&8

5

SURW

)5B6WE\

5

SURW

5

SURW

&

H[W

5

6(16(

,1

&6

9

&&

9

*1'

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'

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287

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OG

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3.1

3.1.1

GND protection network against reverse battery

Solution 1: resistor in the ground line (R

GND

only)

This solution can be used with any type of load.

The following is an indication on how to dimension the R

GND resistor.

1.

R

GND

≤ 600 mV / (I

S(on)max

)

2. R

GND

≥ (−

V

CC

) / (-I

GND

) where -I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power dissipation in R

GND

(when V

CC

< 0: during reverse battery situations) is:

P

D

= (-V

CC

)

2

/ R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the

R

GND produces a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in case of several high side drivers sharing the same R

GND

.

If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests Solution 2 is used (see below).

Doc ID 023333 Rev. 3 21/32

Application information

3.1.2

VND5T035LAK-E

Solution 2: diode (D

GND

) in the ground line

A resistor (R

GND inductive load.

= 4.7 k

Ω) should be inserted in parallel to D

GND

if the device drives an

This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (

≈

600 mV) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

D ld

is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to

V

CC

maximum DC rating. The same applies if the device is subject to transients on the V

CC line that are greater than the ones shown in the ISO T/R 7637/2 table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient is present on the V

CC

line, the control pins are pulled negative. ST suggests that a resistor (R prot

) have to be inserted in line to prevent the microcontroller I/O pins from latching-up.

The value of these resistors is a compromise between the leakage current of the microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.

-V

CCpeak

/I latchup

≤

R prot

≤

(V

OH

μ

C

-V

IH

-V

GND

) / I

IHmax

Calculation example:

For V

CCpeak

= -600 V and I latchup

≥

20 mA; V

OH

μ

C

≥

4.5 V

30 k

Ω ≤

R prot

≤

180 k

Ω

.

Recommended R prot value is 60 k

Ω.

22/32 Doc ID 023333 Rev. 3

VND5T035LAK-E

3.4 Maximum demagnetization energy (V

CC

Application information

= 24 V)

Figure 25.

Maximum turn-off current versus inductance

&

%

9

,1

,

/

A: T jstart

= 150°C single pulse

B: T jstart

= 100°C repetitive pulse

C: T jstart

= 125°C repetitive pulse

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/P+

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*$3*&)7

'HPDJQHWL]DWLRQ

Note:

*$3*&)7

W

Values are generated with R

L

= 0

Ω

. In case of repetitive pulses, T jstart

(at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

Doc ID 023333 Rev. 3 23/32

Package and PCB thermal data

4 Package and PCB thermal data

4.1 PowerSSO-24 thermal data

Figure 26.

PowerSSO-24 PC board

VND5T035LAK-E

.

("1($'5

1.

Layout condition of R th

and Z minimum pad lay-out to 8 cm th

2

).

measurements (PCB: double layer, thermal vias, FR4 area = 77 mm x

86 mm, PCB thickness = 1.6 mm, Cu thickness = 70

μ m (front and back side), Copper areas: from

Figure 27.

R thj-amb

vs PCB copper area in open box free air condition (one channel ON)

5

7+MBDPE

&:

24/32

3&%&XKHDWVLQNDUHDFP

*$3*&)7

Doc ID 023333 Rev. 3

VND5T035LAK-E Package and PCB thermal data

Figure 28.

PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)

=

7+

ƒ&:

$

%

&

A: Cu = Footprint

7LPHV

B: Cu = 2 cm

2

*$3*&)7

C: Cu = 8 cm

2

Figure 29.

Thermal fitting model of a double channel HSD in PowerSSO-24

(1)

("1($'5

1.

The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered

Doc ID 023333 Rev. 3 25/32

Package and PCB thermal data

Equation 1: Pulse calculation formula

Z

TH δ

= R

TH

⋅ δ

+ Z

THtp

(

1 –

δ ) where δ = t

P

/T

Table 15.

Thermal parameters

Area/island (cm

2

)

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

R7 (°C/W)

R8 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

C7 (W.s/°C)

C8 (W.s/°C)

0,1

0,5

1

2.2

0,5

0.75

0,005

0,05

0,005

0,05

Footprint

0,5

0.75

1

7.7

9

28

VND5T035LAK-E

—

—

9

17

—

—

—

—

—

—

8

—

—

—

—

8

10

—

—

4

5

—

—

—

—

—

—

2

—

—

—

—

9

17

26/32 Doc ID 023333 Rev. 3

VND5T035LAK-E

5

Package and packing information

Package and packing information

5.1 ECOPACK

®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

5.2 PowerSSO-24 package information

Figure 30.

PowerSSO-24 package dimensions

Doc ID 023333 Rev. 3 27/32

Package and packing information

Table 16.

PowerSSO-24 mechanical data

Symbol e3

G

G1

H h k

L

N

X

Y

D

E e b c

A

A2 a1

Min.

2.15

2.15

0

0.33

0.23

10.10

7.4

10.1

0.55

4.1

6.5

Millimeters

Typ.

0.8

8.8

5°

VND5T035LAK-E

0.85

10º

4.7

7.1

0.1

0.06

10.5

0.4

Max.

2.47

2.40

0.075

0.51

0.32

10.50

7.6

28/32 Doc ID 023333 Rev. 3

VND5T035LAK-E

5.3

Package and packing information

PowerSSO-24 packing information

Figure 31.

PowerSSO-24 tube shipment (no suffix)

C

B

A

GAPGCFT00002

Base Q.ty

Bulk Q.ty

49

1225

Tube length (± 0.5) 532

A 3.5

B

C (± 0.1)

13.8

0.6

All dimensions are in mm.

Figure 32.

PowerSSO-24 tape and reel shipment (suffix “TR”)

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Doc ID 023333 Rev. 3 29/32

Order codes VND5T035LAK-E

Table 17.

Device summary

Package

PowerSSO-24

Tube

VND5T035LAK-E

Order codes

Tape and reel

VND5T035LAKTR-E

30/32 Doc ID 023333 Rev. 3

VND5T035LAK-E Revision history

Table 18.

Document revision history

Date Revision

15-Jun-2012

19-Jun-2012

18-Sep-2013

1

2

3

Changes

Initial release.

Changed document state form “Target specification“ to “Production data“

Updated disclaimer.

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VND5T035LAK-E

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