STMicroelectronics VND5T100AJ-E Datasheet

VND5T100AJ-E

Double channel high-side driver with analog current sense for 24 V automotive applications

Datasheet

-

production data

– Self limiting of fast thermal transients

– Protection against loss of ground and loss of V

CC

– Thermal shutdown

– Electrostatic discharge protection

PowerSSO-12

Features

Application

All types of resistive, inductive and capacitive loads

Max transient supply voltage

Operating voltage range

Typ on-state resistance (per ch.)

Current limitation (typ)

Off-state supply current

1.

Typical value with all loads connected.

V

CC

V

CC

R

ON

I

LIM

I

S

58 V

8 to 36 V

100 m Ω

22 A

2 µA

(1)

• General

– Very low standby current

– 3.0 V CMOS compatible input

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– Compliant with European directive

2002/95/EC

– Fault reset standby pin (FR_Stby)

• Diagnostic functions

– Proportional load current sense

– High current sense precision for wide range currents

– Off-state open-load detection

– Output short to V

CC

detection

– Overload and short to ground latch-off

– Thermal shutdown latch-off

– Very low current sense leakage

• Protection

– Undervoltage shutdown

– Overvoltage clamp

– Load current limitation

Description

The VND5T100AJ-E is a monolithic device made using STMicroelectronics

®

VIPower

®

technology, intended for driving resistive or inductive loads with one side connected to ground. Active V

CC pin voltage clamp protects the device against low energy spikes.

This device integrates an analog current sense which delivers a current proportional to the load current.

Fault conditions such as overload, overtemperature or short to V

CC

are reported via the current sense pin.

Output current limitation protects the device in overload condition. The device latches off in case of overload or thermal shutdown.

The device is reset by a low level pass on the fault reset standby pin.

A permanent low level on the inputs and fault reset standby pin disables all outputs and sets the device in standby mode.

March 2016

This is information on a product in full production.

DocID018513 Rev 3 1/32 www.st.com

6

7

1

2

Contents

Contents

3

4

5

VND5T100AJ-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1

3.1.2

Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21

Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3

MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4

Maximum demagnetization energy (V

CC

= 24 V) . . . . . . . . . . . . . . . . . . . 23

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1

PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 DocID018513 Rev 3

VND5T100AJ-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5.

Table 6.

Table 7.

Table 8.

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Switching (V

CC

= 24 V; T j

= 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9.

Current sense (8 V < V

CC

< 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10.

Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 12.

Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 13.

Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 14.

Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 15.

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16.

PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 18.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DocID018513 Rev 3 3/32

3

List of figures

List of figures

VND5T100AJ-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

T standby

definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5.

T reset

definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9.

Output stuck to V

CC

detection delay time at FRSTBY activation . . . . . . . . . . . . . . . . . . . . 14

Figure 10.

Delay response time between rising edge of output current and rising edge of current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12.

Device behavior in overload condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13.

Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16.

Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17.

Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19.

On-state resistance vs T

case

Figure 21.

I

LIMH

vs T case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 20.

On-state resistance vs V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 22.

Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 23.

Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 25.

Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 26.

PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 27.

Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 24

Figure 28.

PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 25

Figure 29.

Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 25

Figure 30.

PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 31.

PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 32.

PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/32 DocID018513 Rev 3

VND5T100AJ-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1. Block diagram

9

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Name

V

CC

OUTn

GND

INn

CSn

FR_Stby

Table 1. Pin function

Function

Battery connection

Power output

Ground connection

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state

Analog current sense pin, delivers a current proportional to the load current

In case of latch-off for OT/overcurrent condition, a low pulse on the FR_Stby pin is needed to reset the channel.

The device enters in standby mode if all inputs and the FR_Stby pin are low.

DocID018513 Rev 3 5/32

31

Block diagram and pin description

&6

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Figure 2. Configuration diagram (top view)

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&&

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287

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VND5T100AJ-E

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*$3*&)7

Table 2. Suggested connections for unused and not connected pins

Connection / pin Current sense N.C.

Output Input FR_Stby

Floating

To ground

Not allowed

Through 10 k Ω resistor

X

X

X

Not allowed

X

Through

10 k Ω resistor

X

Through

10 k Ω resistor

6/32 DocID018513 Rev 3

VND5T100AJ-E Electrical specifications

9

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,1Q

Figure 3. Current and voltage conventions

,

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Stressing the device above the ratings listed in Table 3

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to the conditions reported in this section for extended periods may affect device reliability.

Symbol

Table 3. Absolute maximum ratings

Parameter

V

CC

-V

CC

-I

GND

I

OUT

-I

OUT

I

IN

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

DC output current

Reverse DC output current

DC input current

I

FR_Stby

-I

CSENSE

Fault reset standby DC input current

DC reverse CS pin current

V

CSENSE

Current sense maximum voltage

E

MAX

Maximum switching energy

(L = 1.9 mH; V bat

= 32 V; T jstart

= 150 °C; I

OUT

= I limL

(Typ))

Value

58

0.3

200

Internally limited

20

-1 to 10

-1 to 1.5

200

V

CC

- 58 to +V

CC

70 mJ

Unit

A mA mA mA

V

V

V mA

A

DocID018513 Rev 3 7/32

31

Electrical specifications VND5T100AJ-E

Symbol

V

ESD

V

ESD

T j

T stg

L

Smax

Table 3. Absolute maximum ratings (continued)

Parameter Value

Electrostatic discharge

(Human Body Model: R = 1.5 k Ω; C = 100 pF)

– INPUT

– CURRENT SENSE

– FR_STBY

– OUTPUT

– V

CC

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

Maximum stray inductance in short circuit

R

L

= 300 m Ω , V bat

= 32 V, T jstart

= 150 °C, I

OUT

= I limHmax

40

4000

2000

4000

5000

5000

750

-40 to 150

-55 to 150

Unit

V

V

V

V

V

V

°C

°C

µH

Symbol

R thj-case

R thj-amb

Table 4. Thermal data

Parameter

Thermal resistance junction-case (with one channel ON)

Thermal resistance junction-ambient

Maximum value Unit

6 °C/W

See

Figure 27 °C/W

8/32 DocID018513 Rev 3

VND5T100AJ-E Electrical specifications

8 V < V

CC

< 36 V; -40 °C < T j

< 150 °C, unless otherwise specified.

.

Symbol Parameter

Table 5. Power section

Test conditions

V

CC

V

USD

Operating supply voltage

Undervoltage shutdown

V

USDhyst

Undervoltage shutdown hysteresis

V

R

ON clamp

On-state resistance

Clamp voltage

(1)

I

OUT

= 1.5 A; T j

= 25 °C

I

OUT

= 1.5 A; T j

= 150 °C

I

S

= 20 mA

Off-state: V

CC

= 24 V; T j

= 25 °C;

V

IN

= V

OUT

= V

SENSE

= 0 V

I

I

S

L(off)

Supply current

Off-state output current

On-state: V

CC

= 24 V; V

IN

= 5 V;

I

OUT

= 0 A

V

IN

= V

OUT

= 0 V; V

CC

= 24 V;

T j

= 25 °C

V

IN

= V

OUT

= 0 V; V

CC

= 24 V;

T j

= 125 °C

V

F

Output - V

CC

diode voltage -I

OUT

= 1.5 A; T j

= 150 °C

1.

For each channel.

2.

PowerMos leakage included

Min. Typ.

Max.

Unit

8 24

3.5

36

5

V

V

58

0

0

0.5

100

64

2

(2)

4.2

0.01

200

70

5

(2)

6

3

5

0.7

V m

V

V

Ω

µA mA

µA

Symbol t d(on) t d(off) dV

OUT

/dt

(on) dV

OUT

/dt

(off)

W

ON

W

OFF

Table 6. Switching (V

CC

= 24 V; T j

= 25 °C)

Parameter Test conditions Min.

Typ.

Max.

Unit

Turn-on delay time

Turn-off delay time

Turn-on voltage slope

Turn-off voltage slope

R

L

= 16 Ω

R

L

= 16

Ω

R

L

= 16 Ω

R

L

= 16

Ω

Switching energy losses during t won

R

L

= 16 Ω

Switching energy losses during t woff

R

L

= 16 Ω

27

38

1

0.65

0.23

0.26

µs

µs

V / µs

V

/

µs mJ mJ

Symbol

V

IL

I

IL

V

IH

Parameter

Table 7. Logic inputs

Test conditions

Input low level voltage

Low level input current

Input high level voltage

V

IN

= 0.9 V

Min.

Typ.

Max.

Unit

0.9

1

2.1

V

µA

V

DocID018513 Rev 3 9/32

31

Electrical specifications VND5T100AJ-E

Symbol

Table 7. Logic inputs (continued)

Parameter Test conditions

V

I

V

V

I

IH

I(hyst)

V

ICL

FR_Stby_L

FR_Stby_L

FR_Stby_H

High level input current

Input hysteresis voltage

V

IN

= 2.1 V

Input clamp voltage

I

IN

= 1 mA

I

IN

= -1 mA

Fault_reset_standby low level voltage

Low level fault_reset_standby current

Fault_reset_standby high level voltage

V

FR_Stby

= 0.9 V

I

FR_Stby_H

High level fault_reset_standby current

V

FR_Stby

= 2.1 V

V

FR_Stby (hyst)

Fault_reset_standby hysteresis voltage

V

FR_Stby_CL

Fault_reset_standby clamp voltage

I

FR_Stby

= 15 mA

(t < 10 ms)

I

FR_Stby

= -1 mA

Overload latch-off reset time See Figure 4

t reset t stby

Standby delay

See Figure 5

Min.

Typ.

Max.

Unit

10

0.25

5.5

-0.7

7

µA

V

V

V

0.9

V

1

2.1

0.25

µA

V

10 µA

V

11 15 V

2

120

-0.7

24

V

µs

1200 µs

Figure 4. T standby

definition

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VWE\

W

VWE\

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10/32 DocID018513 Rev 3

VND5T100AJ-E Electrical specifications

Figure 5. T reset

definition

7BUHVHW

)5B67%<

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287387

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2YHUORDG

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Symbol

I limH

Table 8. Protections and diagnostics

Parameter Test conditions Min.

DC short circuit current

V

CC

= 24 V

5 V < V

CC

< 36 V

V

CC

= 24 V;

T

R

< T j

< T

TSD

16

I limL

Short circuit current during thermal cycling

Shutdown temperature T

TSD

T

R

T

RS

Reset temperature

T

HYST

V

DEMAG

Thermal reset of status

Thermal hysteresis

(T

TSD

- T

R

)

Turn-off output voltage clamp

V

ON

Output voltage drop limitation

I

OUT

= 1.5 A; V

L = 6 mH

IN

= 0;

I

OUT

= 50 mA;

T j

= -40 °C to 150 °C

Typ.

22

6

150 175

T

RS

+ 1 T

RS

+ 5

135

7

Max.

Unit

30

30

A

A

°C

°C

°C

V

CC

- 58 V

CC

- 64 V

CC

- 70 V

25

200

A

°C mV

Symbol

K

1 dK

1

/K

1

(1)

Table 9. Current sense (8 V < V

CC

< 36 V)

Parameter Test conditions Min.

Typ.

Max. Unit

I

OUT

/I

SENSE

Current sense ratio drift

I

OUT

= 350 mA; V

SENSE

= 1 V;

T j

= -40 °C to 150 °C

T j

= 25 °C to 150 °C

I

OUT

= 350 mA; V

SENSE

= 1 V;

T j

= -40 °C to 150 °C

930

1050

1547

1547

2185

2020

-15 15 %

DocID018513 Rev 3 11/32

31

Electrical specifications VND5T100AJ-E

Symbol

Table 9. Current sense (8 V < V

CC

< 36 V) (continued)

Parameter Test conditions Min.

Typ.

Max. Unit dK dK dK

I

2

3

4

K

/K

K

/K

K

2

3

4

/K

2

(1)

3

(1)

4

(1)

SENSE0

V

SENSE

I

I

I

OUT

OUT

OUT

/I

/I

/I

SENSE

Current sense ratio drift

SENSE

Current sense ratio drift

SENSE

Current sense ratio drift

Analog sense leakage current

I

OUT

= 0.8 A; V

SENSE

= 2 V;

T j

= -40 °C to 150 °C

T j

= 25 °C to 150 °C

I

OUT

= 0.8 A; V

SENSE

= 2 V;

T j

= -40 °C to 150 °C

I

OUT

= 1.5 A; V

SENSE

= 2 V;

T j

= -40 °C to 150 °C

T j

= 25 °C to 150 °C

I

OUT

= 1.5 A; V

SENSE

= 2 V;

T j

= -40 °C to 150 °C

I

OUT

= 6 A; V

SENSE

T j

= 4 V;

= -40 °C to 150 °C

T j

= 25 °C to 150 °C

I

OUT

= 6 A; V

SENSE

= 4 V;

T j

= -40 °C to 150 °C

I

OUT

= 0 A; V

SENSE

= 0 V;

V

IN

= 0 V; T j

= -40 °C to 150 °C

I

OUT

= 0 A; V

SENSE

= 0 V;

V

IN

= 5 V; T j

= -40 °C to 150 °C

Max analog sense output voltage

I

OUT

= 6 A; R

SENSE

= 3.9 k Ω

1225

1310

-12

1340

1405

-8

1450

1475

-5

0

0

5

1528

1528

1525

1525

1522

1522

1835

1745

12

1715

1655

8

1600

1560

5

1

2

%

%

%

µA

µA

V

V

I

SENSEH

SENSEH

Analog sense output voltage in fault condition

(2)

V

CC

= 24 V; R

SENSE

= 3.9 k Ω

Analog sense output

current in fault condition

(2)

V

CC

= 24 V; V

SENSE

= 5 V t

DSENSE2H

Delay response time from rising edge of INPUT pin

V

SENSE

< 4 V;

0.07 A < I

OUT

< 6 A;

I

SENSE

= 90 % of I

SENSE max

(see Figure 6 )

Δ t

DSENSE2H t

DSENSE2L

Delay response time between rising edge of output current and rising edge of current sense

Delay response time from falling edge of INPUT pin

V

SENSE

< 4 V;

I

SENSE

= 90 % of I

SENSEMAX,

I

OUT

= 90 % of I

OUTMAX

I

OUTMAX

= 1.5 A (see

Figure 11 )

V

SENSE

< 4 V,

0.07 A < I

OUT

< 6 A;

I

SENSE

= 10 % of I

SENSE max

(see Figure 6 )

7.5

4.9

8.5

9

100

5

1.

Parameter guaranteed by design; it is not tested.

2.

Fault condition includes: power limitation, overtemperature and open-load in OFF-state condition.

9.5

12

200

150

20

V mA

µs

µs

µs

12/32 DocID018513 Rev 3

VND5T100AJ-E Electrical specifications

Symbol Parameter

Table 10. Open-load detection

Test conditions Min.

Typ.

Max.

Unit t

V

OL

DSTKON

Open-load off-state voltage detection threshold

Output short circuit to

V

CC

detection delay at turn off

V

F

IN

= 0 V; 8 V < V

R_STBY

See

F

= 5 V

Figure 6

;

R_STBY

= 5 V

CC

< 36 V; t

DFRSTK_ON

Output short circuit to

V

CC

detection delay at

FRSTBY activation

I t

L(off2) d_vol

See

Figure 9

; Input

1,2

= low

Off-state output current at V

OUT

= 4V

Delay response from output rising edge to

V

SENSE rising edge in open-load

V

IN

= 0 V; V

SENSE

= 0 V;

V

OUT rising from 0 V to 4 V;

F

R_STBY

= 5 V

V

OUT

= 4 V; V

IN

= 0 V;

V

SENSE

R

SENSE

= 90 % of V

= 3.9 k

Ω;

SENSEH

;

F

R_STBY

= 5 V

2

180

-120

4

1800

50

0

20

V

µs

µs

µA

µs

Figure 6. Current sense delay characteristics

,1387

/2$'&855(17

6(16(&855(17

W

'6(16(+

W

'6(16(/

*$3*&)7

Figure 7. Open-load off-state delay timing

2XWSXWVWXFNDW9

&&

9

,1

9

&6

9

287

!9

2/

9

6(16(+

W

'67.21

*$3*&)7

DocID018513 Rev 3 13/32

31

Electrical specifications

9

287

G9

287

GW

RQ

W

U

,1387

7

GRQ

W

:RQ

Figure 8. Switching characteristics

W

:RII

W

I

G9

287

GW

RII

7

GRII

VND5T100AJ-E

W

W

*$3*&)7

Figure 9. Output stuck to V

CC

detection delay time at FRSTBY activation

)5

67%<

9

VHQVH+

9

&6

W

')567.B21

,QSXW /RZ

*$3*&)7

14/32 DocID018513 Rev 3

VND5T100AJ-E Electrical specifications

Figure 10. Delay response time between rising edge of output current and rising edge of current sense

9

,1 ǻW

'6(16(+

W

,

287

,

2870$;

,

2870$;

W

,

6(16(

,

6(16(0$;

,

6(16(0$;

W

*$3*&)7

Figure 11. Output voltage drop limitation

9

&&

9

287

7

M

ƒ& 7

M

ƒ&

7

M

ƒ&

9

21

9

21

5

21

7

,

287

$*9

DocID018513 Rev 3 15/32

31

Electrical specifications

)$8/7B5(6(7

,1

Q

287387

Q

&6

Q

29(5/2$'

&+$11(/

Q

Figure 12. Device behavior in overload condition

WBUHVHW WBUHVHW

287387

Q

DQG&6

Q

FRQWUROOHGE\,QQ

)$8/7B5(6(7IURPµ¶WRµ¶ĺQRDFWLRQRQ&6

Q

SLQ

RYHUORDGODWFKRII,QQKLJKĺ&6

Q

KLJK

)$8/7B5(6(7ORZ$1'7HPSFKDQQHOQRYHUORDGBUHVHWĺRYHUORDGODWFKUHVHWDIWHUWBUHVHW

WR)$8/7B5(6(7ORZ$1',1

Q

KLJKĺWKHUPDOF\FOLQJ&6

Q

KLJK

)$8/7B5(6(7KLJKĺODWFKRIIUHVHWGLVDEOHG

WRRYHUORDGHYHQWDQG)$8/7B5(6(7KLJKĺODWFKRIIQRWKHUPDOF\FOLQJ

WRRYHUORDGGLDJQRVWLFGLVDEOHGHQDEOHGE\WKHLQSXW

RYHUORDGODWFKRIIUHVHWE\)$8/7B5(6(7

29(5/2$' WKHUPDOVKXWGRZQ25SRZHUOLPLWDWLRQ

VND5T100AJ-E

9

VHQVH+

RYHUORDG

RYHUORDGUHVHW

RYHUORDGGLDJUHVHW

*$3*&)7

16/32 DocID018513 Rev 3

VND5T100AJ-E

Standby

Normal operation

Overload

Conditions

Overtemperature / short to ground

Undervoltage

Short to V

BAT

Open-load off-state (with pull-up)

Negative output voltage clamp

Table 11. Truth table

Fault reset standby Input

X

X

X

L

H

L

X

X

X

L

H

X

L

H

X

X

L

H

L

H

H

L

L

H

X

L

L

H

L

L

H

L

Electrical specifications

Output

L

L

H

L

H

L

Cycling

Latched

L

H

H

H

H

H

H

Negative

Sense

0

0

Nominal

0

> Nominal

0

V

SENSEH

V

SENSEH

0

0

V

SENSEH

< Nominal

0

V

SENSEH

0

0

DocID018513 Rev 3 17/32

31

Electrical specifications VND5T100AJ-E

ISO 7637-2:

2004(E)

Test pulse

1

2a

3a

3b

4

5b

(2)

Table 12. Electrical transient requirements (part 1)

Test levels

(1)

III IV

Number of pulses or test times

Burst cycle/pulse repetition time

- 450 V

+ 37 V

- 150 V

+ 150 V

- 12 V

+ 123 V

- 600 V

+ 50 V

- 200 V

+ 200 V

- 16 V

+ 174 V

5000 pulses

5000 pulses

1h

1h

1 pulse

1 pulse

Delays and impedance

0.5 s

0.2 s

5 s

5 s

1 ms, 50 Ω

50 µs, 2 Ω

90 ms 100 ms 0.1 µs, 50 Ω

90 ms 100 ms 0.1 µs, 50 Ω

100 ms, 0.01

Ω

350 ms, 1 Ω

ISO 7637-2:

2004(E)

Test pulse

1

2a

Table 13. Electrical transient requirements (part 2)

III

C

C

Test level results

3a

3b

(1)

3b

(2)

C

E

C

4

5b

(3)

C

C

1.

Without capacitor between V

CC

and GND.

2.

With 10 nF between V

CC

and GND.

3.

External load dump clamp, 58 V maximum, referred to ground.

IV

C

E

C

C

C

C

C

Class

C

E

Table 14. Electrical transient requirements (part 3)

Contents

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the

18/32 DocID018513 Rev 3

VND5T100AJ-E

)L RII>X$@

Figure 13. Off-state output current

Electrical specifications

Figure 14. High level input current

)IH;U!=

9LQ 9

2IIVWDWH

9&& 9

9LQ 9RXW

6 ICL;6 =

7F>ƒ&@

Figure 15. Input clamp voltage

*$3*&)7

7F>ƒ&@

6 IH;6 =

Figure 16. Input high level voltage

'!0'#&4

,LQ P $

6 IL;6 =

7F>ƒ&@

Figure 17. Input low level voltage

*$3*&)7

6 IHYS T;6 =

7F>ƒ&@

*$3*&)7

Figure 18. Input hysteresis voltage

7F>ƒ&@

*$3*&)7

DocID018513 Rev 3

7F>ƒ&@

*$3*&)7

19/32

31

Electrical specifications

Figure 19. On-state resistance vs T case

5RQ>P 2KP @

,RXW $

9FF 9

VND5T100AJ-E

Figure 20. On-state resistance vs V

CC

2ON ;M /HM =

7F ƒ&

7F ƒ&

7F ƒ&

7F ƒ&

)LIM H;!=

7F>ƒ&@

Figure 21. I

LIMH

vs T case

("1($'5

9FF>9@

Figure 22. Turn-on voltage slope

D6 OU TDT /N;6 US =

*$3*&)7

9FF 9 9FF 9

5O ȍ

7F>ƒ&@

*$3*&)7

Figure 23. Turn-off voltage slope

D6 OU TDT /FF ;6 US =

9FF 9

5O ȍ

20/32

7F>ƒ&@

*$3*&)7

DocID018513 Rev 3

7F>ƒ&@

*$3*&)7

VND5T100AJ-E Application information

9

5

SURW

Figure 24. Application schematic

9

&&

)5B6WE\

0&8

5

SURW

5

SURW

&

H[W

5

6(16(

,1

&6

9

*1'

*1'

'

*1'

287

'

OG

*$3*&)7

3.1

3.1.1

GND protection network against reverse battery

Solution 1: resistor in the ground line (R

GND

only)

This solution can be used with any type of load.

The following is an indication on how to size the R

GND resistor.

1.

R

GND

≤ 600 mV / (I

S(on)max

).

2. R

GND

≥ (−

V

CC

) / (-I

GND

) where -I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power dissipation in R

GND

(when V

CC

< 0: during reverse battery situations) is:

P

D

= (-V

CC

)

2

/ R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the

R

GND produces a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in the case of several high side drivers sharing the same R

GND

.

If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests Solution 2 is used (see below).

DocID018513 Rev 3 21/32

31

Application information

3.1.2

VND5T100AJ-E

Solution 2: diode (D

GND

) in the ground line

A resistor (R

GND

= 4.7 k

Ω) should be inserted in parallel to D

GND

if the device drives an inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (

≈

600 mV) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. This shift not varies if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

D ld

is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to

V

CC

maximum DC rating. The same applies if the device is subject to transients on the V

CC line that are greater than the ones shown in the ISO T/R 7637/2 table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the V

CC

line, the control pins are pulled negative. ST suggests that a resistor (R prot

) be inserted in line to prevent the microcontroller I/O pins from latching-up.

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.

-V

CCpeak

/I latchup

≤

R prot

≤

(V

OH

μ

C

-V

IH

-V

GND

) / I

IHmax

Calculation example:

For V

CCpeak

= -600 V and I latchup

≥

20 mA; V

OH

μ

C

≥

4.5 V

30 k

Ω ≤

R prot

≤

180 k

Ω

.

Recommended R prot value is 60 k

Ω.

22/32 DocID018513 Rev 3

VND5T100AJ-E

3.4

Application information

Maximum demagnetization energy (V

CC

= 24 V)

Figure 25. Maximum turn-off current versus inductance

10

A

C

B

1

0.1

1 10

A: T jstart

= 150°C single pulse

B: T jstart

= 100°C repetitive pulse

C: T jstart

= 125°C repetitive pulse

L (mH)

V

IN

, I

L

100

Demagnetization Demagnetization

1000

Demagnetization

1.

Values are generated with R

L

= 0 Ω . In case of repetitive pulses, T jstart

(at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

t

DocID018513 Rev 3 23/32

31

Package and PCB thermal data

4 Package and PCB thermal data

4.1 PowerSSO-12 thermal data

Figure 26. PowerSSO-12 PC board

VND5T100AJ-E

24/32

*$3*&)7

.

1.

Layout condition of R th

and Z th

measurements (Board finish thickness 1.6 mm +/- 10 %; Board double layer; Board dimension 77 mm x 86 mm; Board Material FR4; Cu thickness 0.070 mm (front and back side); Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias

0.025 mm; Footprint dimension 4.1 mm x 6.5 mm).

Figure 27. R thj-amb

vs PCB copper area in open box free air condition (one channel ON)

RTHjamb

65

60

55

50

45

40

35

30

0 2 4 6

RTHjamb

8 10

GAPGCFT000124

DocID018513 Rev 3

VND5T100AJ-E Package and PCB thermal data

Figure 28. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON)

=7+ƒ&:

&X FP

&X FP

&X I RR WSULQW

7LPHV

*$3*&)7

Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-12

*$3*&)7

1.

The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Equation 1: pulse calculation formula

Z

TH δ

= where

R

TH

⋅ δ

+ Z

THtp

(

1 –

δ )

δ = t p

⁄ T

DocID018513 Rev 3 25/32

31

Package and PCB thermal data

Area/island (cm

2

)

R1 = R7 (°C/W)

R2 = R8 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 = C7 (W.s/°C)

C2 = C8 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

Table 15. Thermal parameters

Footprint

0.0008

0.005

0.05

0.2

0.27

3

0.8

1.5

3

8

22

26

2

0.1

0.8

6

8

15

20

VND5T100AJ-E

8

0.1

1

9

7

10

15

26/32 DocID018513 Rev 3

VND5T100AJ-E

5

Package and packing information

Package and packing information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

5.1 PowerSSO-12 mechanical data

Figure 30. PowerSSO-12 package dimensions

DocID018513 Rev 3

("1($'5

27/32

31

Package and packing information

Symbol

D

E e

B

C

A

A1

A2

H h

L k

X

Y ddd

Table 16. PowerSSO-12 mechanical data

Millimeters

Typ.

Min.

1.250

0.000

1.100

0.230

0.190

4.800

3.800

0.800

5.800

0.250

0.400

0°

1.900

3.600

VND5T100AJ-E

Max.

1.700

0.100

1.600

0.410

0.250

5.000

4.000

6.200

0.550

1.270

8°

2.500

4.200

0.100

28/32 DocID018513 Rev 3

VND5T100AJ-E Package and packing information

A

Figure 31. PowerSSO-12 tube shipment (no suffix)

B

C

All dimensions are in mm.

Base q.ty

Bulk q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

100

2000

532

1.85

6.75

0.6

GA P GC FT000123

Figure 32. PowerSSO-12 tape and reel shipment (suffix “TR”)

Reel dimensions

Base q.ty

Bulk q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

2500

2500

330

1.5

13

20.2

12.4

60

18.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape hole spacing

Component spacing

Hole diameter

Hole diameter

Hole position

Compartment depth

Hole spacing

W

P0 (± 0.1)

P

D (± 0.05)

D1 (min)

F (± 0.1)

K (max)

P1 (± 0.1)

1.5

5.5

4.5

2

12

4

8

1.5

All dimensions are in mm.

End

Top cover tape

No components

500mm min

Components No components

Empty components pockets saled with cover tape.

500mm min

User direction of feed

Start

DocID018513 Rev 3 29/32

31

Order code VND5T100AJ-E

Package

PowerSSO-12

Table 17. Device summary

Order codes

Tube

VND5T100AJ-E

Tape and reel

VND5T100AJTR-E

30/32 DocID018513 Rev 3

VND5T100AJ-E

Date

08-Mar-2011

25-Sep-2013

22-Mar-2016

Revision

Table 18. Document revision history

Changes

1

2

3

Initial release.

Disclaimer updated.

Table 4: Thermal data

:

– R thj-case

: updated value

Updated

Section 5.1: PowerSSO-12 mechanical data

Revision history

DocID018513 Rev 3 31/32

31

VND5T100AJ-E

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2016 STMicroelectronics – All rights reserved

32/32 DocID018513 Rev 3