STMicroelectronics VND5T035AK-E Datasheet
The STMicroelectronics VND5T035AK-E is a high-side driver with analog current sense for automotive applications. It features a very low standby current, optimized electromagnetic emission and susceptibility, and is compliant with the European directive 2002/95/EC. The device integrates an analog current sense which delivers a current proportional to the load current, making it suitable for driving resistive, inductive, and capacitive loads. It also has fault conditions such as overload, overtemperature, or short to VCC that are reported via the current sense pin.
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VND5T035AK-E
Double channel high-side driver with analog current sense
for 24 V automotive applications
Datasheet
−
production data
Features
Max transient supply voltage
Operating voltage range
Typ on-state resistance (per ch.)
Current limitation (typ)
Off-state supply current
V
CC
V
CC
R
ON
I
LIM
I
S
58 V
8 to 36 V
35 m Ω
42 A
2 µA
3RZHU662
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■
■
■
General
– Very low standby current
– 3.0 V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– Compliant with European directive
2002/95/EC
– Fault reset standby pin (FR_Stby)
Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range currents
– Off-state open load detection
– Output short to V
CC
detection
– Overload and short to ground latch off
– Thermal shutdown latch-off
– Very low current sense leakage
Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
CC
– Thermal shutdown
– Electrostatic discharge protection
Application
All types of resistive, inductive and capacitive loads
Description
The VND5T035AK-E is a monolithic device made using STMicroelectronics
®
VIPower
®
technology, intended for driving resistive or inductive loads with one side connected to ground. Active V
CC
pin voltage clamp protects the device against low energy spikes.
The device integrates an analog current sense which delivers a current proportional to the load current.
Fault conditions such as overload, overtemperature or short to V
CC
are reported via the current sense pin.
Output current limitation protects the device in overload conditions. The device latches off in case of overload or thermal shutdown.
The device is reset by a low level pass on the fault reset standby pin.
A permanent low level on the inputs and on the fault reset standby pins disables all outputs and sets the device in standby mode.
September 2013
This is information on a product in full production.
Doc ID 018942 Rev 5 1/31 www.st.com
1
Contents
Contents
VND5T035AK-E
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 21
Maximum demagnetization energy (V
CC
= 24 V) . . . . . . . . . . . . . . . . . . . 22
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/31 Doc ID 018942 Rev 5
VND5T035AK-E
List of tables
List of tables
< 36 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FR_Stby
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Doc ID 018942 Rev 5 3/31
List of figures
List of figures
VND5T035AK-E
case
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LIMH
vs T case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 23
PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 24
4/31 Doc ID 018942 Rev 5
VND5T035AK-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
V
CC
Signal Clamp
IN1
IN2
FR_Stby
CS1
CS2
Undervoltage
Control & Diagnostic 2
Control & Diagnostic 1
Power
Clamp
DRIVER
V
ON
Limitation
Over
Temperature
Current
Limitation
V
SENSEH
Current
Sense
OVERLOAD PROTECTION
(ACTIVE POWER LIMITATION)
OFF-state
Open-load
CH1
CH2
OUT2
OUT1
LOGIC
GND
GAPGCFT00643
Table 1.
Name
V
CC
OUT
1,2
GND
IN
1,2
CS
1,2
FR_Stby
Pin function
Function
Battery connection
Power outputs
Ground connection
Voltage controlled input pins with hysteresis, CMOS compatible. They Control output switch state
Analog current sense pins, they deliver a current proportional to the load current
In case of latch-off for overtemperature/overcurrent condition, a low pulse on the
FR_Stby pin is needed to reset the channel.
The device enters in standby mode if all inputs and the FR_Stby pin are low.
Doc ID 018942 Rev 5 5/31
Block diagram and pin description
Figure 2.
Configuration diagram PowerSSO-24 (top view)
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Table 2.
Suggested connections for unused and not connected pins
Connection / pin CurrentSense N.C.
Output Input
Floating X
(1)
X
To ground
Not allowed
Through 10 K Ω resistor
X Not allowed
FR_Stby
X
Through 10 K Ω resistor
X
Through 10 K Ω
1.
X: do not care.
6/31 Doc ID 018942 Rev 5
VND5T035AK-E Electrical specifications
Note:
2.1
Figure 3.
Current and voltage conventions
V
FR_Stby
I
FR_Stby
V
INn
I
INn
FR_Stby
INn
V
CC
I
OUTn
OUTn
CSn
I
SENSEn
I
S
V
Fn
V
SENSEn
V
OUTn
V
CC
GND
I
GND
V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
Absolute maximum ratings
Stressing the device above the ratings listed in the
Table 3 may cause permanent damage
to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions reported in this section for extended periods may affect device reliability.
Table 3.
Symbol
Absolute maximum ratings
Parameter
V
CC
-V
CC
-I
GND
DC supply voltage
Reverse DC supply voltage
DC reverse ground pin current
I
OUT
-I
OUT
I
IN
DC output current
Reverse DC output current
DC input current
I
FR_Stby
Fault reset standby DC input current
-I
CSENSE
DC reverse CS pin current
V
CSENSE
Current sense maximum voltage
E
MAX
Maximum switching energy
(L = 2.3 mH; V
BAT
= 32 V; T jstart
= 150 °C; I
OUT
= I limL (typ)
)
Value
58
0.3
200
Unit
V
V mA
Internally limited A
40 A
-1 to 10
-1 to 1.5
mA mA
200
V
CC
- 58 to
+V
CC mA
V
250 mJ
Doc ID 018942 Rev 5 7/31
Electrical specifications
Table 3.
Symbol
L smax
V
ESD
V
ESD
Absolute maximum ratings (continued)
Parameter
Maximum strain inductance in short circuit condition
R
L
= 300 m Ω , V
BAT
= 32 V, T jstart
= 150 °C, l
OUT
= I
LMHmax
Electrostatic discharge
(Human Body Model: R = 1.5 K Ω; C = 100 pF)
– IN
1,2
– CS
1,2
– FR_Stby
– OUT
1,2
– V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature T j
T stg
Storage temperature
VND5T035AK-E
Value Unit
40 µH
4000
2000
4000
5000
5000
750
-40 to 150
-55 to 150
°C
°C
V
V
V
V
V
V
Table 4.
Symbol
Thermal data
Parameter Value Unit
R thj-case
R thj-amb
Thermal resistance junction-case (max) (with one channel ON)
Thermal resistance junction-ambient (max)
2 °C/W
°C/W
8/31 Doc ID 018942 Rev 5
VND5T035AK-E Electrical specifications
8 V < V
CC
< 36 V; -40 °C < T j
< 150 °C, unless otherwise specified.
Table 5.
Symbol
Power section
Parameter Test conditions
V
V
V
CC
USD
USDhyst
Operating supply voltage
Undervoltage shutdown
Undervoltage shutdown hysteresis
V
I
R
I
ON clamp
S
L(off)
On-state resistance
Clamp voltage
Supply current
(1)
Off-state output current
I
OUT
= 3 A; T j
= 25°C
I
OUT
= 3 A; T j
= 150°C
I
S
= 20 mA
Off-state; V
V
IN
= V
OUT
CC
= V
= 24 V; T j
SENSE
= 25°C;
= 0 V
I
On-state; V
CC
OUT
= 0 A
= 24 V; V
IN
= 5 V;
V
IN
T j
= V
OUT
= 25°C
= 0 V; V
CC
= 24 V;
V
IN
T j
= V
OUT
= 125°C
= 0 V; V
CC
= 24 V;
V
F
Output - V
CC
diode voltage
1.
For each channel
2.
PowerMOS leakage included
-I
OUT
= 3 A; T j
= 150°C
Min. Typ.
Max.
Unit
8
58
24
3.5
0.5
35
64
2
(2)
4.2
0 0.01
0
36
5
70
70
5
(2)
6
3
5
0.7
V
V
V m Ω
V
µA mA
µA
V
Table 6.
Symbol
Switching (V
CC
= 24 V; T j
= 25 °C)
Parameter Test conditions t d(on) t d(off) dV
OUT
/dt
(on) dV
OUT
/dt
(off)
W
ON
W
OFF
Turn-on delay time
Turn-off delay time
Turn-on voltage slope
Turn-off voltage slope
R
L
= 8 Ω
R
L
= 8
Ω
R
L
= 8 Ω
R
L
= 8 Ω
Switching energy losses during t won
Switching energy losses during t woff
R
L
= 8 Ω
R
L
= 8 Ω
Min.
Typ. Max. Unit
46
54
0.55
0.46
µs
µs
V/µs
V/µs
1 mJ
0.65
mJ
Doc ID 018942 Rev 5 9/31
Electrical specifications VND5T035AK-E
Table 7.
Symbol
Logic inputs
Parameter Test conditions
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
V
V
IN
IN
= 0.9 V
= 2.1 V
V
ICL
Input clamp voltage
I
IN
= 1 mA
I
IN
= -1 mA
V
FR_Stby_L
Fault_reset_standby low level voltage
I
FR_Stby_L
V
FR_Stby_H
Low level fault_reset_standby current
Fault_reset_standby high level voltage
V
FR_Stby
= 0.9 V
I
FR_Stby_H
High level fault_reset_standby current
V
FR_Stby
= 2.1 V
V
FR_Stby
(hyst)
Fault_reset_standby hysteresis voltage
V
FR_Stby_CL
Fault_reset_standby clamp voltage
I
FR_Stby
= 15 mA (10 ms)
I
FR_Stby
= -1 mA
Overload latch-off reset time See Figure 4
t reset t stby
Standby delay
Figure 4.
Treset definition
Min.
Typ. Max. Unit
0.9
1
2.1
0.25
5.5
-0.7
10
7
µA
V
V
V
V
µA
V
0.9
V
1
2.1
µA
V
10 µA
0.25
V
11
2
120
-0.7
15
24 µs
1200 µs
V
V
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10/31 Doc ID 018942 Rev 5
VND5T035AK-E
Figure 5.
Tstby definition
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Table 8.
Symbol
Protections and diagnostics
Parameter Test conditions Min.
Typ.
Max.
Unit
I
I limH limL
DC short circuit current
V
CC
= 24V
5 V < V
CC
< 36 V
Short circuit current during thermal cycling
V
CC
= 24 V; T
R
< T j
< T
TSD
T
TSD
T
R
T
RS
Shutdown temperature
Reset temperature
Thermal reset of status
T
HYST
Thermal hysteresis
(T
TSD
-T
R
)
V
DEMAG
Turn-off output voltage clamp
I
OUT
= 3 A; V
L = 6 mH
IN
= 0;
T
30
150
RS
+ 1 T
135
42
10.5
175
RS
7
+ 5
55
55
200
A
A
A
°C
°C
°C
°C
V
CC
- 58 V
CC
- 64 V
CC
- 70 V
V
ON
Output voltage drop limitation
I
T
OUT j
= 150 mA;
= -40°C...+150°C
25 mV
Doc ID 018942 Rev 5 11/31
Electrical specifications VND5T035AK-E
Table 9.
Symbol
I
V
V
I
K
K
K
1 dK
1
/K
1
(1)
2 dK
2
/K
2
(1)
3 dK
3
/K
3
(1)
SENSE0
SENSE
SENSEH
SENSEH
Current sense (8 V < V
CC
< 36 V)
Parameter Test conditions Min.
Typ.
Max.
Unit
I
I
I
OUT
/I
SENSE
Current sense ratio drift
OUT
/I
SENSE
Current sense ratio drift
OUT
/I
SENSE
Current sense ratio drift
I
OUT
= 1 A; V
SENSE
= 2 V;
T j
= -40°C...150°C
T j
= 25°C...150°C
I
OUT
= 1 A; V
SENSE
= 2 V;
T j
= -40°C to 150°C
I
OUT
= 3 A; V
SENSE
= 4 V;
T j
= -40°C...150°C
T j
= 25°C...150°C
I
OUT
= 3 A; V
SENSE
= 4 V;
T j
= -40°C to 150°C
I
OUT
= 12 A; V
SENSE
= 4 V;
T j
= -40°C...150°C
T j
= 25°C...150°C
I
OUT
= 12 A; V
SENSE
= 4 V;
T j
= -40°C to 150°C
1952
2080
-15
2490
2585
-10
2770
2755
-5
Analog sense leakage current
I
OUT
= 0 A; V
SENSE
= 0 V;
V
IN
= 0 V; T j
= -40°C...150°C
I
OUT
= 0 A; V
SENSE
= 0 V;
V
IN
= 5 V; T j
= -40°C...150°C
0
0
Max analog sense output voltage
I
OUT
= 12 A; R
SENSE
= 3.9 K Ω 5
Analog sense output voltage in fault condition
(2)
V
CC
= 24 V; R
SENSE
= 3.9 K Ω 7.5
Analog sense output current in fault condition
(2)
V
CC
= 24 V; V
SENSE
= 5 V 4.9
2960
4150
3840
2930
2900
8.5
9
15
3440
3265
+10
3125
3045
5
1
2
9.5
12
%
%
%
µA
µA
V
V mA t
DSENSE2H
Delay response time from rising edge of
INPUT pins
V
SENSE
< 4 V;
0.2 A < I
OUT
< 12 A;
I
SENSE
= 90 % of I
SENSE max
;
Δ t
DSENSE2H
Delay response time between rising edge of output current and rising edge of current sense t
DSENSE2L
Delay response time from falling edge of
INPUT pins
V
SENSE
< 4 V;
I
SENSE
= 90 % of I
SENSEMAX
;
I
OUT
= 90 % of I
I
OUTMAX
OUTMAX
;
)
V
SENSE
< 4 V;
0.2 A < I
OUT
I
SENSE
< 12 A;
= 10 % of I
(see
SENSE max
;
200
5
1.
Parameter guaranteed by design; it is not tested.
2.
Fault condition includes: power limitation, overtemperature and open load in off-state condition.
400
250
20
µs
µs
µs
12/31 Doc ID 018942 Rev 5
VND5T035AK-E Electrical specifications
Table 10.
Openload detection (V
FR_Stby
= 5 V)
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit
V
OL
Openload off-state voltage detection threshold
V
IN
= 0 V; 8 V < V
CC
< 36 V t
DSTKON
I
L(off2) td_vol
Output short circuit to
V
CC
detection delay at turn off t
DFRSTK_ON
Output short circuit to
V
CC
detection delay at
FRSTBY activation
Off-state output current at V
OUT
= 4V
Delay response from output rising edge to
V
SENSE rising edge in openload
V
IN
= 0 V; V
SENSE
= 0 V;
V
OUT rising from 0 V to 4 V
V
OUT
= 4 V; V
IN
V
SENSE
= 0 V;
= 90 % of V
SENSEH
R
SENSE
= 3.9 K
;
1,2
= low
2
180
-120
4
1800
0
20
50
V
µs
µA
µs
µs
Figure 6.
Current sense delay characteristics
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Openload off-state delay timing
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Doc ID 018942 Rev 5 13/31
Electrical specifications
Figure 8.
Switching characteristics
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Output stuck to VCC detection delay time at FRSTBY activation
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14/31 Doc ID 018942 Rev 5
VND5T035AK-E Electrical specifications
Figure 10. Delay response time between rising edge of ouput current and rising edge of current sense
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Doc ID 018942 Rev 5 15/31
Electrical specifications
Figure 12. Device behavior in overload condition
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Table 11.
Truth table
Conditions
Fault reset standby
Standby
Normal operation
Overload
Overtemperature / short to ground
Undervoltage
Short to V
BAT
Open load off-state
(with pull-up)
X
X
X
L
H
X
L
H
X
L
H
X
L
X
X
Negative output voltage clamp
X
Input
L
H
L
H
H
X
L
L
H
L
L
H
L
L
H
L
Output
L
H
L
Cycling
Latched
L
H
H
H
H
H
H
L
L
H
Negative
16/31 Doc ID 018942 Rev 5
VND5T035AK-E
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0
0
Nominal
0
> Nominal
0
V
SENSEH
V
SENSEH
0
0
V
SENSEH
< Nominal
0
V
SENSEH
0
0
VND5T035AK-E Electrical specifications
Table 12.
Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test pulse
Test levels
(1)
III IV
Number of pulses or test times
Burst cycle/pulse repetition time
1
2a
3a
- 450 V
+ 37 V
- 150 V
- 600 V
+ 50 V
- 200 V
5000 pulses
5000 pulses
1h
0.5 s
0.2 s
90 ms
5 s
5 s
100 ms
3b + 150 V + 200 V 1h 90 ms
4
5b
(1)
- 12 V
+ 123 V
- 16 V
+ 174 V
1 pulse
1 pulse
1.
Valid in case of external load dump clamp: 58 V maximum referred to ground.
100 ms
Delays and impedance
1 ms, 50 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01
Ω
350 ms, 1 Ω
Table 13.
Electrical transient requirements (part 2) (1)
ISO 7637-2:
2004(E)
Test pulse III
Test level results
IV
1
2a
C
C
C
C
3a
3b
(2)
3b
(3)
C
E
C
E
C C
4
5b
(4)
C C
C C
1.
In order to guarantee the ISO transient classes a minimum 10K
Ω
protection resistors are needed on logic pins
2.
Without capacitor between V
CC
and GND.
3.
With 10 nF between V
CC
and GND.
4.
External load dump clamp, 58 V maximum, referred to ground.
Table 14.
Electrical transient requirements (part 3)
Class Contents
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 018942 Rev 5 17/31
Electrical specifications
Figure 13. Off-state output current
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VND5T035AK-E
Figure 14. High-level input current
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Figure 15. Input clamp voltage
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Figure 16. High-level input voltage
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,LQ P$
7F> &@
Figure 17. Low-level input voltage
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Figure 18. Input hysteresis voltage
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18/31
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Doc ID 018942 Rev 5
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VND5T035AK-E Electrical specifications
Figure 19. On-state resistance vs T case
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Figure 20. On-state resistance vs V
CC
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7F &
7F &
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Figure 21. I
LIMH
vs T case
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Figure 22. Turn-on voltage slope
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Figure 23. Turn-off voltage slope
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Doc ID 018942 Rev 5 19/31
Application information VND5T035AK-E
Figure 24. Application schematic
9
0&8
5
SURW
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5
SURW
5
SURW
&
H[W
5
6(16(
,1
&6
9
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OG
9
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287
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3.1 GND protection network against reverse battery
resistor in the ground line (R
GND
only)
This solution can be used with any type of load.
The following is an indication on how to dimension the R
GND resistor.
1.
R
GND
≤ 600 mV / (I
S(on)max
).
2. R
GND
≥ (−
V
CC
) / (-I
GND
) where -I
GND
is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power dissipation in R
GND
(when V
CC
< 0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/ R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND produces a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in case of several high side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests Solution 2 is used (see below).
20/31 Doc ID 018942 Rev 5
VND5T035AK-E
3.1.2 Solution 2: diode (D
GND
) in the ground line
Application information
A resistor (R
GND inductive load.
= 4.7 k
Ω) should be inserted in parallel to D
GND
if the device drives an
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (
≈
600 mV) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.
D ld
is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
V
CC
maximum DC rating. The same applies if the device is subject to transients on the V
CC line that are greater than the ones shown in the ISO T/R 7637/2 table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient is present on the V
CC
line, the control pins are pulled negative. ST suggests that a resistor (R prot
) have to be inserted in line to prevent the microcontroller I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of the microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
-V
CCpeak
/I latchup
≤
R prot
≤
(V
OH
μ
C
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= -600 V and I latchup
≥
20 mA; V
OH
μ
C
≥
4.5 V
30 k
Ω ≤
R prot
≤
180 k
Ω
.
Recommended R prot value is 60 k
Ω.
Doc ID 018942 Rev 5 21/31
Application information
3.4 Maximum demagnetization energy (V
CC
= 24 V)
Figure 25. Maximum turn-off current versus inductance
VND5T035AK-E
&
%
9
,1
,
/
A: T jstart
= 150°C single pulse
B: T jstart
= 100°C repetitive pulse
C: T jstart
= 125°C repetitive pulse
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Values are generated with R
L
=0
Ω
. In case of repetitive pulses, T jstart
(at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
22/31 Doc ID 018942 Rev 5
VND5T035AK-E
4 Package and PCB thermal data
Package and PCB thermal data
4.1 PowerSSO-24 thermal data
Figure 26. PowerSSO-24 PC board
.
("1($'5
1.
Layout condition of R th
and Z minimum pad lay-out to 8 cm th
2
).
measurements (PCB: double layer, thermal vias, FR4 area = 77 mm x
86 mm, PCB thickness = 1.6 mm, Cu thickness = 70
μ m (front and back side), Copper areas: from
Figure 27. R thj-amb
vs PCB copper area in open box free air condition (one channel ON)
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7+MBDPE
&:
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*$3*&)7
Doc ID 018942 Rev 5 23/31
Package and PCB thermal data VND5T035AK-E
Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)
=
7+
&:
$
%
&
A : Cu = Footprint B
7LPHV
: Cu = 2 cm
2
*$3*&)7
C : Cu = 8 cm
2
Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24
("1($'5
1.
The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered
24/31 Doc ID 018942 Rev 5
VND5T035AK-E
Equation 1: Pulse calculation formula
Z
TH δ
= R
TH
⋅ δ
+ Z
THtp
(
1 –
δ ) where δ = t
P
/T
Table 15.
Thermal parameters
Area/island (cm
2
)
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
R7 (°C/W)
R8 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
C7 (W.s/°C)
C8 (W.s/°C)
Footprint
0,5
0.75
1
7.7
9
28
0,5
0.75
0,005
0,05
0,1
0,5
1
2.2
0,005
0,05
Package and PCB thermal data
17
—
—
—
—
2
—
—
—
—
9
—
—
4
5
—
—
10
—
—
—
—
8
—
—
—
—
8
—
—
9
17
—
—
Doc ID 018942 Rev 5 25/31
Package and packing information
5 Package and packing information
VND5T035AK-E
5.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 30. PowerSSO-24 package dimensions
26/31 Doc ID 018942 Rev 5
VND5T035AK-E
Table 16.
PowerSSO-24 mechanical data
Symbol
H h k
L
N e3
G
G1
X
Y
E e c
D
A
A2 a1 b
Min.
2.15
2.15
0
0.33
0.23
10.10
7.4
10.1
0.55
4.1
6.5
Package and packing information
Millimeters
Typ.
0.8
8.8
5º
0.85
10º
4.7
7.1
0.1
0.06
10.5
0.4
Max.
2.47
2.40
0.075
0.51
0.32
10.50
7.6
Doc ID 018942 Rev 5 27/31
Package and packing information
5.3 PowerSSO-24 packing information
Figure 31. PowerSSO-24 tube shipment (no suffix)
C
B
A
GAPGCFT00002
Base Q.ty
Bulk Q.ty
49
1225
Tube length (± 0.5) 532
A 3.5
B
C (± 0.1)
13.8
0.6
All dimensions are in mm.
VND5T035AK-E
Figure 32. PowerSSO-24 tape and reel shipment (suffix “TR”)
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6WDUW
1RFRPSRQHQWV &RPSRQHQWV 1RFRPSRQHQWV
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VDOHGZLWKFRYHUWDSH
8VHUGLUHFWLRQRIIHHG
("1($'5
28/31 Doc ID 018942 Rev 5
VND5T035AK-E Order codes
Table 17.
Device summary
Package
PowerSSO-24
Tube
VND5T035AK-E
Order codes
Tape and reel
VND5T035AKTR-E
Doc ID 018942 Rev 5 29/31
Revision history VND5T035AK-E
Table 18.
Document revision history
Date
21-Sep-2011
19-Oct-2011
26-Oct-2011
13-Mar-2012
18-Sep-2013
Revision
1
2
3
4
5
Changes
Initial release.
Updated
Table 2: Suggested connections for unused and not connected pins
Added note on Table 13: Electrical transient requirements (part 2)
Changed document status from preliminary data to definitive datasheet
Updated
Figure 13: Off-state output current
Updated
Section 3.4: Maximum demagnetization energy (V
Updated Disclaimer
30/31 Doc ID 018942 Rev 5
VND5T035AK-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
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OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
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DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
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Information in this document supersedes and replaces all information previously supplied.
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Doc ID 018942 Rev 5 31/31
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