STF5N65M6
N-channel 650 V, 1.15
Ω typ., 4 A MDmesh™ M6
Power MOSFET in a TO-220FP package
Datasheet - production data
TO-220FP
Figure 1: Internal schematic diagram
D(2)
G(1)
Order code
STF5N65M6
S(3)
Features
Order code V
DS
R
DS(on)
max. I
D
STF5N65M6 650 V 1.3 Ω 4 A
Reduced switching losses
Lower R
DS(on)
x area vs previous generation
Low gate input resistance
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ
MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent
R
DS(on)
* area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum endapplication efficiency.
AM15572v1_no_tab
Table 1: Device summary
Marking Package
5N65M6 TO-220FP
Packing
Tube
May 2016 DocID029232 Rev 1
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STF5N65M6
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
TO-220FP package information ...................................................... 10
5 Revision history ............................................................................ 12
2/13 DocID029232 Rev 1
STF5N65M6
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
Gate-source voltage
I
D
Drain current (continuous) at T
C
= 25 °C
I
D
Drain current (continuous) at T
C
= 100 °C
I
DM
(1)
Drain current (pulsed)
P
TOT
Total dissipation at T
C
= 25 °C
dv/dt (2)
Peak diode recovery voltage slope
dv/dt (3)
MOSFET dv/dt ruggedness
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s, T
C
= 25 °C)
T
J
T stg
Operating junction temperature range
Storage temperature range
Value
± 25
4
2.5
16
20
5
50
2.5
-55 to 150
Unit
V
A
A
A
W
V/ns kV
°C
Notes:
(1)
Pulse width limited by safe operating area
(2)
I
SD
≤ 4 A, di/dt = 400 A/μs; V
DS peak
< V
(BR)DSS
, V
DD
= 400 V
(3)
V
DS
≤ 520 V
Symbol
Table 3: Thermal data
Parameter Value Unit
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
6.25
62.5
Symbol
I
AR
E as
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
=25°C, I
D
= I
AR
, V
DD
=50 V)
°C/W
Value Unit
1
90
A mJ
DocID029232 Rev 1 3/13
Electrical characteristics
2 Electrical characteristics
STF5N65M6
T
C
= 25 °C unless otherwise specified
Symbol Parameter
Table 5: On/off-state
Test conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0, I
D
= 1 mA
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Zero gate voltage drain current
Gate body leakage current
Gate threshold voltage
Static drain-source on-resistance
V
GS
= 0 V, V
DS
= 650 V
V
GS
= 0 V, V
DS
= 650 V;
T
C
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±25 V
V
V
DS
GS
= V
GS
, I
D
= 10 V, I
= 250 µA
D
= 2 A
650
2.25 3
1.15
100
±5
V
µA
µA
µA
3.75 V
1.3 Ω
1
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions Min. Typ. Max. Unit
C iss
C oss
C rss
C oss
eq.
(1)
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz, V
GS
= 0 V
V
DS
= 0 to 520 V, V
GS
= 0 V f = 1 MHz, I
D
=0 A
V
DD
= 350 V, I
D
= 1 A, V
GS
= 10 V,
(see Figure 15: "Test circuit for gate charge behavior" )
-
-
-
-
-
-
-
-
170
20
1
35
5
5.1
0.8
2
-
-
-
-
-
-
-
- pF pF pF pF
Ω nC nC nC
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DD
= 325 V, I
D
= 2 A, R
G
= 4.7 Ω,
V
GS
= 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform" )
-
-
-
-
6.5
5.9
17.4
15.2
-
-
-
- ns ns ns ns
4/13 DocID029232 Rev 1
STF5N65M6
Symbol Parameter
Table 8: Source-drain diode
Test conditions
I
SD
Source-drain current
I
SDM
(1)
Source-drain current (pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
I
RRM t rr
Q rr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
I
RRM
Reverse recovery current
I
I
V
I
V
SD
SD
DD
SD
DD
= 4 A, V
GS
= 0 V
= 4 A, di/dt = 100 A/µs,
= 60 V, (see
= 4 A, di/dt = 100 A/µs,
= 60 V, T
(see
j
= 150 °C
Figure 19: "Switching time waveform" )
Figure 19:
"Switching time waveform" )
Electrical characteristics
-
-
-
-
-
-
-
-
Min. Typ. Max. Unit
4
16
1.6
222
1.24
11.2
264
1.39 ns
µC
A ns
µC
A
A
V
- 10.5 A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DocID029232 Rev 1 5/13
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STF5N65M6
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/13 DocID029232 Rev 1
STF5N65M6
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Normalized V(BR)DSS vs temperature
Figure 12: Output capacitance stored energy
Figure 13: Source-drain diode forward characteristics
DocID029232 Rev 1 7/13
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STF5N65M6
Figure 15: Test circuit for gate charge behavior
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
8/13
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
DocID029232 Rev 1
STF5N65M6
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID029232 Rev 1 9/13
Package information
4.1 TO-220FP package information
Figure 20: TO-220FP package outline
STF5N65M6
10/13 DocID029232 Rev 1
STF5N65M6
Dim.
G1
H
L2
L3
L4
L5
L6
L7
Dia
F
F1
F2
G
A
B
D
E
Table 9: TO-220FP package mechanical data mm
Min. Typ.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
28.6
9.8
2.9
15.9
9
3
Package information
Max.
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
DocID029232 Rev 1 11/13
Revision history
5
STF5N65M6
Revision history
Date
05-May-2016
Table 10: Document revision history
Revision
1
Changes
Initial release.
12/13 DocID029232 Rev 1
STF5N65M6
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DocID029232 Rev 1 13/13
