STF7N65M6
Datasheet
N-channel 650 V, 0.91 Ω typ., 5 A, MDmesh™ M6 Power MOSFET in a TO
‑
220FP package
G(1)
TO-220FP
D(2)
S(3)
1
2
3
Features
Order code
STF7N65M6
V
DS
650 V
R
DS(on)
max.
0.99 Ω
• Reduced switching losses
• Lower R
DS(on)
per area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
Applications
• Switching applications
I
D
5 A
AM15572v1_no_tab
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs.
STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R
DS(on)
per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency.
Product status link
STF7N65M6
Product summary
Order code STF7N65M6
Marking
Package
Packing
7N65M6
TO-220FP
Tube
DS11822 - Rev 2 - October 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STF7N65M6
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
I
D
I
D
I
DM
(1)
P
TOT
dv/dt (2) dv/dt (3)
Gate-source voltage
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
Total power dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Parameter
= 25 °C
= 100 °C
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink
(t = 1 s, T
C
= 25 °C)
Operating junction temperature range T
J
T stg
Storage temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 5 A, di/dt = 400 A/μs, V
DS peak
< V
(BR)DSS
, V
DD
= 400 V
3. V
DS
≤ 520 V
Symbol
R thj-case
R thj-amb
Table 2. Thermal data
Thermal resistance junction-case
Parameter
Thermal resistance junction-ambient
Value
±25
5
3.2
20
20
5
50
2.5
-55 to 150
Value
6.25
62.5
Unit
°C/W
Unit
V
A
A
A
W
V/ns kV
°C
Symbol
I
AR
E as
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax.
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
1.5
95
Unit
A mJ
DS11822 - Rev 2 page 2/13
2
STF7N65M6
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 4. On/off state
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 650 V
Zero gate voltage drain current
Gate body leakage current
V
GS
= 0 V, V
DS
= 650 V,
T
C
= 125 °C
(1)
V
DS
= 0 V, V
GS
= ±25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 2.5 A
1. Defined by design, not subject to production test.
Min.
650
Typ.
Max.
1
Unit
V
µA
2.25
3
0.91
100
±5
3.75
0.99
µA
µA
V
Ω
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
(1)
R
Q
Q
Q
G g gs gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
V
DS
= 0 to 520 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 520 V, I
D
= 5 A,
V
GS
= 0 to 10 V
(see
Figure 14. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
-
-
Typ.
220
25
1.1
45
6.3
6.9
1.3
3.1
Max.
-
-
-
-
-
-
-
-
Unit pF pF pF pF
Ω nC nC nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss to 80% V
DSS
.
when V
DS
increases from 0
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 325 V, I
D
= 2.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 13. Test circuit for resistive load switching times and
Figure 18. Switching time waveform
)
Min.
-
-
-
-
Typ.
6.5
4.5
21.4
12.4
Max.
-
-
-
-
Unit ns ns ns ns
DS11822 - Rev 2 page 3/13
STF7N65M6
Electrical characteristics
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 7. Source-drain diode
Test conditions
I
SD
= 5 A, V
GS
= 0 V
I
SD
= 5 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 5 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
Min.
-
-
-
-
-
-
-
-
11.8
234
1.2
10.8
Typ.
Max.
5
20
1.6
171
1
Unit
A
A
V ns
µC
A ns
µC
A
DS11822 - Rev 2 page 4/13
STF7N65M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GIPG130920161403SOA
10 1
Operation in this area is limited by R
DS(on)
10 0
10 -1 t p
=10 µs t p
=100 µs t p
=1 ms t p
=10 ms
10 -2
10 -1 single pulse
T
J
T
C
V
≤ 150 °C
= 25 °C
GS
=10 V
10 0 10 1 10 2
V
DS
(V)
I
D
(A)
Figure 3. Output characteristics
GIPG290720160921OCH
8 V
GS
= 6 V
6
V
GS
=5 V
4
2
0
0 2 4 6
V
GS
= 4 V
8 10 12 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
V
DS
10
GIPG020820160837QVG V
DS
(V)
600
500
V
DD
= 520 V
I
D
= 5 A
8 400
6
4
300
200
2
0
0 1 2 3 4 5 6 7 8
100
Q
0 g
(nC)
K
Figure 2. Thermal impedance
GC20940
10 -1
10 -2
10 -3
10 -4 10 -3 10 -2 10 -1 10 0 t p
(s)
4
2
0
0
I
D
(A)
Figure 4. Transfer characteristics
GIPG290720161033TCH
V
DS
=14 V
8
6
2 4 6 8 V
GS
(V)
Figure 6. Static drain-source on-resistance
GIPG290720161116RID
Ω
0.97
V
GS
=10 V
0.95
0.93
0.91
0.89
0.87
0.85
0 1 2 3 4 5 I
C
(A)
DS11822 - Rev 2 page 5/13
STF7N65M6
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GIPG290720161128CVR
10 3
C
ISS
10 2
10 1
C
OSS f = 1 MHz
C
RSS
10 0
10 -1
10 -1 10 0 10 1 10 2
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
GIPG290720161206RON
V
GS
=10 V
2.2
1.8
1.4
1
0.6
0.2
-75 -25 25 75 125 °
Figure 11. Output capacitance stored energy
GIPG290720161227EOS E
(μJ)
2.4
2
1.6
1.2
0.8
0.4
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GIPG290720161143VTH
I
D
=250 µA
1.1
1
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T
J
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GIPG290720161215BDV
1.08
I
D
= 1 mA
1.04
1
0.96
0.92
0.88
-75 -25 25 75 125 °
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.1
GIPG290720161328SDF
T j
= 50 °C
Tj = 25 °C
1
0.9
0.8
0.7
T j
= 150 °C
0.6
0.5
0 1 2 3 4 5 I
SD
(A)
DS11822 - Rev 2 page 6/13
STF7N65M6
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
I
G
= CONST
2.7 kΩ
47 kΩ
1 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF
+
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS11822 - Rev 2 page 7/13
4
STF7N65M6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS11822 - Rev 2 page 8/13
4.1
TO-220FP package information
Figure 19. TO-220FP package outline
STF7N65M6
TO-220FP package information
DS11822 - Rev 2
7012510_Rev_12_B page 9/13
DS11822 - Rev 2
Dim.
F2
G
G1
H
L2
L3
L4
L5
L6
L7
Dia
D
E
A
B
F
F1
Table 8. TO-220FP package mechanical data mm
Typ.
Min.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
28.6
9.8
2.9
15.9
9
3
STF7N65M6
TO-220FP package information
Max.
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
page 10/13
Revision history
Date
15-Sep-2016
16-Oct-2018 2
Table 9. Document revision history
Revision
1
Changes
Initial release.
Updated Figure 14. Test circuit for gate charge behavior .
Minor text changes
STF7N65M6
DS11822 - Rev 2 page 11/13
STF7N65M6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DS11822 - Rev 2 page 12/13
STF7N65M6
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DS11822 - Rev 2 page 13/13
