STMicroelectronics STF25N60M2-EP Datasheet
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STF25N60M2-EP
Datasheet
N-channel 600 V, 0.175 Ω typ., 18 A MDmesh™ M2 EP
Power MOSFET in a TO-220FP package
G(1)
TO-220FP
D(2)
1
2
3
Features
Order code
STF25N60M2-EP
V
DS
at T
J
max.
650 V
• Extremely low gate charge
• Excellent output capacitance (C
OSS
) profile
• Very low turn-off switching losses
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
0.188 Ω
Applications
• Switching applications
• Tailored for Very high frequency converters (f > 150 kHz)
I
D
18 A
S(3)
AM15572v1_no_tab
Description
This device is an N-channel Power MOSFET developed using MDmesh™
M2 enhanced performance (EP) technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance, optimized switching characteristics with very low turn-off switching losses, rendering it suitable for the most demanding very high frequency converters.
Product status link
STF25N60M2-EP
Product summary
Order code STF25N60M2-EP
Marking
Package
Packing
25N60M2EP
TO-220FP
Tube
DS10758 - Rev 6 - May 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STF25N60M2-EP
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
V
GS
I
D
I
D
I
DM
P
TOT
Gate-source voltage
Transient gate-source voltage (t
Drain current (continuous) at T
Drain current (continuous) at T
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
C
C p
≤ 10 ns)
= 25 °C
= 100 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Parameter
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink
(t = 1 s, T
C
= 25 °C)
Storage temperature range T stg
T j
Operating junction temperature range
1. Limited by maximum junction temperature
2. Pulse width limited by safe operating area
3. I
SD
≤ 18 A, di/dt ≤ 400 A/µs, V
DS peak
< V
(BR)DSS
, V
DD
= 400 V
4. V
DS
≤ 480 V
Symbol
R thj-case
R thj-amb
Table 2. Thermal data
Parameter
Thermal resistance junction-case
Thermal resistance junction-ambient
11.3
72
30
15
50
Value
±25
±35
18
2500
-55 to 150
Value
4.2
62.5
Unit
°C/W
°C/W
A
A
W
V/ns
V/ns
Unit
V
V
A
V
°C
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
3.5
200
Unit
A mJ
DS10758 - Rev 6 page 2/14
2
STF25N60M2-EP
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 4. On/off states
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 600 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 600 V,
T
C
Gate-body leakage current
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±25 V
V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 9 A
1. Defined by design, not subject to production test.
Min.
600
3.25
Typ.
Max.
1
100
4
±10
4.75
0.175
0.188
Unit
V
µA
µA
µA
V
Ω
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
R
Q
Q
Q
G g gs gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
V
DS
= 0 to 480 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 480 V, I
D
= 18 A,
V
GS
= 0 to 10 V
(see
Figure 15. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
-
-
Typ.
1090
56
1.6
255
7
29
6
12
Max.
-
-
-
-
-
-
-
-
Unit pF pF pF pF
Ω nC nC nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS
increases from 0 to 80% V
DSS
.
Symbol
E
(off)
Parameter
Turn-off energy
(from 90% V
GS
to 0% I
D
)
Table 6. Switching energy
Test conditions
V
DD
= 400 V, I
D
= 2 A,
R
G
= 4.7 Ω, V
GS
= 10 V
V
DD
= 400 V, I
D
= 4 A,
R
G
= 4.7 Ω, V
GS
= 10 V
Min.
-
Typ.
Max.
Unit
7 µJ
8 µJ
DS10758 - Rev 6 page 3/14
DS10758 - Rev 6
STF25N60M2-EP
Electrical characteristics
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 7. Switching times
Test conditions
V
DD
= 300 V, I
D
= 9 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 14. Test circuit for resistive load switching times and
Figure 19. Switching time waveform
)
Min.
-
-
-
-
Typ.
15
10
61
16
Max.
-
-
-
-
Unit ns ns ns ns
Symbol
I
SD
I
SDM
V
SD
t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 8. Source drain diode
Test conditions
V
GS
= 0 V, I
SD
= 18 A
I
SD
= 18 A, di/dt = 100 A/µs,
V
DD
= 100 V (see
Figure 16. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 18 A, di/dt = 100 A/µs,
V
DD
= 100 V, T j
= 150 °C
(see
Figure 16. Test circuit for inductive load switching and diode recovery times
)
1. Pulse width is limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
-
-
-
-
-
-
Min.
-
-
-
360
5
28
445
6.5
29
Typ.
Max.
18
72
1.6
Unit
A
A
V ns
µC
A ns
µC
A page 4/14
STF25N60M2-EP
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A)
Operation in this area is limited by R
DS(on)
GADG250520181324SOA
10 1
10 0
Single pulse, T
C
T
= 25 °C,
J
≤ 150 °C, V
GS
= 10 V t p
=10 µs t p
=100 µs t p
=1 ms t p
=10 ms
10 -1
10 -1 10 0 10 1 10 2
V
DS
(V)
24
16
8
0
0
I
D
(A)
40
Figure 3. Output characteristics
GIPG090220181022OCH
V
GS
= 8, 9, 10 V
V
GS
=7 V
32
4 8
V
GS
=6 V
12
V
GS
=5 V
16 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
10
V
DS
GADG260320181223QVG V
DS
(V)
V
DD
= 480 V, I
D
= 18 A
600
500
4
2
0
0
8
6
5
400
300
10 15 20 25 30
200
100
Q
0 g
(nC)
Figure 2. Thermal impedance
24
16
8
0
3
I
D
(A)
40
Figure 4. Transfer characteristics
V
DS
=16 V
GIPG090220181022TCH
32
4 5 6 7 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
GIPG090220181138RID
V
GS
= 10 V
0.185
0.18
0.175
0.17
0.165
0 3 6 9 12 15 18 I
D
(A)
DS10758 - Rev 6 page 5/14
C
(pF)
Figure 7. Capacitance variations
GIPG090220181022CVR
10 3
C iss
10 2
C oss
10 1 f = 1 MHz
10 0
10 -1 10 0 10 1 10 2
C rss
V
DS
(V)
Figure 9. Turn-off switching energy vs drain current
E off
(µJ)
14
V
DD
= 400 V
R
G
= 4.7Ω
V
GS
= 10V
GADG260320181227TSL
12
10
8
6
4
2
0 1 2 3 4 5 6 I
D
(A)
Figure 11. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.5
V
GS
= 10 V
GIPG090220181019RON
2.0
1.5
1.0
0.5
0.0
-75 -25 25 75 125 T j
(°C)
STF25N60M2-EP
Electrical characteristics (curves)
Figure 8. Output capacitance stored energy
E
OSS
(µJ)
GIPG090220181024EOS
8
6
4
2
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 10. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
1.1
GIPG090220181018VTH
I
D
= 250 µA
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T j
(°C)
Figure 12. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
1.10
I
D
= 1 mA
GIPG090220181020BDV
1.05
1.00
0.95
0.90
0.85
-75 -25 25 75 125 T j
(°C)
DS10758 - Rev 6 page 6/14
Figure 13. Source-drain diode forward characteristics
V
SD
(V)
1.1
GIPG090220181021SDF
T j
= -50 °C
1.0
0.9
0.8
0.7
0.6
0.5
0 3 6
T j
= 25 °C
T j
= 150 °C
9 12 15 18 I
SD
(A)
STF25N60M2-EP
Electrical characteristics (curves)
DS10758 - Rev 6 page 7/14
STF25N60M2-EP
Test circuits
3
Test circuits
Figure 14. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 16. Test circuit for inductive load switching and diode recovery times
Figure 15. Test circuit for gate charge behavior
V
GS pulse width
2200
μF
+
1 kΩ
12 V
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 17. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 18. Unclamped inductive waveform
V
(BR)DSS
V
D
I DM
I D
V
DD V DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
Figure 19. Switching time waveform
0 t d(on) t on t r
90%
10%
V
GS
V
DS
90% t d(off) t off t f
90%
10%
0 10%
AM01473v1
DS10758 - Rev 6 page 8/14
4
STF25N60M2-EP
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS10758 - Rev 6 page 9/14
4.1
TO-220FP package information
Figure 20. TO-220FP package outline
STF25N60M2-EP
TO-220FP package information
DS10758 - Rev 6
7012510_Rev_12_B page 10/14
DS10758 - Rev 6
Dim.
F2
G
G1
H
L2
L3
L4
L5
L6
L7
Dia
D
E
A
B
F
F1
Table 9. TO-220FP package mechanical data mm
Typ.
Min.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
28.6
9.8
2.9
15.9
9
3
STF25N60M2-EP
TO-220FP package information
Max.
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
page 11/14
STF25N60M2-EP
Revision history
Date
02-Dec-2014
12-Jan-2015
14-Jan-2015
25-Aug-2016
13-Feb-2018
28-May-2018
4
5
6
Table 10. Document revision history
Revision
1
2
3
Changes
First release.
Updated product status from “preliminary data” to “production data”.
Corrected product status information on cover page.
Modified: Table 2: "Absolute maximum ratings"
Minor text changes
Removed maturity status indication from cover page.
Modified Table 1. Absolute maximum ratings , Table 4. On/off states , Table 5.
Dynamic , Table 6. Switching Energy , Table 7. Switching times and Table 8.
Source drain diode .
Updated Section 2.1 Electrical characteristics (curves).
Minor text changes.
Updated Table 1. Absolute maximum ratings
.
Updated Section 2 Electrical characteristics
and Section 2.1 Electrical characteristics (curves) .
Minor text changes
DS10758 - Rev 6 page 12/14
STF25N60M2-EP
Contents
Contents
DS10758 - Rev 6 page 13/14
STF25N60M2-EP
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DS10758 - Rev 6 page 14/14
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