STMicroelectronics VNI4140K-32 Datasheet
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Product status
VNI4140K
VNI4140K-32
Product label
VNI4140K, VNI4140K-32
Datasheet
Quad high-side smart power solid-state relay
Features
• Operating output current: 0.6 A (VNI4140K) or 1.0 A (VNI4140K-32) per channel
• Per channel short-circuit protection
• Per channel overtemperature protection
• Thermal case protection
• Not simultaneous channel reactivation at Thermal case reset
• All type of loads (resistive, capacitive, inductive load) are driven
• Loss of GND protection
• Undervoltage shutdown with hysteresis
• Overvoltage protection (V
CC
clamping)
• Very low supply current
• Per channel open drain thermal fault pins
• 5 V and 3.3 V compatible I/Os
• Fast demagnetization of inductive loads
• Designed to meet IEC61131-2, IEC61000-4-4, and IEC61000-4-5
• ESD according to IEC 61000-4-2 up to ±25 kV
Applications
• Programmable logic control
• Industrial PC peripheral input/output
• Numerical control machines
Description
The VNI414K (for loads up to 0.6 A) and VNI4140K-32 (for loads up to 1.0 A) are monolithic 4-channel drivers featuring very low R
DS(on)
and per-channel diagnostic.
The ICs, realized in STMicroelectronics™ VIPower™ technology, are intended to drive any kind of load with one side connected to ground.
Active channel current limitation combined with thermal shutdown, independent for each channel, and automatic restart, protect the device against overload.
A channel in an overload condition overheats and turns OFF and back ON automatically in order to maintain its junction temperature between T
TSD
and T
R
.
If this condition makes case temperature reach T
CSD
, the overloaded channel is turned OFF and restarts only when case temperature has decreased down to T
CR
. In case of more than one channel in overload, restart of the overloaded channels is not simultaneous, in order to avoid high peak current from the supply. Non-overloaded
(non-overheated) channels continue operating normally.
The four open drain STATUS
X
output pins indicate per-channel overtemperature conditions.
DS13837 - Rev 1 - October 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1
Block diagram
Figure 1. Block diagram
VNI4140K, VNI4140K-32
Block diagram
DS13837 - Rev 1 page 2/29
2
Pin connection
Figure 2. Pin connection (top view)
VNI4140K, VNI4140K-32
Pin connection
DS13837 - Rev 1
Pin
4
5
6
7
8
2
3
1,
TAB
VCC
16,
17,
18
19,
20,
21
22,
23,
24
9
13,
14,
15
STAT4
10 IN4
11, 12 NC
OUT4
OUT3
OUT2
OUT1
IN1
STAT1
IN2
STAT2
GND
STAT3
IN3
Name Type
Supply
Logic input
Output/Open Drain
Logic input
Output/Open Drain
Ground
Output/Open Drain
Logic input
Output/Open Drain
-
Logic input
Table 1. Pin description
Description
IC supply voltage.
Channel 1 input, 3.3 V CMOS/TTL compatible.
Channel 1 overtemperature status (active low).
Channel 2 input, 3.3 V CMOS/TTL compatible.
Channel 2 overtemperature status (active low).
Device ground connection.
Channel 3 overtemperature status (active low).
Channel 3 input, 3.3 V CMOS/TTL compatible.
Channel 4 overtemperature status (active low).
Channel 4 input, 3.3 V CMOS/TTL compatible.
Not connected.
Output Channel 4 power stage output, internally protected.
Output Channel 3 power stage output, internally protected.
Output
Output
Channel 2 power stage output, internally protected.
Channel 1 power stage output, internally protected.
page 3/29
3
VNI4140K, VNI4140K-32
Maximum ratings
Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
I
GND
I
OUT
I
R
I
IN
V
IN
V
STAT
I
STAT
V
ESD
Power supply voltage
DC ground reverse current
DC output current
DC reverse output current (per channel)
Input pin current (per channel)
Input pin voltage
Status pin voltage
Status pin current (per pin)
Electrostatic discharge (R = 1.5k Ω; C = 100 pF)
-0.3 to 41
-250
Internally limited
-5
+/-10
+V
+V
CC
CC
+/-10
2000
V mA
A
A mA
V
V mA
V
E
AS
P
TOT
T
J
T
STG
Single channel/single pulse avalanche energy @T amb
= 125 °C, I
OUT
=
0.5 A
Power dissipation at T
Junction operating temperature
Storage temperature
C
= 25 °C
5
Internally limited
Internally limited
-55 to 150
(1)
(1)
1. Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous operation.
Continuous and repetitive operation of protection functions may reduce the IC lifetime.
J
W
°C
°C
Symbol
R th(JC)
Table 3. Thermal data
Parameter
Thermal resistance junction-case (1)
R th(JA)
Thermal resistance junction-ambient
Value
2
See
TH(JA) vs. PCB copper area in open box free air condition (one channel ON)
Unit
°C/W
°C/W
1. per channel
DS13837 - Rev 1 page 4/29
4
Recommended operating conditions
Symbol
F
VIN(MAX)
Table 4. Input switching limits
Parameter
Maximum input switching frequency
VNI4140K, VNI4140K-32
Recommended operating conditions
Value
10
Unit kHz
DS13837 - Rev 1 page 5/29
5
5.1
5.2
VNI4140K, VNI4140K-32
Electrical characteristics
Electrical characteristics
10.5 V < V
CC
< 36 V; -40 °C < T
J
< 125 °C; unless otherwise specified
Power section
Table 5. Power section
Symbol
V
CC
Parameter
Supply voltage
Test conditions
I
I
I
R
S
V
V
DS(on)
CC clamp
OUT(OFF)
OUT(OFF)
LGND
ON-state resistance
VNI4140K,
I
OUT
= 0.5 A at T
J
= 25 °C
VNI4140K, I
OUT
= 0.5 A
VNI4140K-32,
I
OUT
= 0.7 A at T
J
= 25 °C
VNI4140K-32, I
OUT
= 0.7 A
All channels in OFF-state
V
CC
supply current
Clamp on V
CC
OFF-state output voltage
OFF-state output current
All channels in ON-state, with V
IN1..4
= 5 V
I
S
= 20 mA
V
IN
= 0 V, I
OUT
= 0 A
V
IN
= V
OUT
= 0 V
VNI4140K output current at
GND disconnection
VNI4140K-32 output current at GND disconnection
V
CC
V
= V
IN
OUT
= V
= 0 V
STAT
= V
GND
= 24 V;
F
CP
Charge pump frequency Channel in ON-state
1. To cover EN55022 class A and class B normative.
Switching
Symbol t
PD(L-H) t r t
PD(H-L) t f dV
(ON)
/dt r dV
(OFF)
/dt f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Turn-on voltage slope
Turn-off voltage slope
Table 6. Switching
Test conditions
V
CC
= 24 V, R
L
= 48 Ω, input rise time < 0.1 µs. See
Figure 4. Timing in normal operation
Min.
-
-
-
-
-
-
Typ.
16
8
21
4
2
4
Min.
10.5
Typ.
41
0
0.25
2.4
45
1.45
4
52
1
5
1.0
0.5
Max.
36
0.08
0.14
0.08
0.14
Unit
V
Ω mA mA
V
V
μA mA mA
MHz
Max.
35
25
36
12
-
-
Unit
µs
µs
µs
µs
V/µs
V/µs
DS13837 - Rev 1 page 6/29
Figure 3. Timing in normal operation
VNI4140K, VNI4140K-32
Logic inputs
5.3
Logic inputs
Table 7. Logic inputs
Symbol
V
IL
V
IH
V
I(HYST)
Parameter
Input low level voltage
Input high level voltage
Input hysteresis voltage
I
IN
Input current
V
IN
= 15 V
V
IN
= 36 V
Test conditions Min.
2.20
Typ.
0.15
Max.
0.8
10
210
Unit
V
V
V
µA
DS13837 - Rev 1 page 7/29
5.4
5.5
VNI4140K, VNI4140K-32
Protection and diagnostic
Protection and diagnostic
I
LSTAT
T
TSD
T
R
T
HIST
T
CSD
T
CR
T
CHYST
V
DEMAG
Symbol
V
STAT
V
USD
V
USDHYS
I
PEAK
I
LIM
Parameter
Status voltage output low
Undervoltage protection
Undervoltage hysteresis
VNI4140K maximum DC output current
VNI4140K-32 maximum DC output current
VNI4140K, DC short-circuit current
VNI4140K-32, DC shortcircuit current
Status leakage current
Junction shutdown temperature
Junction reset temperature
Junction thermal hysteresis
Case shutdown temperature
Case reset temperature
Case thermal hysteresis
Output voltage at turn-OFF
Table 8. Protection and diagnostic
Test conditions
I
STAT
= 1.6 mA
Dynamic load
V
CC
= 24 V, R
LOAD
= < 10 mΩ
V
CC
= V
STAT
= 36 V
I
OUT
= 0.5 A; L
LOAD
≥ 1 mH
Min.
7
0.4
0.7
1.1
150
Typ.
0.5
1.3
1.6
1.0
1.5
30
170
Max.
0.6
10.5
1.7
2.6
190
135
7
125
15
130 135
110
7 15
V
CC
- 41 V
CC
- 45 V
CC
- 52
Unit
V
V
V
A
A
μA
°C
°C
°C
V
°C
°C
°C
Current and voltage conventions
Figure 4. Current and voltage conventions
DS13837 - Rev 1 page 8/29
VNI4140K, VNI4140K-32
Truth table
6
Note:
Truth table
Condition
Normal operation
Overtemperature
Undervoltage
Output overload
(current limitation before overtemperature)
X = don't care
Table 9. Truth table
Input
N
L
H
L
H
L
H
L
H
Output
N
L
H
L
L
L
L
L
X
Status
N
H
H
H
L
X
X
H
H
DS13837 - Rev 1 page 9/29
7
Typical application circuit
Figure 5. Typical application circuit
VNI4140K, VNI4140K-32
Typical application circuit
DS13837 - Rev 1 page 10/29
8
VNI4140K, VNI4140K-32
Thermal management
Thermal management
The power dissipation in the IC is the main factor that sets the safe operating condition of the device in the application. Therefore, it must be considered very carefully. Furthermore, the available space on the PCB should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Two different protections have been implemented to guarantee safety of the device if it overheats due to an overloaded condition or high environment temperature. The following flowchart explains in detail this protection functionality.
Figure 6. Thermal behavior
Vin(i) = H
OUT(i) On
STAT(i) Off (H)
NO
Tj(i) > Ttsd
1
YES
OUT(i) Off
STAT(i) On (L)
YES
Tc > Tcsd
NO
4
YES
Tc > Tcr
NO
2
3
NO
Tj(i) > Tjr
YES
GIPG030420151405LM
Note: 1 Thermal shutdown
2 Junction hysteresis
3 Restore to idle condition
4 Case hysteresis
DS13837 - Rev 1 page 11/29
9
Switching waveforms
Figure 7. Switching waveforms
VNI4140K, VNI4140K-32
Switching waveforms
DS13837 - Rev 1 page 12/29
10
Pin function description
Figure 8. Input circuit
VNI4140K, VNI4140K-32
Pin function description
Figure 9. Status circuit
DS13837 - Rev 1 page 13/29
VNI4140K, VNI4140K-32
Pin function description
Figure 10. Charge pump switching frequency (typical) vs. temperature
DS13837 - Rev 1 page 14/29
11
11.1
Package and PCB thermal data
Thermal data
Figure 11. PCB for thermal tests
VNI4140K, VNI4140K-32
Package and PCB thermal data
Layout condition of R
TH
and Z
TH
measurements (PCB: double layer, thermal vias, FR4 area = 77 mm x 86 mm,
PCB thickness = 1.6 mm, Cu thickness = 70 mm (front and back side), copper areas: from minimum pad layout to
8 cm 2 ).
Figure 12. R
TH(JA)
vs. PCB copper area in open box free air condition (one channel ON)
DS13837 - Rev 1 page 15/29
VNI4140K, VNI4140K-32
Thermal data
Figure 13. Thermal impedance junction-ambient single pulse (one channel ON)
DS13837 - Rev 1 page 16/29
12
Note:
VNI4140K, VNI4140K-32
Reverse polarity protection
Reverse polarity protection
Reverse polarity protection can be implemented on-board using two different solutions:
1.
Placing a resistor (R
GND
) between IC GND pin and load GND
2.
Placing a diode between IC GND pin and load GND
If option 1 is selected, the minimum resistance value has to be selected according to the following equation:
R
GND
≥ V
CC
/ I
GND where I
GND
is the DC reverse ground pin current and can be found in Maximum ratings of this datasheet.
Power dissipated by R
GND
(when V
CC
< 0: during reverse polarity situations) is:
P
D
= (V
CC
) 2 /R
GND
If option 2 is selected, the diode has to be chosen by taking into account VRRM >|V
CC
| and its power dissipation capability:
P
D
≥ I
S
*V
F
In normal conditions (no reverse polarity), due to the diode, there is a voltage drop between GND of the device and GND of the system.
Figure 14. Reverse polarity protection
+Vcc
Intput
i
Status
i
R
GND
GND
Output
i
Load
Diode
GIPG020420151344LM
This schematic can be used with any type of load.
DS13837 - Rev 1 page 17/29
13
VNI4140K, VNI4140K-32
Demagnetization energy
Demagnetization energy
Figure 15. Maximum demagnetization energy vs. load current, typical values
DS13837 - Rev 1 page 18/29
14
VNI4140K, VNI4140K-32
Package mechanical data
Package mechanical data
Figure 16. PowerSSO-24 package dimensions [mm]
DS13837 - Rev 1
Dim.
e3
G
G1
H h
L
D
E e
N
X
Y
A
A2 a1 b c
Table 10. PowerSSO24, mechanical data
[mm]
Typ.
Min.
2.15
2.15
0
0.33
0.23
10.10
7.4
-
0.8
8.8
10.1
0.55
4.1
6.5
Max.
2.47
2.40
0.075
0.51
0.32
10.50
7.6
0.1
0.06
10.5
0.4
0.85
10deg
4.7
7.1
page 19/29
VNI4140K, VNI4140K-32
Package mechanical data
Figure 17. PowerSSO24 suggested footprint [mm]
STMicroelectronics is not responsible for any PCB related issues. The footprint shown in the above figure is a suggestion which might not be in line with the customer PCB supplier design rules.
DS13837 - Rev 1 page 20/29
15
VNI4140K, VNI4140K-32
PowerSSO24, packing information
PowerSSO24, packing information
Figure 18. PowerSSO-24 tube shipment (no suffix)
Note:
Table 11. PowerSSO24, tube shipment information
Description
Base quantity
Bulk quantity
Tube lenght (± 0.5)
A
B
C (± 0.1)
Value
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
Figure 19. PowerSSO24, reel shipment
DS13837 - Rev 1 page 21/29
Note:
VNI4140K, VNI4140K-32
PowerSSO24, packing information
Description
Base quantity
Bulk quantity
A (max.)
B (min.)
C (± 0.2)
F
G (2 ± 0)
N (min.)
T (max.)
All dimensions are in mm.
Table 12. PowerSSO24, reel information
Figure 20. PowerSSO24, tape drawings
Value
1000
1000
330
1.5
13
20.2
24.4
100
30.4
DS13837 - Rev 1
Description
Tape width
Tape hole spacing
Component spacing
Table 13. PowerSSO24, tape dimension
Symbol
W
P0 (± 0.1)
P
Value
24
4
12 page 22/29
Note:
Note:
VNI4140K, VNI4140K-32
PowerSSO24, packing information
Description
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
Symbol
D (± 0.05)
D1 (min.)
F (± 0.1)
K (max.)
P1 (± 0.1)
All dimensions are in mm.
According to the Electronic Industries Association (EIA) standard 481 rev. A, Feb 1986.
Value
1.55
1.5
11.5
2.85
2
DS13837 - Rev 1 page 23/29
16
Ordering information
Order code
VNI4140K
VNI4140KTR
VNI4140K-32
VNI4140KTR-32
Table 14. Order codes
Package Package marking
VNI4140K
PowerSSO-24
VNI4140K-32
VNI4140K, VNI4140K-32
Ordering information
Packaging
Tube
Tape and reel
Tube
Tape and reel
DS13837 - Rev 1 page 24/29
VNI4140K, VNI4140K-32
Revision history
Date
05-Oct-2021
Version
1
Table 15. Document revision history
Changes
Initial release.
DS13837 - Rev 1 page 25/29
VNI4140K, VNI4140K-32
Contents
Contents
DS13837 - Rev 1 page 26/29
VNI4140K, VNI4140K-32
List of tables
List of tables
DS13837 - Rev 1 page 27/29
VNI4140K, VNI4140K-32
List of figures
List of figures
DS13837 - Rev 1 page 28/29
VNI4140K, VNI4140K-32
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© 2021 STMicroelectronics – All rights reserved
DS13837 - Rev 1 page 29/29
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