STMicroelectronics L9942 Datasheet

L9942

Integrated stepper motor driver for bipolar stepper motors with microstepping and programmable current profile

Features

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Two full bridges for max. 1.3 A load

(R

DSON

= 500 m



)

Programmable current waveform with look-up table: 9 entries with 5 bit resolution

Current regulation by integrated PWM controller and internal current sensing

Programmable stepping mode: full, half, mini and microstepping

Programmable slew rate for EMC and power dissipation optimization

Programmable Fast-, Slow-, Mixed- and Auto-

Decay Mode

Full-scale current programmable with 3 bit resolution

Programmable stall detection

Step clock input for reduced µController requirements

I

Very low current consumption in standby mode

S

< 3 µA, typ. T j



85 °C

All outputs short circuit protected with openload, overload current, temperature warning and thermal shutdown

The PWM signal of the internal PWM controller is available as digital output.

All parameters are guaranteed for 3 V < Vcc <

5.3 V and for 7 V < Vs < 20 V

Applications

Stepper motor driver for bipolar stepper motors in automotive applications like light levelling,

Bending light and Throttle control.

Table 1.

Device summary

Order code Junction temp. range,



C

L9942XP1

L9942XP1TR

-40 to 150

-40 to 150

Description

The L9942 is an integrated stepper motor driver for bipolar stepper motors with microstepping and programmable current profile look-up-table to allow a flexible adaptation of the stepper motor characteristics and intended operating conditions.

It is possible to use different current profiles depending on target criteria: audible noise, vibrations, rotation speed or torque. The decay mode used in PWM-current control circuit can be programmed to slow-, fast-, mixed-and autodecay. In autodecay mode device will use slow decay mode if the current for the next step will increase and the fast decay or mixed decay mode if the current will decrease. The programmable stall detection is useful in case of head lamp leveling and bending light application, by preventing to run the motor too long time in stall for position alignment. If a stall is detected, the alignment process is closed and the noise is minimized.

Package

PowerSSO24

PowerSSO24

PowerSSO24

Packing

Tube

Tape and reel

September 2013 Doc ID 11778 Rev 7 1/40 www.st.com

1

1

2

Contents

Contents

3

4

L9942

Block diagram and pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Dual power supply: V

S

and V

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2

Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3

Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10

2.6

Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7

Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.8

PWM current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.9

Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.10

Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.11

Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.12

Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.13

Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Outputs: Qxn (x = A; B n = 1; 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Functional description of the logic with SPI . . . . . . . . . . . . . . . . . . . . . 21

4.1

Motor stepping clock input (STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2

PWM output (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/40 Doc ID 11778 Rev 7

8

9

L9942

5

6

7

Contents

4.4

Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5

Serial data in (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6

Serial data out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7

Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.8

Data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2

Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3

Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4

Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.5

Register 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.6

Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.7

Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.8

Auxiliary logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.8.1

5.8.2

5.8.3

Fault condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI communication monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PWM monitoring for stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Logic with SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 28

6.1

Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2

DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3

Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4

Output: DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.5

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.6

STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1

Stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.2

Step clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.3

Load current control and detection of overcurrent (shortages at outputs) 33

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Doc ID 11778 Rev 7 3/40

List of tables

List of tables

L9942

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9.

Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10.

Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 11.

Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12.

Outputs: Qxn (x = A; B n =1; 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 13.

PWM control (see

Figure 4 and Figure 7 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 14.

Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15.

Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16.

Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17.

Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 18.

Register 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19.

Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 20.

Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 21.

Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 22.

DI timing (see Figure 11

and Figure 13 )

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 23.

Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 24.

Output: DO timing (see

Figure 12 and Figure 13 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 25.

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 26.

STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 27.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4/40 Doc ID 11778 Rev 7

L9942

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4.

Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5.

Thermal data of the package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6.

VS monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7.

Logic to set load current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8.

Switching on minimum time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9.

SPI and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10.

Transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11.

Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 12.

SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 13.

DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 14.

Timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15.

Stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 16.

Reference generation for PWM control (switch on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17.

Reference generation for PWM control (decay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18.

PowerSSO24 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 11778 Rev 7 5/40

Block diagram and pin information

1 Block diagram and pin information

Figure 1.

Block diagram

STEP

EN

PWM

DO

DI

CLK

CSN

VCC

Oscillator

CP

Charge

Pump

Diagnostic

Gate-Driver

&

PWM-Controller

Diagnostic

Biasing

GND

U/I-

Converter

RREF

Gate-Driver

&

PWM-Controller

VBAT

ReversePolarityProtection

VS

QA1

Note: value of capacitor has to be choosen carefully to limit the VS voltage below absolute maximum ratings in case of an unexpected freewheeling condition (e.g.

TSD, POR)

QA2

QB1

Stepper

Motor

GNDP

GND

L9942

Figure 2.

Pin connection (top view)

PGND 1

QA1 2

VS 3

CLK 4

DI 5

CSN 6

DO 7

PWM 8

STEP 9

VS 10

QB1 11

PGND 12

Power SSO24

Exposed

Pad

All pins with the same name must be externally connected!

All pins PGND are internally connected to the heat slug.

24 PGND

23 QA2

22 VS

21 EN

20 RREF

19 VCC

18 TEST

17 GND

16 CP

15 VS

14 QB2

13 PGND

6/40 Doc ID 11778 Rev 7

L9942 Block diagram and pin information

Table 2.

Pin description

Pin Symbol Function

1, 12, 13,

24

3, 10, 15,

22

PGND

VS

Power ground: All pins PGND are internally connected to the heat slug.

Important : All pins of PGND must be externally connected!

Power supply voltage (external reverse protection required): For EMI reason a ceramic capacitor as close as possible to PGND is recommended.

Important : All pins of VS must be externally connected!

2, 23

QA1,QA

2

Fullbridge-outputs An: The output is built by a high-side and a low-side switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal reverse diode (bulkdrain-diode: highside driver from output to VS, low-side driver from PGND to output). This output is overcurrent protected.

11, 14

QB1,QB

2

Fullbridge-outputs Bn: The output is built by a highside and a low-side switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal reverse diode (bulkdrain-diode: highside driver from output to VS, low-side driver from PGND to output). This output is overcurrent protected.

SPI clock input: The input requires CMOS logic levels. The CLK input has

4 CLK a pull-down current. It controls the internal shift register of the SPI.

Serial data input: The input requires CMOS logic levels. The DI input has a pull-down current. It receives serial data from the microcontroller. The data

5 DI is a 16bit control word and the most significant bit (MSB, bit 0) is transferred first.

Chip Select Not input The input requires CMOS logic levels. The CSN micro controller is enabled by pulling the input CSN to low level.

SPI data output: The diagnosis data is available via the SPI and it is a if the chip is not selected by the input CSN (CSN = high)

PWM output This CMOS compatible output reflects the current duty cycle of the internal PWM controller of bridge A. It is an high resistance output

8 PWM until VCC has reached minimum voltage ore can switched off via the SPI command.

Step clock input: The input requires CMOS logic levels. The STEP input has a pull-down current. It is clock of up and down counter of control

9 STEP register 0. Rising edge starts new PWM cycle to drive motor in next position.

Charge Pump Output: A ceramic capacitor (e.g.100 nF) to VS can be

16 CP connected to this pin to buffer the charge-pump voltage.

Ground: Reference potential besides power ground e.g. for reference

17 GND resistor RREF. From this pin exist a resistive path via substrate to PGND.

Test input The TEST input has a pull-down current. Pin used for production

18 TEST test only. In the application it must be connected to GND.

Logic supply voltage: For this input a ceramic capacitor as close as

19 VCC possible to GND is recommended.

Doc ID 11778 Rev 7 7/40

Block diagram and pin information L9942

Table 2.

Pin description (continued)

Pin Symbol Function

Reference Resistor The reference resistor is used to generate a temperature stable reference current used for current control and internal should be chosen that a current of about 200uA will flow through the resistor.

Enable input: The input requires CMOS logic levels. The EN input has a pull-down resistor. In standby-mode outputs will be switched off and all

21 EN registers will be cleared. If EN is set to a logic high level then the device will enter the active mode.

8/40 Doc ID 11778 Rev 7

L9942 Device description

2.1 Dual power supply: V

S

and V

CC

The power supply voltage V

S

supplies the half bridges. An internal charge-pump is used to drive the highside switches. The logic supply voltage V

CC

(stabilized) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (V

CC

increases from undervoltage to V

POR OFF

= 2.60 V, typical) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage V

CC

decreases under the minimum threshold (V

POR ON

= 2.3 V, typical), the outputs are switched to tristate (high impedance) and the internal registers are cleared.

The EN input has a pull-down resistor. The device is in standby mode if EN input isn't set to a logic high level. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 3 µA (1 µA) for

CSN = high (DO in tristate). If EN is set to a logic high level then the device will enter the active mode. In the active mode the charge pump and the supervisor functions are activated.

2.4

All diagnostic functions (overload/-current, open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered (t

GL

= 32 µs, typical) and the condition has to be valid for a minimum time before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device.

Open load and temperature warning function are intended for information purpose and will not change the state of the bridge drivers. On contrary, the overload/-current and thermal shutdown condition will disable the corresponding driver (overload/-current) or all drivers

(thermal shutdown), respectively. The microcontroller has to clear the status bit to reactivate the bridge driver.

Overvoltage and undervoltage detection

If the power supply voltage Vs rises above the overvoltage threshold V

SOV OFF

(typical

21 V), an overvoltage condition is detected. Programmable by SPI (OVW) the outputs are switched to high impedance state (default after reset) or the overvoltage bit is set without switching the outputs to high impedance. When the voltage Vs drops below the undervoltage threshold V

SUV OFF

, the outputs are switched to high impedance state to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). Error condition is latched and the microcontroller needs to clear the status bits to reactivate the drivers.

Doc ID 11778 Rev 7 9/40

Device description

2.5

L9942

Temperature warning and thermal shutdown

If junction temperature rises above T j TW

a temperature warning flag is set which is detectable via the SPI. If junction temperature increases above the second threshold T j SD

, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below Tj SD -Tj SD HYS and the thermal shutdown bit has to be cleared by the microcontroller.

Each half bridge is built by an internally connected highside and a low-side power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven without external free-wheeling diodes. In order to reduce the power dissipation during free-wheeling condition the PWM controller will switch-on the output transistor parallel to the freewheeling diode (synchronous rectification).

2.8

The four half-brides of the device are cross-current protected by an internal delay time depending on the programmed slew rate. If one driver (LS or HS) is turned-off then activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time.

PWM current regulation

An internal current monitor output of each high-side and low-side transistor sources a current image which has a fixed ratio of the instantaneous load current. This current images are compared with the current limit in PWM control. Range of limit can reach from programmed full scale value (register1 DAC Scale) down belonging LSB value of 5 bit DAC

(register1 DAC Phase x). The data of the two 5 bit DACs comes form set up in 9 current profiles (register2 to 6). If signal changes to logic high at pin STEP then 2 current profiles are moved in register1 for DAC Phase A and B. Number of profile depends on phase counter reading and direction bit in register0 (

Figure 7 ). The bridges are switched on until

the load current sensed at HS switch exceeds the limit. Load current comparator signal is used to detect open load or overcurrent condition also.

10/40

During off-time the device will use one of several decay modes programmable by SPI

(

Figure 4 top). In slow decay mode HS switches are activated after cross current protection

time for synchronous rectification to reduce the power dissipation (

Figure 4 detail A). In fast

decay opposite half bridge will switched on after cross current protection time, that is same like change in the direction. For mixed decay the duration of fast decay period before slow decay can be set to a fixed time (

Figure 4

detail B continuous line) or is triggered by underrun of the load current limit (

Figure 4 detail B dashed line), that can be detected at LS

switch. The special mode where the actual phase counter value is taken into account to select the decay mode is called auto decay (e.g. in

Figure 3 Micro Stepping DIR=1). If the

absolute value of the current limit is higher as during step before then PWM control uses

Doc ID 11778 Rev 7

L9942 Device description slow decay mode always. Otherwise one of the fast decay modes is automatic selected for a quick decrease of the load current and so it obtains new lower target value.

The overcurrent detection circuit monitors the load current in each activated output stage. In

HS stage it is in function after detection of current limit during PWM cycle and in LS stage it works permanently. If the load current exceeds the overcurrent detection threshold for at least t

ISC

= 4 µs, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. Error condition is latched and the microcontroller needs to clear the status bits to reactivate the drivers.

2.11 Open load detection

The open load detection monitors the activity time of the PWM controller and is available for each phase. If the limit of load current is below around 100mA then open load condition is detectable. Open load bit for a bridge is set in the register6 if this low current limit can't reached after at least 15 consecutive PWM cycles.

Table 3.

DC2

1

1

1

1

0

0

0

0

Truth table

DC1 DC0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

I4

0

0

0

0

0

0

0

0

I3

0

0

0

0 x x

0

0

I2

0

0

0

0 x x x x

I1 x x

0

0 x x x x

I0 x x

1

1 x x x x max. IOL

46mA

68mA

52mA

81mA

53mA

78mA

37mA

44mA

Truth table shows possible profiles for active open load detection. Maximum threshold IOL is shown in left column if x bits are 1 (see also

Figure 7 ). Lowest possible limit is e.g. 3.1 mA

for DC2=DC1=DC0=0 and it is set only I0=1.

One full revolution can consist of four full steps, eight half steps, sixteen mini steps or 32 microsteps.

Mode is set up in register 0 and it defines increment size of phase counter. Phase counter value defines address of corresponding current profile. Stepping modes with typical profile values can see in

Figure 3 (e.g. also so called 'Two Phase On' shown in dashed line).

Doc ID 11778 Rev 7 11/40

Device description

Figure 3.

Stepping modes

0

0

Full-Stepping Mode: DIR=0

8 16 24

8

Current Driver A

0 8

Phase Counter

Address of Current

Profile Entry

0

24

Full-Stepping Mode: DIR=1

16 8

8

Current Driver A

0 8

0

8 0

Current Driver B

8

STEP Signal

0

Address of Current

Profile Entry

8

Current Driver B

0 8

STEP Signal

0

0

0

Half-Stepping Mode: DIR=0

4 8 12 16 20 24

Current Driver A

4 8 4 0 4 8

28

4

Phase Counter 0

Address of Current

Profile Entry

0

Half-Stepping Mode: DIR=1

28 24 20 16 12 8

Driver Current A

4 8 4 0 4 8

4

4

L9942

8 4 0

Current Driver B

4 8 4

STEP Signal

0 4

Address of Current

Profile Entry

8 4 0

Driver Current B

4 8 4

STEP Signal

0 4

0 2 4

Mini-Stepping Mode: DIR=0

6 8 10 12 14 16 18 20 22 24

Current Driver A

26 28 30

Phase Counter

0 30 28

Mini-Stepping Mode: DIR=1

26 24 22 20 18 16 14 12 10 8 6

Current Driver A

4 2

0 2 4 6 8 6 4 2 0 2 4 6 8 6 4 2

Adress of Current

Profile Entry

0 2 4 6 8 6 4 2 0 2 4 6 8 6 4 2

8 6 4 2 0 2

Current Driver B

4 6 8 6 4 2 0 2 4 6

Adress of Current

Profile Entry

8 6 4 2 0 2

Current Driver B

4 6 8 6 4 2 0 2 4 6

STEP Signal STEP Signal

Micro Stepping Mode: DIR=0 (e.g auto decay)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Phase Counter

Current Driver A

Slow Decay

Mode

Mixed Decay

Mode

0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

Slow Decay

Mode

Mixed Decay

Mode

Adress of Current

Profile Entry

0

Micro Stepping Mode: DIR=1 (e.g. auto decay)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Slow Decay

Mode

Current Driver A

Mixed Decay

Mode

0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

Slow Decay

Mode

Mixed Decay

Mode

Mixed Decay

Mode

Slow Decay

Mode

Current Driver B

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

Slow Decay

Mode

Mixed Decay

Mode

Adress of Current

Profile Entry

Mixed Decay

Mode

8 7 6 5 4 3 2 1

Current Driver B

Slow Decay

Mode

0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

Slow Decay

Mode

Mixed Decay

Mode

12/40 Doc ID 11778 Rev 7

L9942 Device description

Figure 4.

Decay modes

Load

Current

ON SLOW

DECAY on

VS on

A on

VS on

FAST

DECAY on

VS on on

MIXED

DECAY

VS on

VS on

B

Time

Internal PWM_CLK

Load

Current

Detail A: SWITCH ON AND SLOW DECAY

ON T

FT

SLOW DECAY

Step

Limit

HS

T

FT

T

CC

T

B

register0

DM2 DM1 DM0 MODE

0 0 0 slow

Fast decay is caused by current through internal diodes during cross current protection time.

OFF

OFF

Time

Filter time for the purpose of switch off delay in on mode is set by FT register6

Cross current protection time is set by SR1 SR0 register0

Blank time of load current comparator T

B

=T

CC

VS

OFF

OFF

Load

Current

T

CC

Step

Limit

LS

Detail B:

MIXED DECAY

register0

DM2 DM1 DM0 MODE CURVE

X 0 1

X 1 0

X 1 1

T

MD1

T

MD2

T mc

T

FT

T

CC

FAST

DECAY

SLOW DECAY after current undershoot

T mc

T

> mc

= T

FT

+ 2T

CC

Time

Load

Current

T = T

MD1 or T

MD2

T

FT

T

T

CC

FAST

DECAY

T

SLOW DECAY with delay

T

CC

Filter time for purpose of delay when decay mode has to change after limit under-run

When limit is reached so fast decay duration time is set by DM1 DM2 register0

Time

Doc ID 11778 Rev 7 13/40

Electrical specifications L9942

3.1 Absolute maximum ratings

Table 4.

Absolute maximum ratings

Symbol Parameter

V

S

DC supply voltage single pulse t max

< 400 ms

V

CC

V

RREF

Stabilized supply voltage, logic supply

V

DI

,V

DO

,

V

CLK

V

CSN

,

V

STEP

V

EN

Digital input / output voltage

Current reference resistor

V

CP

Charge pump output

V

Qxn

I

Qxn

(x=A;B n=1;2) output voltage

(x=A;B n=1;2) output current

-0.3 to 28 V

40 V

-0.3 to 5.5 V

-0.3 to V

CC

+ 0.3 V

-0.3 to V

CC

+ 0.3

-0.3 to V

S

+ 11

V

V

-0.3 to V

S

+ 0.3 V



2.5 A

Warning: Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit!

Table 5.

ESD protection

All pins output pins: Qxn (x=A;B n=1;2)

1.

HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A

2.

HBM with all unzapped pins grounded



2 (1)



4

(2) kV kV

14/40 Doc ID 11778 Rev 7

L9942 Electrical specifications

Table 6.

Operating junction temperature

Symbol Parameter

T j

Table 7.

Operating junction temperature

Temperature warning and thermal shutdown

-40 to 150

T jTW ON

T jTW OFF

T jSD ON

T jSD OFF

T jSD HYS

Temperature warning threshold junction temperature

Temperature warning threshold junction temperature

Thermal shutdown threshold junction temperature

Thermal shutdown threshold junction temperature

Thermal shutdown hysteresis -

-

-

-

T j

increasing

Figure 5.

Thermal data of the package

-

130

-

150

-

-

-

-

-

5

°C

150 °C

°C

170

-

-

°C

°C

K

Note:

1s 1 signal layer

2s2p 2 signal layers 2 internal planes

Doc ID 11778 Rev 7 15/40

Electrical specifications L9942

V

S

= 7 to 20 V, V

CC

= 3.0 to 5.3 V, T j

= -40 to 150 °C, I

REF

= -200 µA, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

3.4.1 Supply

Table 8.

Symbol

Supply

Parameter Test condition

I

S

I

CC

V

S

DC supply current in active mode

V

S

= 13.5 V, EN=V floating

CC

outputs

V

S

quiescent supply current

V

S

= 13.5 V, TEST,

EN = 0V outputs floating

T j

= -40 °C to 25 °C

T j

= 125 °C

V

CC

= 5.0 V EN=V

CC

,

DI=CLK=STEP=0V

V

CC

DC supply current in active mode

V

CC

= 5.0 V TEST;

EN = 0 V; CSN =

V

CC

no clocks outputs floating

T j

= -40 °C to 25 °C

I

CC

V

CC

quiescent supply current

CSN=V

CC

no clocks outputs floating

V

S

= 13.5 V, V

CC

=

5.0 V

T j

= 125 °C

T j

= -40 °C to 25 °C

I

S

+ I

CC

Sum quiescent supply current

TEST; EN=0 V

CSN=V

CC no clocks outputs floating

T j

= 125 °C t setPOR

(1)

V

CC

on set up time

EN = 5 V, CSN=CLK=0V DO changes from high ohmic to logic level LOW

1.

This parameter is guaranteed by design.

Min.

-

-

-

-

-

-

-

-

Typ.

7

1

2

4

8

2 -

3

6

1

Max.

Unit

20 mA

10

20

3

3

6

13

26

-

µA mA

µA

µA

µA

µs

16/40 Doc ID 11778 Rev 7

L9942 Electrical specifications

3.4.2 Over- and undervoltage detection

Table 9.

Over- and undervoltage detection

Symbol Parameter Test

V

SUV ON

V

S

UV-threshold voltage

V

SUV OFF

V

SUV hyst

V

S

UV-threshold voltage

V

S

UV-hysteresis

V

SOV OFF

V

S

OV-threshold voltage

V

SOV ON

V

S

OV-threshold voltage

V

SOV hys t V

S

OV-hysteresis

V

POR OFF

V

POR ON

V

POR hyst

Power-on-reset hysteresis

V

S

increasing

V

S

decreasing

V

SUV ON

-V

SUV OFF

V

S

increasing

V

S

decreasing

V

SOV OFF

-V

SOV ON

V

CC

increasing

V

CC

decreasing

V

POR OFF

-V

POR ON

-

4.8

-

-

18.5

-

-

2.00

-

6.90

-

0.3 -

-

21

20

25

-

0.5 -

2.6 2.9

2.3

0.11 -

-

Figure 6.

VS monitoring

Register 7

UV

Register 7

OV

1 1

V

V

V

V

V

V

V

V

V

0

VS

0

VS

VSUV OFF VSUV ON VSOV ON VSOV OFF

3.4.3 Reference current output

Table 10.

Reference current output

Symbol Parameter

V

REF

I

REFshorted

Reference voltage range I

REF

= -200



A

Reference current threshold shorted pin REF register6 bit7 RERR = 1

I

REFopen

Reference current threshold open pin REF register6 bit7 RERR = 1

1.05 1.25 1.45 V

-250



A

-150 -



A

The device works properly without the external resistor at pin REF. In this case it doesn't have to fulfill all specified parameters.

Doc ID 11778 Rev 7 17/40

Electrical specifications L9942

3.4.4 Charge pump output

Table 11.

Charge pump output

Symbol Parameter

V

CP

Test condition

Charge pump output voltage

V

S

=7 V

V

S

=13.5 V

V

S

=20 V

I

CP

= -100



A, all switches off at

Qxn

Min.

11

20

30

Typ.

-

-

-

The ripple of voltage at CP can suppressed using a capacity of e.g.100 nF.

Max.

20

35

40

Unit

V

V

V

3.4.5 Outputs: Qxn (x = A; B n = 1; 2)

The comparator, which is monitoring current image of HS, is working during ON cycle of

PWM control. If load current is higher as set value then the signal ILIMIT is generated and after filter time the bridge is switched off. Test mode gets access to signal ILIMIT and threshold of current can be measured.

Table 12.

Outputs: Qxn (x = A; B n =1; 2)

Symbol Parameter

R

DSON HS

On-resistance Qxn to V

S

R

|I

DSON LS

QxnOC

|

On-resistance Qxn to

PGND

Output overcurrent limitation to VS or PGND

V

S

= 13.5 V, T j

= 25 °C,

I

Qxn

= -1.0 A

V

S

= 13.5 V, T j

= 125 °C,

I

Qxn

= -1.0 A

V

S

= 7.0 V, T j

= 25 °C,

I

Qxn

= -1.0 A

V

S

= 13.5 V, T j

= 25 °C,

I

Qxn

= + 1.0 A

V

S

= 13.5 V, T j

= 125 °C,

I

Qxn

= + 1.0 A

V

S

= 7.0 V, T j

= 25 °C,

I

Qxn

= + 1.0 A test mode exclusive of filter

time 4µs ( Chapter 2.10

)

Bits: DC2 DC1 DC0=000

Bits: DC2 DC1 DC0=001

I

QxnFS_HS

Value of output current to supply V

S

(so called full scale value)1 sourcing from HS switch

Bits: DC2 DC1 DC0=010

Bits: DC2 DC1 DC0=011

Bits: DC2 DC1 DC0=100

Bits: DC2 DC1 DC0=101

Bits: DC2 DC1 DC0=110

Bits: DC2 DC1 DC0=111

I

QxnLIM_HS

Accuracy of micro steps current limit

-

1.

MIN= 0.92 · I

QxnLIM

– 0.02 · |I

QxnFS_HS

|; MAX= 1.08 · I

QxnLIM

+ 0.02 · |I

QxnFS_HS

|

-

-

-

-

-

-

1.6

60

100

180

300

485

720

1000

1200

MIN

(1)

Typ.

500

750

550

500

750

550

2

95

140

230

360

550

810

1150

1350

-

Max.

700

1000

750

700

1000

750

-

130

180

280

420

615

900

1300

1500

MAX

(1)

Unit m

 m

 m

 m

 m

 m



A mA mA

18/40 Doc ID 11778 Rev 7

L9942 Electrical specifications

Note: Current profile has to pre set with I4 I3 I2 I1 I0 = 11111 and load to register 1.

Output current limit I

QxnLIM

is product of full scale current |I

QxnFS_ |

(bits DC2 DC1 DC0) and value of DAC Phase A/B (bits I4 I3 I2 I1 I0) in register1.

Values of DAC Phase A and B can read out and depends on set up done before:

1.

direction DIR, stepping mode ST1 ST0 and phase counter P4 P3 P2 P1 P0 in register 0 and

2. value of corresponding current profile (for address of current profile entry see also

Figure 3 ).

Figure 7.

Logic to set load current limit

STEP

UP/Down

Count by

1,2,4,8 P4

PhaseCounter

P3 P2 P1

Register 0

Decay Mode

P0 DM2 DM1 DM0

Slew Rate

SR1 SR0

StepMode

ST1 ST0 DIR

0 0 0

0 1 2 3 0 1 2 3 0 1 2 3

A2 A1 A0

MUX MUX MUX

Current-Profile Table stored in register2, ...6

I4 I3 I2

I4 I3 I2

I4 I3 I2

I4 I3 I2

I4 I3 I2

I4 I3 I2

I4 I3 I2

I4 I3 I2

I4 I3 I2

I1 I0

I1 I0

I1 I0

I1 I0

I1 I0

I1 I0

I1 I0

I1 I0

I1 I0

Profile 8

5

5

Profile 7

5

Profile 6

5

Profile 5

5

Profile 4

5

Profile 3

5

Profile 2

5

Profile 1

5

Profile 0

9

A3 A2 A1 A0 Address Calculation

Phase A

A3=0

Adr A[3..0]

A3=1

Adr neg(A[3..0])

Phase B

A3=0

Adr neg(A[3..0])

A3=1

Adr A[3..0]

DI

REF

I

REF

DAC

Full Scale

I

MAX

5

Register 1

DAC Scale

DC2 DC1 DC0 I4

DAC Phase B

I3 I2 I1 I0 I4

DAC Phase A

I3 I2 I1 I0

5 bit DAC

Phase B

LIMIT B

5 bit DAC

Phase A

I

LIMIT A

I

QA1LIM

1000

I

QB1LIM

1000

I

QA2LIM

1000

I

QB2LIM

1000

QA1

QA2

I

Qx1LIM

QB1

QB2

I

Qx2LIM

Doc ID 11778 Rev 7 19/40

Electrical specifications L9942

Table 13.

PWM control (see

Figure 4

and Figure 7

)

Symbol Parameter Test condition Min.

f

PWM

(1)

Frequency of PWM cycles

Bit: FRE= 1

Bit: FRE= 0

Bits: DM1 DM0= 0 1

T

MD

(1)

Mixed decay switch off delay time

T

T

T

FT

(1) cc

B

(1)

(1)

Glitch filter delay time

Bits: DM1 DM0= 1 0

Bit: FILTER= 0

Bit: FILTER= 1

Bits: SR1 SR0= 0 0

Cross current protection time Blank time of comparator

Bits: SR1 SR0= 0 1

Bits: SR1 SR0= 1 0

VSR

Bits: SR1 SR0= 1 1

Bits: SR1 SR0= 0 0

Slew rate (dV/dt 30 % - 70 %) @HS switches on resistive load of 10



,

VS = 13.5 V

Bits: SR1 SR0= 0 1

Bits: SR1 SR0= 1 0

Bits: SR1 SR0= 1 1

1.

This parameter is guaranteed by design.

Time base is an internal trimmed oscillator of typical 2MHz and it has an accuracy of ±6 %.

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Figure 8.

Switching on minimum time

Load current at Qxn

T

FT

T

CC

Step limit

T

FT

Filter time of current comparator

T

CC

Cross current protection time

T

B

Blank time of current comparator e.g. T

B

= T

CC

= 1 us T

FT

= 1.5 us

Typ.

Max.

Unit

13

6

6

4

13

1

2

20.8

31.3

4

8

1.5

2.5

0.5

-

-

-

-

-

-

-

-

-

-

-

-

-

-

µs

µs

µs

V/µs

V/µs

V/µs

V/µs

µs

µs

µs

µs kHz kHz

µs

T

CC

T

B

Internal PWM clock

20 or 30 kHz

T

INT _2MHz

Pin PWM

(for bridge A) on

T

PWM decay

Time

20/40 Doc ID 11778 Rev 7

L9942

4

4.1

4.2

4.3

4.4

4.5

Functional description of the logic with SPI

Functional description of the logic with SPI

Motor stepping clock input (STEP)

Rising edge of signal STEP is latched. It is synchronized by internal clock. At next start of a new PWM cycle the new values of output current limit are used to drive motor in next position. Before start new motor step this signal has to be low for at least two internal clock periods to reset latch.

PWM output (PWM)

This output reflects the current duty cycle of the internal PWM controller of bridge A. High level indicates on state to increase current through load and low level is in off state so load current decreases depending on chosen decay mode.

Serial peripheral interface (SPI)

This device uses a standard 16 bit SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect an internal error flag of the device which is a logical-or of all status bits in the Status Register

(reg 7) and in the current profile register 4 (reg 6). The microcontroller can poll the status of the device without the need of a full SPI-communication cycle.

Chip select not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame.

Serial data in (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and latched into an internal 16 bit shift register.

The first 3 bit are interpreted as address of the data register. At the rising edge of the CSN signal the contents of the shift register will be transferred to the selected data register. The writing to the register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Doc ID 11778 Rev 7 21/40

Functional description of the logic with SPI

Note:

L9942

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.

4.6

4.7

Serial data out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.

Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.

The device has eight data registers. The first three bits (bit 0 ... bit 2) at the DI-input are used to select one of the input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected

Input Data Register only if a frame of exact 16 data bits are detected. The selected register will be transferred to DO during the current communication frame.

Figure 9.

SPI and registers

DI

CLK

CSN

INT_2MHz

POR

CLK_ADR

SPI-

Controll

SEL_ERROR

SPI2REG

D

D0 D1

D

A0 A1

D2

A2

D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 A0 A1 A2

DO

Register 0

Register 1

P4

Phase Counter

P3 P2 P1

DC2

DAC_Scale

DC1 DC0

P0 DM2

Decay Mode

DM1 DM0

Slew Rate

SR1 SR0

Step Mode

ST1 ST0

BI4

Read Only

BI3

DAC Phase B

BI2 BI1 BI0 AI4

DAC Phase A

AI3 AI2 AI1

DIR

AI0

Register 2

Register 3

I4

I4

I3

Current Profile 1

I2 I1

I3

Current Profile 3

I2 I1

I0

I0

OV

OVW

Test only

T 1 T 0 I4

PWM Counter

D1 D0

PWM

NPWM I4

Current Profile 0

I3 I2 I1

Current Profile 2

I3 I2 I1

I0

I0

Register 4

I4 I3

Current Profile 5

I2 I1 I0

PWM Counter

D4 D3 D2 I4

Current Profile 4

I3 I2 I1 I0

Register 5

I4

Register 6

CLR6

I3

Current Profile 7

I2 I1

SST

I0

PWM Counter

D7 D6 D5

FT

PWM

Freq

ST

RREF

Error

Read-Only

Openload

Phase

B

Phase

A

I4

I4

Current Profile 6

I3 I2 I1

Current Profile 8

I3 I2 I1

I0

I0

Register 7

Read-Only

CLR7

Temperature

TSD TW

VS Monitor

OV(W) UV HSB2 HSB1 LSB2

Overcurrent

LSB1 HSA2 HSA1 LSA2 LSA1

22/40 Doc ID 11778 Rev 7

L9942

5 SPI - control and status registers

SPI - control and status registers

Table 14.

Register 0

Phase counter

Bit

Decay mode Slew rate Step mode DIR

Access r w r w r w r w r w r w r w r w r w r w r w r w r w

Name P4 P3 P2 P1 P0 DM2 DM1 DM0 SR1 SR0 ST1 ST0 DIR

The meaning of the different bits is as follows:

DIR

:

This bit controls direction of motor movement. DIR=1 clockwise DIR=0 counter clockwise.

ST1 ST0

00

01

10

11

SR1 SR0

This bits controls step mode of motor movement (

Figure 3

).

Micro-stepping

Mini-stepping

Half-stepping

Full-stepping

This bit controls slew rate of bridge switches. See also parameter Table 13

DM2 DM1 DM0

This bits controls decay mode of output current ( Figure 3 ).

000

001

010

011

100

101

110

111

Slow decay

Mixed decay, fast decay until T

MD

> 4 µs

Mixed decay, fast decay until T

MD

> 8 µs

Mixed decay, fast decay until current undershoot T mc

=T

FT

+T

CC

Auto decay, fast decay without delay time

Auto decay, fast decay until T

MD

> 4 µs

Auto decay, fast decay until T

MD

> 8 µs

Auto decay, fast decay until current undershoot T mc

Auto decay uses mixed decay automatically to reduce current for next step if required

(see

Figure 3

down right).

P4 P3 P2 P1 P0 This bits control position of motor, e.g. 00000 step angle is 0° , 01111 step angle is 180 °.

Doc ID 11778 Rev 7 23/40

SPI - control and status registers L9942

Table 15.

Register 1

DAC scale

Bit

Access r w r w r w r

DAC phase B DAC phase A r r r r r r r r r

Name DC2 DC1 DC0 BI4 BI3 BI2 BI1 BI0 AI4 AI3 AI2 AI1 AI0

The meaning of the different bits is as follows:

AI4 AI3 AI2 AI1 AI0

BI4 BI3 BI2 BI1 BI0

DC2 DC1 DC0

These bits control DAC of bridge A.

These bits control DAC of bridge B.

These bits set full scale range of limit, e.g. 000 for 100 mA or

111 for e.g. 1500 mA

Value depends on address and the value of corresponding current profile.

See also parameter Table 12 .

Table 16.

Register 2

Current profile 1

Bit

OV Test only Current profile 0

Access r w r w r w r w r w r w r w r w r w r w r w r w r w

The meaning of the different bits is as follows:

:

I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed. See

parameter

T1 T0 Should be programmed to 0.

-

OVW = 0

OVW = 1

In case of an overvoltage event (V-SOV OFF) the outputs are switched to high impedance state and the Vs Monitor bit OV is set.

In case of an overvoltage event (V-SOV OFF) the Vs Monitor bit

OV is set. The status of the outputs are unchanged.

-

-

24/40 Doc ID 11778 Rev 7

L9942 SPI - control and status registers

Table 17.

Register 3

Current profile 3

Bit

PWM counter PWM Current profile 2

12 11 10 9 8 7 6 5 4 3 2 1 0

Access r w r w r w r w r w r w r w r w r w r w r w r w r w

Name I4 I3 I2 I1 I0 D1 D0 NPW I4 I3 I2 I1 I0

The meaning of the different bits is as follows:

I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed.

D1 D0

NPWM

These bits are for threshold value in counter of active time during signal PWM.

This bit switches internal PWM signal of bridge A to pin PWM if it is set to 0, otherwise pin is in high resistance status.

-

See also parameter Table 12

-

5.5 Register 4 and 5

Table 18.

Register 4 and 5

Current profile 5 (7)

Bit

12 11 10 9

Access r w

Reset 0

Name I4 r w

0

I3 r w

0

I2 r w

0

I1

8 r w

0

I0

PWM counter

7 6 5 r w

0 r w

0 r w

0

D4(7) D3(6) D2(5)

4 r w

0

I4

Current profile 4 (6)

3 r w

0

I3

2 r w

0

I2

1 r w

0

I1

The meaning of the different bits is as follows:

I4 I3 I2 I1 I0

These bits are loaded needed. in register1 DAC Phase A or B if needed.

See also parameter

Table 12

D4 D3 D2 (register4 ) These bits are for threshold value in counter of active time during signal PWM. LSB and next value are set in

D7 D6 D5 (register5) register3 by D0 and D1.

-

0 r w

0

I0

Doc ID 11778 Rev 7 25/40

SPI - control and status registers L9942

Table 19.

Register 6

CLR

ST

(PWM)

Filter Freq.

ST

REF

ERR

Open load Current profile 8

Bit 12 11 10 9 8 7 6 5 4 3 2 1 0

Access r w r w r w r w r r r r r w r w r w r w r w

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Name CLR6 SST FT

PWM

Freq.

ST

RREF

Error

Phase

B

Phase

A

I4 I3 I2 I1 I0

The meaning of the different bits is as follows:

I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed

See also parameter Table 12

Phase B Phase A These bits indicate open load at bridges

RREF Error

ST

This bit indicates if reference current is OK (150 µA <I

REF

< 250 µA), then is RERR=0.

This bit indicates stall detection.

PWM Freq.

FT

SST

CLR6

This bit sets frequency of PWM cycle. FRE=1 frequency 20 kHz, FRE=0 frequency 30 kHz

This bit sets filter time in glitch filter. FT=0 T

F

=1.5 µs, FT=1 T

F

= 2.5 µs

This bit specifies output PWM to reflect same logical level like bit ST.

This bit resets all read only bits to 0 in register 6.

Table 20.

Register 7

Overcurrent

Reset 0 0 0 0 0 0 0 0 0 0 0 0

Name CLR7 TSD TW OV(W) UV HSB2 HSB1 LSB2 LSB1 HSA2 HSA1 LSA2 LSA1

The meaning of the different bits is as follows: bit7 ... bit0 These bits indicate overcurrent in each low side or highside power transistor.

1

OV(W) UV

01

10

TSD TW

01

10

CLR7 overcurrent failure I > 2 A

These bits indicates failure at VS (See also parameter

Table 9 )

Voltage at pin VS is too low.

Voltage at pin VS is too high.

These bits indicates temperature failure (See also parameter Table 7

)

Only for information set at temperature warning threshold.

In case of thermal shutdown all bridges are switched off. It has to reset by bit CLR7.

This bit resets all bits to 0 in register 7.

26/40 Doc ID 11778 Rev 7

L9942

5.8 Auxiliary logic blocks

SPI - control and status registers

Logical level at pin D0 represents fault condition. It is valid from first high to low edge of signal CLK up to transfer of data bit D12. Fault bit is an logical OR of:

Control and status register 6 bit 5 and 6 for open load, bit 7 reference current failure

(RERR) and

Control and status register 7 bit 0 to bit 7 for overcurrent, bit 8 and 9 failure at VS

(UV,OV) and bit 10 and bit 11 during high temperature (TW,TSD)

Note:

5.8.3

At the rising edge of the CSN signal the contents of the shift register will be transferred to the selected data register. A counter monitors proper SPI communication. It counts rising edges at pin CLK. The writing to the register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. SPI communication can be checked by loading a command twice and then answer at pin DO must be same.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.

PWM monitoring for stall detection

Control registers 4, 5, and 3 contain bits D0-D7, use for setting a stall detection threshold.

The value in this set of bits determine the minimum time for current rise over one quadrant of motor driving. D7-D0 is compared with the sum of the rise times over one quadrant. When the sum is less than the value stored in D7-D0 the ST bit (register 6 bit 8) is set to a logic “1”.

The PWM pin reflects the PWM control signal of the load current in bridge A. This is so after power on when the SST bit (register 6, bit11) is reset to a logic “0”. If this bit is set to a logical “1” then status of the ST bit 8 is mirrored to pin PWM. This provides stall detection without the need of reading register 6 through the SPI bus.

Doc ID 11778 Rev 7 27/40

Logic with SPI - electrical characteristics

6 Logic with SPI - electrical characteristics

L9942

VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, T j

= -40 to 150 °C, I

REF

= -200



A, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

6.1 Inputs: CSN, CLK, STEP, EN and DI

Table 21.

Inputs: CSN, CLK, STEP, EN and DI

V in L

V in H

V in Hyst

I

CSN in

I

CLK in

I

DI in

I

STEP in

R

EN in

C in

(1) input low level input hysteresis pull up current at input CSN pull down current at input CLK pull down current at input DI pull down current at input STEP resistance at input EN to GND input capacitance at input CSN,

CLK, DI and PWM

1.

Parameter guaranteed by design.

-

-

-

V

CSN

= VCC -1.5 V,

V

CLK

= 1.5 V

V

DI

= 1.5 V

V

STEP

= 1.5 V

V

EN in

= VCC

0.3*VCC 0.4*VCC

-

-

0.1*VCC -

V

V

V

-50 -25 -10 µA

10 25 50 µA

10 25 50 µA

10 25 50 µA

0 V < VCC < 5.3 V 10 15 pF

Table 22.

DI timing (see Figure 11

and

Figure 13 )

(1)

Symbol Parameter Test t t

CLK t

CLKH t

CLKL set CSN

Clock period

Clock high time

Clock low time

CSN set up time, CSN low before rising edge of CLK t set CLK t f in

CLK set up time, CLK high before rising edge of CSN t set DI

DI set up time t hold DI

DI hold time t r in

Rise time of input signal DI, CLK,

CSN

Fall time of input signal DI, CLK,

CSN

VCC = 5 V

VCC = 5 V

VCC = 5 V

VCC = 5 V

VCC = 5 V

VCC = 5 V

VCC = 5 V

VCC = 5 V

VCC = 5 V

1.

DI timing parameters tested in production by a passed/failed test:

T j

=-40°C/+25°C: SPI communication @5MHz; T j

=+125°C: SPI communication @4.25MHz

250

100

100

100

100

50

50

-

-

-

-

-

-

-

-

-

-

-

25

-

-

-

25

-

-

-

ns ns ns ns ns ns ns ns ns

28/40 Doc ID 11778 Rev 7

L9942 Logic with SPI - electrical characteristics

6.3 Outputs: DO, PWM

Table 23.

Outputs: DO, PWM

Symbol Parameter

V

DOoutL

V

PWMoutL

V

DOoutH

V

PWMoutH

Output low level output high level

VCC = 5 V, I

D

= 2 mA

VCC = 5 V, I

D

= -2 mA

I

DOoutLK

Tristate leakage current

I

PWMoutLK

Tristate leakage current

C out

(1)

V

CSN

= VCC,

0 V < V

DO

< VCC

Register3bit5=1 (NPWM)

0 V < V

PWM

< VCC

V

CSN

= VCC,

0 V < VCC < 5.3 V

0.2 0.4 V

VCC -

0.4

VCC -

0.2

-10 -

V

-10 -

10 15 pF

6.4 Output: DO timing

Table 24.

Output: DO timing (see Figure 12 and Figure 13 )

Symbol Parameter t t r DO f DO t en DO tri L

DO rise time C

L

= 100 pF, I load

= -1 mA

C

L

= 100 pF, I load

= 1 mA

DO enable time from tristate to low level

C

L

= 100 pF, I load up load to VCC

= 1 mA pullt dis DO L tri

DO disable time from low level to tristate

C

L

= 100 pF, I load up load to VCC

= 4 mA pullt en DO tri H

DO enable time from tristate to high level t d DO

DO delay time

C

L

= 100 pF, I load

= -1 mA pulldown load to GND t dis DO H tri

DO disable time from high level to tristate

C

L

= 100 pF, I load

= -4 mA pull-down load to GND

V

DO

< 0.3 VCC, V

DO

> 0.7

VCC, C

L

= 100 pF

-

-

-

-

-

-

-

50

50

100

100 ns ns

50 250 ns

50 250 ns

50 250 ns

50 250 ns

50 250 ns

Table 25.

CSN timing

Symbol Parameter t

CSN_HI,min

(1)

CSN high time, active mode

Transfer of SPI-command to

Input Register

1.

Parameter guaranteed by design.

2 µs

Doc ID 11778 Rev 7 29/40

Logic with SPI - electrical characteristics L9942

Table 26.

STEP timing

Symbol Parameter t

STEPmin

(1)

STEP low or high time

1.

Parameter guaranteed by design.

-

Figure 10.

Transfer timing diagram

2 µs t

CSN_HI,min

CSN high to low: DO enabled

CSN time

CLK

DI

DO

A2

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DI: data will be accepted on the rising edge of CLK signal actual data

A1 A0 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DO: data will change on the falling edge of CLK signal status information

D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D0 fault bit

Control and Status Register

CSN low to high: actual data is transfered to registers old data fault bit actual data

0 1 time new data

A2 A1 time time time

Figure 11.

Input timing

CSN t set CSN t

CLKH t

CLK t set CLK

0.8 VCC

0.2 VCC

CLK

0.8 VCC

0.2 VCC t set DI t hold DI t

CL KL

DI Valid Valid

0.8 VCC

0.2 VCC

30/40 Doc ID 11778 Rev 7

L9942

Figure 12.

SPI - DO valid data delay time and valid time

Logic with SPI - electrical characteristics t f in t r in

CLK

0.8 VCC

0.5 VCC

0.2 VCC t r DO

DO

(low to high)

0.8 VCC

0.2 VCC t d DO t f DO

DO

(high to low)

0.8 VCC

0.2 VCC

Figure 13.

DO enable and disable time t f i n t r i n

C S N

D O p u l l - u p l o a d t o V C C

0 . 8 V C C

5 0 %

0 . 2 V C C

5 0 % t e n D O t r i L t d i s D O L t r i

D O p u l l - d o w n l o a d t o G N D

5 0 % t e n D O t r i H t d i s D O H t r i

Doc ID 11778 Rev 7 31/40

Logic with SPI - electrical characteristics

Figure 14.

Timing of status bit 0 (fault condition)

CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transferred to D0

L9942

CSN

CLK time time

DI

D0

D0 time

DI: data is not accepted

0

D0: status information of data bit 0 (fault condition) will stay as long as CSN is low time

32/40 Doc ID 11778 Rev 7

L9942

7 Appendix

Appendix

7.2

7.3

The L9942 contains logic blocks designed to detect a motor stall caused by excessive mechanical load.During a motor stall condition the load current rises much faster than during normal operation. The L9942 measures this time and compares it to a programmed value.

This is done by summing the PWM on times for one full quadrant. For a full wave stepping this is just one value (step 0). For microstepping this includes 8 separate values added together, one for each step. This measurement is only done on phase A during the

quadrants where the current is increasing naturally (quadrants 1 and 3 of Figure 15

); e.g. stall detection is active during phase counter values 1 to 8 and 17 to 24 for DIR=0. During the quadrants where the current is decreasing fast decay recirculation interferes with accurate measurement of this time. If the sum of the PWM on time is less than a programmed threshold stored in D0-D7, stall is detected and indicated as a logic “1” in the stall (ST) bit found in register 6 bit 8 (

Figure 15

bottom). If bit 11 of register 6 is set to logical

“1” then the ST bit is mirrored to the PWM pin providing detection externally.The register values DT7-DT0 store the threshold value in 16us intervals. These bits can be found interstitially in register 3 (D0, D1), register4 (D2, D3, D4) and register5 (D5, D6, D7).

Care should be taken when deciding the threshold timing. Motor current slew rates are dependant on the driving voltage, the actual speed of the motor, the back EMF of the motor as well as the motor and the inductance. Be sure to set your threshold well away from what can be seen in normal operation at any temperature.

Step clock input

The Step clock input allows to run one device in micro-step mode, or several devices simultaneously with cost effective 8 bit µController. In case of the L9942, the SPI communication link provides only the settings for motor operation mode. Motor commutation as high duty process is outsourced to a parallel driven pin. Without this step clock input, the

SPI command would also have to clock the motor, leading to a high SPI speed. For full micro-step operation or simultaneous motor drive, an 8 bit µController could be rapidly overloaded.

Load current control and detection of overcurrent (shortages at outputs)

The L9942 controls load current in the two full bridges by using a pulls with modulation

(PWM) regulator. The mirrored output current of active HS switch is compared with a programmed reference current (e.g. in figure A2 HSA1 and HSB2). Bridge is switched off if current has exceeded the programmed limit value. A second comparator of the related LS switch uses the mirrored load current to detect an overcurrent to ground during ON state of

bridges (e.g. in Figure 16 LSA2 and LSB1). The event of shortage from output to supply

voltage VS is detectable, but short current between outputs is limited through PWM controller and so an overcurrent failure will not occur.

Load currents decrease more or less fast during OFF state of bridges depending on selected decay mode. Slow decay mode is released by activating the HS switches of the

Doc ID 11778 Rev 7 33/40

Appendix L9942 bridge and current comparator has as new reference the overcurrent limit. A shortage to ground can be detected, but not between the outputs.

Is it recommended to use the different fast decay modes too, especially in period if the load current has to reduce from step to step. The duration of fast decay can set by fixed time ore that it depends on the comparator signal utilizing the second current mirror at LS switch.

There can be monitored the undershoot of bridge current during OFF state.

Fast decay can be seen as switching the bridge in opposite direction, if it is compared to ON state before. The load current control at HS switch is not used, but the comparator is still active. The reference value is changed to overcurrent limit and a shortage to ground or now between the outputs too will result in a signal. The internal filter time of at least 4 us will inhibit the signal in many applications. Then you can use the mode “auto decay without any

delay time“ (On Section 5.1

mode 100). On page 12 you can find in the lower part of

Figure 3 the phase counter values, when fast decay as only part of mixed decay is used and

the shortages can be detected during a longer time. After this it is signalized in register 7 as

overcurrent in HS switch (e.g. in Figure 17 HSA1).

34/40 Doc ID 11778 Rev 7

L9942

Figure 15.

Stall detection

PWM activ detection

Load Current Rising During High Speed

Counter value is above threshold value.

Stall

Time

Threshold

16us *

Register 5 bit7 bit6 bit5

Register 4 Reg3 bit7 bit6 bit5 bit7 bit6

D7 D6 D5 D4 D3 D2 D1 D0

PWM activ detection PWM activ detection

Time

Stall

Threshold

PWM activ counter

Stall

Threshold

PWM activ counter

No

Stall Signal

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Activ sampling and threshold

0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

Activ sampling and threshold

Current Driver A

Phase Counter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Current Driver A

Adress of Current

Profile Entry

0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

Current Driver B

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

Current Driver B

Adress of Current

Profile Entry

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

STEP Signal

Micro Stepping Mode: DIR=0

Micro Stepping Mode: DIR=1

PWM activ detection

Load Current Rising During Low Speed or Stall

Time

Counter value is below threshold value.

PWM activ detection PWM activ detection

Stall

Threshold

PWM activ counter

Stall

Threshold

PWM activ counter

Stall Signal Stall Signal

Appendix

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

5 4 3 2

Activ sampling and threshold

1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2

1

0 1 2 3 4 5 6 7 8 7 6

Activ sampling and threshold

Current Driver A

Phase Counter 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Current Driver A

Adress of Current

Profile Entry

0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2

1

Current Driver B

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

Current Driver B

Adress of Current

Profile Entry

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

STEP Signal

Micro Stepping Mode: DIR=0

Micro Stepping Mode: DIR=1

Doc ID 11778 Rev 7 35/40

Appendix

Figure 16.

Reference generation for PWM control (switch on)

UP/Down

Count by

1,2,4,8

PhaseCounter

0 0 0

1

0 1

Register 0

Decay Mode

DM2 DM1 DM0

Slew Rate

SR1 SR0

StepMode DIR

0 0 0

1

Counter value changes after an signal at STEP to next one depending on selected stepping mode described in figure 3

(e.g. during micro stepping to value 2) .

STEP

0 0 0

0 1 2 3 0 1 2 3 0 1

A2 A1

2 3

A0

MUX MUX MUX

Address Calculation

Phase A

A3=0

Adr A[3..0]

A3=1

Adr neg(A[3..0])

A3 A2 A1 A0

Phase B

A3=0

Adr neg(A[3..0])

A3=1

Adr A[3..0]

Current-Profile Table stored in register2, ...6

1

1

1

1

1

1

0

0

0

1

1

0

1

1

0

1

0

0

1

0

1

1

1

0

1

1

0

1 1

1

1

1 0

0 1

0

0

0 1

0 0

1 0

0 0

Profile 8

Profile 7

Profile 6

5

5

5

9

5

Profile 5

Profile 4

Profile 3

5

5

5

Profile 2

Profile 1

Profile 0

5

5

Phase Counter

PWM Control With HS Current Monitoring

Overcurrent Detection At LS Switch

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Current Driver A

Adress of Current

Profile Entry

Phase A

0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

Current Driver B

Adress of Current

Profile Entry

Phase B

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

STEP Signal

5

DI

Register 1

0

DAC Scale

0 0 1

95 mA

DAC Phase B

1 1 1

100mA * 30/31 = 91.9mA

0 0

DAC Phase A

0 1 1 0

100mA * 6/31 = 18.4mA

5 bit DAC

Phase B

I

LIMIT B

5 bit DAC

Phase A

I

LIMIT A

I

REF

REF

200 uA

DAC

Full Scale

I

MAX

LS Current

Monitoring

(Overcurrentl)

-

+

2mA

2mA

OC

LSB1

-

+

-

HS Current

Monitoring

(Load control)

-

+

-

LIMIT

HSB2

2mA

-

+

I

QA2LIM

1000

2mA

-

+

-

LS1 on

QB1

HS2on

QB2

I

B

-

+

-

LIMIT

HSA1

2mA

-

+

I

QA1LIM

1000

HS Current

Monitoring

(Load control)

HS1 on

QA1

2mA

-

+

-

I

A -

+

-

-

+

2mA

2mA

OC

LSA2

-

+

-

-

-

+

LS2 on

QA2

LS Current

Monitoring

(Overcurrent)

L9942

36/40 Doc ID 11778 Rev 7

L9942 Appendix

Figure 17.

Reference generation for PWM control (decay)

UP/Down

Count by

1,2,4,8

1

Counter value changes after an signal at STEP to next one depending on selected stepping mode described in figure 1.2

(e.g. during micro stepping to value 2) .

PhaseCounter

0 0 0

1

0 1

Register 0

Decay Mode

DM2 DM1 DM0

Slew Rate

SR1 SR0

StepMode DIR

0 0 0

STEP

0 0 0

0 1 2 3 0 1

A2

MUX

2 3

A1

MUX

0 1 2 3

A0

MUX

Address Calculation

Phase A

A3=0

Adr A[3..0]

A3=1

Adr neg(A[3..0])

A3 A2 A1 A0

Phase B

A3=0

Adr neg(A[3..0])

A3=1

Adr A[3..0]

Current-Profile Table stored in register2, ...6

1

1

1

1

0

0

0

1

1

1

1

1

1

1

0

0

0

0

1

1

1

0

1

1

0

1

0

1 1

1 0

0 1

1 0

1

0

0

1

0 0

1 0

0 0

Profile 8

Profile 7

Profile 6

Profile 5

Profile 4

Profile 3

Profile 2

Profile 1

Profile 0

5

9

5

5

5

5

5

5

5

5

Phase Counter

Auto Decay

Slow Decay

Mixed Decay

Fast and Slow

Decay

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Current Driver A

Adress of Current

Profile Entry

Phase A

0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

Current Driver B

Adress of Current

Profile Entry

Phase B

8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

STEP Signal

5

DI

Register 1

0

DAC Scale

0 0 1

95 mA

DAC Phase B

1 1 1

95mA * 30/31 = 91.9mA

0 0

DAC Phase A

0 1 1 0

100mA * 6/31 = 18.4mA

5 bit DAC

Phase B

I

REF

REF

200 uA

DAC

Full Scale

I

MAX

HS Current

Monitoring

(Overcurrent)

I

LIMIT B

2mA

5 bit DAC

Phase A

OC

HSB1

2mA

-

-

+

+

-

I

LIMIT A

I

QB1

1000

-

+

HS1 on

QB1

Fast

Decay

-

-

+

2mA QB2 LS Current

Monitoring

(Load Control)

2mA

-

+

-

LIMIT

LSB2 -

+

-

LS2on

I

B

OC

HSA1

2mA

-

+

2mA

-

+

-

-

+

-

OC

HSB1

2mA

-

+

2mA

-

+

-

-

+

-

HS Current

Monitoring

(Overcurrent)

HS1 on

Slow

QA1

Decay

HS2 on

QA2

HS Current

Monitoring

I

A

(Overcurrent)

Doc ID 11778 Rev 7 37/40

Package information L9942

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

Figure 18.

PowerSSO24 mechanical data and package dimensions

Dim.

A

A2 a1 b c

D

(1) mm inch

Min.

Typ.

Max.

Min.

Typ.

Max.

2.15

0

0.33

0.23

10.10

2.45

2.35

0.084

0.10

10.50

0

0.51

0.013

0.32

0.009

0.398

0.0965

0.0925

0.003

0.020

0.012

0.413

E

(1) e e3

F

G

G1

H

Q

S

T

U

L

O h k

7.40

10.10

0.55

0.80

8.80

2.30

1.20

0.80

2.90

3.65

1.0

7.60

0.10

0.06

10.50

0.40

0.291

0˚ (min.), 8˚ (max.)

0.85

0.398

0.0217

0.031

0.346

0.090

0.299

0.004

0.002

0.413

0.016

0.0335

0.047

0.031

0.114

0.143

0.039

N

X

Y

4.10

6.50

4.90

(4)

10˚ (max)

4.70

7.10

5.50

(4)

0.161

0.256

0.192

(4)

0.185

0.279

0.216

(4)

(1) “D and E1” do not include mold flash or protusions.

Mold flash or protusions shall not exceed 0.15mm (0.006”)

(2) No intrusion allowed inwards the leads.

(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side

(4) Variation for small window leadframe option.

OUTLINE AND

MECHANICAL DATA

PowerSSO24

(Exposed pad down)

38/40 Doc ID 11778 Rev 7

7412818 I

L9942 Revision history

Table 27.

Document revision history

Date Revision

10-Nov-2005

04-May-2006

21-Sep-2006

09-Jul-2007

02-Feb-2009

15-May-2009

19-Sep-2013

1

2

3

4

5

6

7

Changes

Initial release.

Feature list updated.

Part numbers updated.

Feature list updated.

Table 21 on page 28 updated.

Updated the order codes (see Table 1: Device summary on page 1 ).

Changed the status from Preliminary data to Datasheet.

Updated the following tables: 2

,

9

,

14 ,

15

,

16 ,

17

,

18 ,

19 and 20

.

Updated the following chapters: 2.4

,

5.1

,

5.2

,

5.3

,

5.4

, 5.5

,

5.6

and

5.7

.

Updated

Figure 18: PowerSSO24 mechanical data and package dimensions on page 38

.

Updated Disclaimer.

Doc ID 11778 Rev 7 39/40

L9942

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

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40/40 Doc ID 11778 Rev 7