STMicroelectronics TSZ182H Datasheet
বিজ্ঞাপন
বিজ্ঞাপন
TSZ181H, TSZ182H
Datasheet
Automotive-grade, very high accuracy (25 µV), high bandwidth (3 MHz), high temperature (150 °C), zero-drift operational amplifiers
SOT23-5 SO8
Maturity status link
TSZ181H , TSZ182H
TSZ181 ,
Related products
TSZ182
For - 40/125 °C range
Features
• AEC-Q100 qualified
• Very high accuracy and stability:
– 25 µV max. offset voltage at 25 °C
– 44 µV offset voltage over full temperature range
• Rail-to-rail input and output
• Low supply voltage: 2.2 - 5.5 V
• Low power consumption: 1 mA max. at 5 V
• Gain bandwidth product: 3 MHz
• Extended temperature range: -40 to 150 °C
• Micropackage: SOT23-5, SO8
• Benefits:
– Higher accuracy without calibration
– Accuracy virtually unaffected by temperature change
Applications
• High accuracy signal conditioning
• Current measurement
• Sensor signal conditioning
• Automotive
Description
The TSZ181H and TSZ182H are a single and dual operational amplifier, featuring very low offset voltages with virtually zero-drift versus temperature changes. The
TSZ181H and TSZ182H offer rail-to-rail input and output, excellent speed/power consumption ratio, and 3 MHz gain bandwidth product, while consuming just 1 mA at
5 V. The device operates over an extended range of -40 to +150°C and features an ultra-low input bias current. These features make the TSZ181H and TSZ182H ideal for high-accuracy high-bandwidth sensor interfaces for automotive environment.
DS13229 - Rev 2 - December 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Package pin connections
Figure 1. Pin connections (top view)
TSZ181H, TSZ182H
Package pin connections
SOT23-5 (TSZ181H) SO8 (TSZ182H)
DS13229 - Rev 2 page 2/26
2
TSZ181H, TSZ182H
Absolute maximum ratings and operation conditions
Absolute maximum ratings and operation conditions
Table 1. Absolute maximum ratings
Symbol
V
CC
V id
V in
I in
T stg
T j
R th-ja
ESD
Differential input voltage (2)
Input current
Storage temperature
Junction temperature
Parameter
Thermal resistance junction to ambient
SO8
SOT23-5
Human body model (HBM)
Charged device model (CDM) (8)
Value
6
± V
CC
(V
CC
-)-0.2 to (V
CC
+)+0.2
10
-65 to 150
160
125
250
4
1.5
Unit
V
V
V mA
°C
°C
°C/W kV
1. All voltage values, except differential voltage, are with respect to network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. V
CC
- V in
must not exceed 6 V, Vin must not exceed 6 V.
4. Input current must be limited by a resistor in series with the inputs.
5. R th
are typical values.
6. Short-circuits can cause excessive heating and destructive dissipation.
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating.
8. Charged device model: all pins plus packages are charged together to the specified voltage and then discharged directly to ground.
Symbol
V
CC
V icm
T
Table 2. Operating conditions
Parameter
Supply voltage
Common mode voltage on input pins
Operating free-air temperature range
Value
2.2 to 5.5
(V
CC
-)-0.1 to (V
CC
+)+0.1
-40 to 150
Unit
V
V
°C
DS13229 - Rev 2 page 3/26
TSZ181H, TSZ182H
Electrical characteristics
3 Electrical characteristics
DS13229 - Rev 2
Table 3. Electrical characteristics (V
CC
+ = 2.2 V, V
CC
- = 0 V, V icm
= V
CC
/2, T = 25 °C, R
L
=10 kΩ connected to
V
CC
/2, unless otherwise specified)
Symbol
DC performance
Parameter Conditions Min.
Typ.
Max.
Unit
V
IO
I
IB
I
IO
CMR1
A vd
V
OH
V
OL
I
OUT
Input offset voltage
|∆V
IO
/∆T| Input offset voltage drift
Input bias current
(V
OUT
=V
CC
/2)
(V
OUT
=V
CC
/2)
Common-mode rejection ratio (3) ,
V ic
= 0 V to V
CC
, V
OUT
=V
CC
/2, R
L
>1 MΩ
Large signal voltage gain,
V
OUT
=0.5 V to (V
CC
- 0.5 V)
High-level output voltage,
V
OH
= V
CC
- V
OUT
Low-level output voltage
I sink
(V
OUT
= V
CC
)
I source
(V
OUT
=0 V)
I
CC
Supply current per channel,
V
OUT
= V
CC
/2, R
L
>1 MΩ
AC performance
T=25 °C
Tmin < T < Tmax
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T=25 °C
Tmin < T < Tmax
T=25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
4
2.37
3.5
1.9
3.5
30
60
96
90
115
112 130
98
15
10
6
4
0.7
40
70
30
70
35
54
0.15
200
400
400
600
1
1.2
µV
µV/°C pA dB mV mA
GBP
Φ m
G m
S
R
Gain bandwidth product,
R
L
= 10 kΩ, C
L
= 100 pF
Phase margin
Gain margin
Slew rate
T = 25 °C
Tmin < T < Tmax
R
L
= 10 kΩ, C
L
=100 pF
1.6
1.1
3
2.5
2.3
59
16
4.6
MHz degrees dB
V/µs t s en en-pp
C s
Settling time
Equivalent input noise voltage density
Voltage noise
Channel separation
T=25 °C
Tmin < T < Tmax
To 0.1%, Vin = 0.8 Vpp f = 1 kHz f =10 kHz f = 0.1 to 10 Hz f = 1 kHz
500
50
50
0.6
120 ns nV/√Hz
µVpp dB page 4/26
TSZ181H, TSZ182H
Electrical characteristics
Symbol t init
Parameter
Initialization time, G = 100
Conditions
T = 25 °C
Tmin < T < Tmax
Min.
Typ.
60
100
Max.
Unit
µs
1. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design.
3. CMR is defined as 20xLOG(∆
Vicm
/∆
Vio
).
4. Slew rate value is calculated as the average between positive and negative slew rates.
5. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization.
DS13229 - Rev 2 page 5/26
DS13229 - Rev 2
TSZ181H, TSZ182H
Electrical characteristics
Table 4. Electrical characteristics (V
CC
+ = 3.3 V, V
CC
- = 0 V, V icm
= V
CC
/2, T = 25 °C, R
L
=10 kΩ connected to
V
CC
/2, unless otherwise specified)
Symbol
DC performance
Parameter Conditions Min.
Typ.
Max.
Unit
V
IO
I
IB
I
IO
CMR1
CMR2
A vd
V
OH
V
OL
I
OUT
SR t s e n en-pp
C s
Input offset voltage
|∆V
IO
/∆T| Input offset voltage drift
Input bias current (V
OUT
=V
CC
/2)
(V
OUT
=V
CC
/2)
Common-mode rejection ratio (3) ,
Vic=0 V to V
CC
, V
OUT
=V
CC
/2, R
L
>1 MΩ
Common-mode rejection ratio (3)
,
V
OUT
=V
CC
/2, R
L
>1 MΩ
Large signal voltage gain,
V
OUT
=0.5 V to (V
CC
-0.5 V)
High-level output voltage,
V
OH
= V
CC
- V
OUT
Low-level output voltage
I sink
(V
OUT
= V
CC
)
I source
(V
OUT
=0 V)
I
CC
Supply current per channel,
V
OUT
= V
CC
/2, R
L
>1 MΩ
AC performance
GBP
Gain bandwidth product,
R
L
=10 kΩ, C
L
=100 pF
Φ m
G m
Phase margin
Gain margin
Settling time
Equivalent input noise voltage density
Voltage noise
Channel separation
T = 25 °C
Tmin < T < Tmax
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C,
V ic
= 0 to V
CC
-1.8 V
Tmin < T < Tmax,
V ic
= 0 to V
CC
-2 V
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
R
L
= 10 kΩ, C
L
= 100 pF
T = 25 °C
Tmin < T < Tmax
To 0.1%, Vin = 1.2 Vpp f=1 kHz f = 10 kHz f = 0.1 to 10 Hz f=1 kHz
2
30
60
104 120
100
106 132
104
120 138
110
16
10
7.1
6
3.8
11
15
11
0.7
2
1.5
2.8
56
15
2.6
4.5
2.1
550
40
40
0.5
120
40
70
30
70
30
49
0.15
200
400
400
600
1
1.2
µV
µV/°C pA dB mV mA
MHz degrees dB
V/µs ns nV/√Hz
µVpp dB page 6/26
TSZ181H, TSZ182H
Electrical characteristics
Symbol t int
Parameter
Initialization time, G=100 (5)
Conditions
T = 25 °C
Tmin < T < Tmax
Min.
Typ.
60
100
Max.
Unit
µs
1. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design.
3. CMR is defined as 20xLOG(∆
Vicm
/∆
Vio
).
4. Slew rate value is calculated as the average between positive and negative slew rates.
5. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization.
DS13229 - Rev 2 page 7/26
DS13229 - Rev 2
TSZ181H, TSZ182H
Electrical characteristics
Table 5. Electrical characteristics (V
CC
+ = 5 V, V
CC
- = 0 V, V icm
=V
CC
/2, T = 25 °C, R
V
CC
/2, unless otherwise specified)
L
=10 kΩ connected to
Symbol
DC performance
Parameter Conditions Min.
Typ.
Max.
Unit
V
IO
Input offset voltage
|∆V
IO
/∆T| Input offset voltage drift
I
IB
I
IO
CMR1
CMR2
SVR1
A vd
OUT
=V
CC
/2)
Input offset current
OUT
=V
CC
/2)
Common-mode rejection ratio (3) ,
Vic=0 V to V
CC
, V
OUT
=V
CC
/2, R
L
>1 MΩ
Common-mode rejection ratio (3) ,
V ic
=0 V to V
CC
, V
OUT
=V
CC
/2, R
L
>1 MΩ
Supply voltage rejection ratio
V
CC
=2.2 to 5.5 V, V ic
=0 V, R
L
>1 MΩ
Large signal voltage gain,
V
OUT
=0.5 V to (V
CC
- 0.5 V)
EMIRR
V
OH
V
OL
I
OUT
High-level output voltage,
V
OH
= V
CC
- V
OUT
Low-level output voltage
I sink
(V
OUT
= V
CC
)
I source
(V
OUT
=0 V)
T = 25 °C
Tmin < T < Tmax
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C,
V ic
= 0 to V
CC
-1.8 V
Tmin < T < Tmax,
Vic = 0 to V
CC
-2 V
T = 25 °C
Tmin < T < Tmax
T=25 °C
Tmin < T < Tmax
V
RF
=100 mVp, f=400 MHz
V
RF
=100 mVp, f=900 MHz
V
RF
=100 mVp, f=1800 MHz
VRF=100 mVp, f=2400 MHz
T=25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
T = 25 °C
Tmin < T < Tmax
1
30
60
108 126
106
112 136
110
20
14
15
9
105 123
104
120 144
110
52
52
72
85
18
13
29
25
0.8
40
70
30
70
25
44
0.15
200
400
400
600
1
1.2
µV
µV/°C pA dB mV mA
I
CC
Supply current per channel,
V
OUT
= V
CC
/2, R
L
>1 MΩ
AC performance
GBP
Gain bandwidth product,
R
L
=10 kΩ, C
L
=100 pF
Φ m
G m
SR
Phase margin
Gain margin
T=25 °C
Tmin < T < Tmax
R
L
=10 kΩ, C
L
=100 pF
T=25 °C
2
1.5
3
56
15
2.9
4.7
MHz
Degrees dB
V/µs page 8/26
TSZ181H, TSZ182H
Electrical characteristics
Symbol
SR t e s n en-pp t
C s init
Settling time
Equivalent input noise voltage density
Voltage noise
Parameter
Channel separation
Initialization time, G=100 (7)
Conditions
Tmin < T < Tmax
To 0.1%, Vin=1.5 Vpp
To 0.01%, Vin=1 Vpp f = 1 kHz f = 10 kHz f=0.1 to 10 Hz f = 100 Hz
T = 25 °C
Tmin < T < Tmax
Min.
2.4
Typ.
600
4
37
37
0.4
135
60
100
Max.
Unit
V/µs ns
µs nV/√Hz
µVpp dB
µs
1. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design
3. CMR is defined as 20xLOG(∆
Vicm
/∆
Vio
).
4. SVR is defined as 20xLOG(∆Vcc/∆
Vio
).
5. EMIRR is defined as -20Log(VRF_Peak/∆
Vio
), tested on the MiniSO8 package, RF injection on the IN- pin.
6. Slew rate value is calculated as the average between positive and negative slew rates.
7. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization.
DS13229 - Rev 2 page 9/26
DS13229 - Rev 2
Figure 2. Supply current vs supply voltage
TSZ181H, TSZ182H
Electrical characteristics
Figure 3. Input offset voltage distribution at
V
CC
= 5 V
Figure 4. Input offset voltage distribution at
V
CC
= 3.3 V
Figure 5. Input offset voltage distribution at
V
CC
= 2.2 V
Figure 6. Input offset voltage distribution at
V
CC
= 5 V, T = 150 °C
Figure 7. Input offset voltage distribution at
V
CC
= 5 V, T = -40 °C page 10/26
DS13229 - Rev 2
Figure 8. Input offset voltage distribution at
V
CC
=2.2 V, T = 150 °C
TSZ181H, TSZ182H
Electrical characteristics
Figure 9. Input offset voltage distribution at
V
CC
=2.2 V, T = -40 °C
Figure 10. Input offset voltage vs supply voltage
Figure 11. Input offset voltage vs input common mode at V
CC
= 5 V
Figure 12. Input offset voltage vs input common mode at V
CC
= 3.3 V
Figure 13. Input offset voltage vs input common mode at V
CC
= 2.2 V page 11/26
DS13229 - Rev 2
Figure 14. Input offset voltage vs temperature
TSZ181H, TSZ182H
Electrical characteristics
Figure 15. V
OH
vs supply voltage
Figure 16. V
OL
vs supply voltage Figure 17. Output current vs output voltage at
V
CC
= 5 V
Figure 18. Output current vs. output voltage at
V
CC
= 2.2 V
Figure 19. Input bias current vs common-mode at
V
CC
= 5 V page 12/26
DS13229 - Rev 2
Figure 20. Input bias current vs. temperature at
V
CC
= 5 V
TSZ181H, TSZ182H
Electrical characteristics
Figure 21. Output rail linearity
Figure 22. Bode diagram at V
CC
=5 V Figure 23. Bode diagram at V
CC
=2.2 V
Figure 24. Bode diagram at V
CC
=3.3 V Figure 25. Open loop gain vs frequency page 13/26
DS13229 - Rev 2
TSZ181H, TSZ182H
Electrical characteristics
Figure 26. Positive slew rate vs supply voltage Figure 27. Negative slew rate vs supply voltage
Figure 28. Noise 0.1 – 10 Hz vs time Figure 29. Noise vs frequency
Figure 30. Output overshoot vs load capacitance
Figure 31. Small signal V
CC
= 5 V page 14/26
DS13229 - Rev 2
Figure 32. Small signal V
CC
= 2.2 V
TSZ181H, TSZ182H
Electrical characteristics
Figure 33. Large signal V
CC
= 5 V
Figure 34. Large signal V
CC
= 2.2 V
Figure 35. Negative overvoltage recovery
V
CC
= 2.2 V
Figure 36. Positive overvoltage recovery V
CC
= 5 V Figure 37. Output impedance vs frequency page 15/26
DS13229 - Rev 2
TSZ181H, TSZ182H
Electrical characteristics
Figure 38. Settling time positive step (-2 V to 0 V)
Figure 39. Settling time negative step (2 V to 0 V) at t=0
Figure 40. Settling time positive step (-0.8 V to 0 V) Figure 41. Settling time negative step (0.8 V to 0 V)
Figure 42. Maximum output voltage vs frequency
0
Figure 43. Crosstalk vs frequency page 16/26
Figure 44. PSSR vs frequency
TSZ181H, TSZ182H
Electrical characteristics
DS13229 - Rev 2 page 17/26
4
4.1
TSZ181H, TSZ182H
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
SO8 package information
Figure 45. SO8 package outline
DS13229 - Rev 2
Dim.
D
E
E1 e h
L
L1 k
A
A1
A2 b c
Min.
0.25
0.4
0
0.1
1.25
0.28
0.17
4.8
5.8
3.8
4.9
6
3.9
1.27
mm
Typ.
Table 6. SO-8 mechanical data
Min.
Max.
1.75
0.25
0.48
0.23
5
6.2
4
0.004
0.049
0.011
0.007
0.189
0.228
0.15
0.5
1.27
0.01
0.016
1.04
8 ° 1 °
Inches
Typ.
0.193
0.236
0.154
0.05
0.04
Max.
0.069
0.01
0.019
0.01
0.197
0.244
0.157
0.02
0.05
8 ° page 18/26
Dim.
ccc
Min.
mm
Typ.
Max.
0.1
Min.
TSZ181H, TSZ182H
SO8 package information
Inches
Typ.
Max.
0.004
DS13229 - Rev 2 page 19/26
4.2
SOT23-5 package information
Figure 46. SOT23-5 package outline
TSZ181H, TSZ182H
SOT23-5 package information
DS13229 - Rev 2
Ref.
e
E
F
L
K
A
A1
A2
B
C
D
D1
Min.
0.90
0.90
0.35
0.09
2.80
2.60
1.50
0.10
0 degrees
1.05
0.40
0.15
2.90
1.90
0.95
2.80
1.60
0.35
Table 7. SOT23-5 mechanical data
Dimensions
Millimeters
Typ.
1.20
Max.
1.45
0.15
1.30
0.50
0.20
3.00
Min.
0.035
0.035
0.014
0.004
0.110
3.00
1.75
0.60
10 degrees
0.102
0.059
0.004
0 degrees
Inches
Typ.
0.047
0.041
0.016
0.006
0.114
0.075
0.037
0.110
0.063
0.014
0.118
0.069
0.024
10 degrees
Max.
0.057
0.006
0.051
0.020
0.008
0.118
page 20/26
5
TSZ181H, TSZ182H
Ordering information
Ordering information
Table 8. Ordering information
Order code
TSZ181HYLT
Package
SO8
SOT23-5
Packing
Tape and reel
Marking
TSZ182H
K229
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 &
Q002 or equivalent.
DS13229 - Rev 2 page 21/26
TSZ181H, TSZ182H
Revision history
Date
20-Jan-2020
09-Dec-2020
Version
1
2
Table 9. Document revision history
Changes
Initial release.
Added new part number TSZ181H and new Section 4.2 SOT23-5 package information
Updated package figure on the cover page, Figure 1
and new order code in
.
DS13229 - Rev 2 page 22/26
TSZ181H, TSZ182H
Contents
Contents
DS13229 - Rev 2 page 23/26
TSZ181H, TSZ182H
List of tables
List of tables
Table 3. Electrical characteristics (V
Table 4. Electrical characteristics (V
Table 5. Electrical characteristics (V
DS13229 - Rev 2 page 24/26
TSZ181H, TSZ182H
List of figures
List of figures
Figure 3. Input offset voltage distribution at V
Figure 4. Input offset voltage distribution at V
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Input offset voltage distribution at V
= 2.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Input offset voltage distribution at V
= 5 V, T = 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Input offset voltage distribution at V
= 5 V, T = -40 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Input offset voltage distribution at V
=2.2 V, T = 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Input offset voltage distribution at V
=2.2 V, T = -40 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Input offset voltage vs input common mode at V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12. Input offset voltage vs input common mode at V
= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13. Input offset voltage vs input common mode at V
= 2.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 17. Output current vs output voltage at V
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 18. Output current vs. output voltage at V
= 2.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 19. Input bias current vs common-mode at V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 20. Input bias current vs. temperature at V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 35. Negative overvoltage recovery V
Figure 36. Positive overvoltage recovery V
DS13229 - Rev 2 page 25/26
TSZ181H, TSZ182H
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DS13229 - Rev 2 page 26/26
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