STMicroelectronics VIPER0P Datasheet
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SO16 narrow
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VIPer0P
VIPer0P
Datasheet
Zero-power off-line high voltage converter
Features
• Smart stand-by architecture using the zero-power mode (ZPM)
• ZPM management by MCU easily realizable
• 800 V avalanche-rugged power MOSFET allowing ultra wide VAC input range to be covered
• Embedded HV startup and sense-FET
• Current mode PWM controller
• Drain current limit protection (OCP)
• Wide supply voltage range: 4.5 V to 30 V
• Self-supply option allows to remove the auxiliary winding or bias components
• Minimized system input power consumption:
– Less than 4 mW @ 230 V
AC
in ZPM
– Less than 10 mW @ 230 V
AC
in no-load condition
– Less than 400 mW @ 230 V
AC
with 250 mW load
• Jittered switching frequency reduces the EMI filter cost
– 60 kHz ± 7% (type L)
– 120 kHz ± 7% (type H)
• Embedded E/A with 1.2 V reference and separate ground for easy negative voltage setting
• Protections with automatic restart: overload/short circuit (OLP), max. duty cycle counter, V
CC
clamp
• Pulse-skip protection to prevent flux-runaway
• Embedded thermal shutdown
• Built in soft start for improved system reliability
Applications
• SMPS for home appliances, home automation, industrial, lighting and consumers
Figure 1. Basic application schematic
~ AC
Din Rin
Cin
Ccl
Rcl
T Dout
Cout
Vout
GND
Tactile switch MCU
ON
VCC
VIPER0P
DRAIN
OFF
COMP FB EAGND SGND PGND
C1
Cs R1
R2
DS11301 - Rev 3 - October 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
VIPer0P
Description
Description
The device is a high-voltage converter that smartly integrates an 800 V avalanche rugged power MOSFET with
PWM current-mode control. The power MOSFET with 800 V breakdown voltage allows extended input voltage range to be applied, as well as to reduce the size of the DRAIN snubber circuit. This IC is capable of meeting the most stringent energy-saving standards as it has very low consumption and operates in pulse frequency modulation under light load. The zero-power mode (ZPM) feature enables the IC to work in an idle state, where the system is totally shutdown. An MCU can be easily connected to the IC for smart ZPM management and it can be supplied by the IC itself during the idle state. The design of flyback, buck and buck boost converters is supported. The integrated HV startup, sense FET, error amplifier and oscillator with jitter allow a complete application to be designed with a minimum component count. In flyback non isolated topology, a negative output voltage is easily set thanks to the integrated error amplifier with separate ground.
DS11301 - Rev 3 page 2/36
VIPer0P
Pin setting
2
Pin setting
Figure 2. Connection diagram
PGND
EAGND
VCC
SGND
FB
COMP
ON
OFF
VIPer0P
DRAIN
DRAIN
DRAIN
DRAIN
N.C.
N.C.
N.C.
N.C.
GIPD210420151108MT
Note: The PCB copper area for heat dissipation has to be provided under the DRAIN pins.
Table 1. Pin description
SO16N Name Function
1
2
3
4
5
6
7
8
9 to12
PGND
VCC
Power ground and MOSFET source.
The pulsed current flowing through the Power MOSFET must be closed on this pin.
The pin must be connected to the same ground plan of SGND with the shortest track.
EAGND
Error amplifier ground reference. In case of non-isolated flyback converter with negative output voltage, this pin can be connected directly to the negative rail. Otherwise, in case of positive output voltage, the pin must be shorted to SGND.
Controller supply.
An external storage capacitor has to be connected across this pin and SGND. The pin, internally connected to the high-voltage current source, provides the VCC capacitor charging current at startup and, if self-supply mode is selected, also during steady-state operation. A small bypass capacitor (0.1 μF typ.) in parallel, placed as close as possible to the IC, is also recommended, for noise filtering purpose.
SGND
FB
COMP
Signal ground.
All of the groundings of bias components must be tied to a trace going to this pin and kept separate from the pulsed current return.
Direct feedback.
It is the inverting input of the internal transconductance E/A, which is internally referenced to 1.2 V with respect to EAGND. In case of non-isolated converter, the output voltage information is directly fed into the pin through a voltage divider. In case of primary regulation, the FB voltage divider is connected to the VCC. The E/A is disabled soldering FB to EAGND.
Compensation.
It is the output of the internal E/A. A compensation network is placed between this pin and SGND to achieve stability and good dynamic performance of the control loop. In case of secondary feedback, the internal E/A must be disabled and the COMP directly driven by the optocoupler to control the DRAIN peak current setpoint.
ON
OFF
N.C.
13 to 16 DRAIN
ZPM exit.
When the device is in ZPM, the IC is reactivated by forcing this pin to SGND for a debounce time, t
DEB_ON
Due to the extremely low level of energy available while in ZPM, the pin can be noise sensitive. A film-type bypass capacitor from the pin to SGND is therefore recommended in a noisy environment to prevent improper startup of the
.
device. An internal pull-up resistor keeps the pin voltage at V
ON
level during normal operation.
ZPM enter. To enter ZPM this pin has to be forced to SGND, for a debounce time t
DEB_OFF keeps the pin voltage at V
OFF
level during normal operation.
. An internal pull-up resistor
These pins are not internally connected and must be left floating in order to get a safe clearance distance.
MOSFET drain . The internal high-voltage current source sinks current from this pin to charge the VCC capacitor at startup and during steady-state operation.
These pins are mechanically connected to the internal metal PAD of the MOSFET in order to facilitate heat dissipation. On the PCB, some copper area must be placed under these pins in order to decrease the total junction-to-ambient thermal resistance thus facilitating the power dissipation.
DS11301 - Rev 3 page 3/36
3
DS11301 - Rev 3
VIPer0P
Electrical and thermal ratings
Electrical and thermal ratings
Table 2. Absolute maximum ratings
Symbol Pin
Min.
Max.
V
DS
I
DRAIN
13 to 16
13 to 16
Drain-to-source (ground) voltage
Pulsed drain current (pulse-width limited by SOA)
-0.3
800
2
V
V
EAGND
CC
2
3
EAGND voltage (referred to VCC)
EAGND voltage (referred to SGND)
VCC voltage (referred to EAGND)
VCC voltage (referred to SGND)
0.3
0.3
-0.3
35
-0.3
35
I
CC
3 VCC internal Zener current
FB voltage (referred to EAGND)
FB voltage (referred to VCC)
COMP voltage (referred to SGND)
COMP voltage (referred to VCC)
30
-0.3
V
V
FB
COMP
5
6
ON voltage (referred to SGND)
ON voltage (referred to VCC)
OFF voltage (referred to SGND)
OFF voltage (referred to VCC)
-35 0.3
-0.3
-35 0.3
-0.3
5.5
V
V
ON
OFF
7
8
-35 0.3
-0.3
5.5
-35 0.3
P
TOT
T j
T
STG
Power dissipation @ T amb
< 50 °C
Junction temperature operating range
Storage temperature
1. Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. Voltage is internally limited.
1
-40 150
-55 150
Unit
V
A
V mA
W
°C
°C
V
V
V
V
V
V
V
V
V
V
V
Table 3. Thermal data
Symbol Parameter
R thJP
R thJA
Thermal resistance junction-pin (dissipated power 1 W)
Thermal resistance junction-ambient (dissipated power 1 W)
Thermal resistance junction-ambient (dissipated power 1 W)
1. Derived by characterization.
2. When mounted on a standard single side FR4 board with 100 mm² (0.155
2 inch) of Cu (35 µm thick).
Max. value
SO16N
35
110
80
Unit
°C/W
Symbol
I
AR
E
AS
Parameter
Avalanche current
Table 4. Avalanche characteristics
Single pulse avalanche energy (1)
Conditions
Pulse-width limited by T
Jmax
Repetitive and non-repetitive
Starting T
J
= 25 °C
I
AS
= I
AR
; V
DS
= 100 V
Min.
Typ.
Max.
Unit
0.8
A
0.5
mJ page 4/36
3.1
VIPer0P
Electrical characteristics
1. Parameter derived by characterization.
Electrical characteristics
T j
= -40 to 125 °C, V
CC
= 9 V (unless otherwise specified).
Symbol Parameter
V
BVDSS
Breakdown voltage
I
DSS
R
DS(on)
Drain-source leakage current
Static drain-source on-resistance
C
OSS EQ
Equivalent output capacitance
Table 5. Power section
Test conditions
I
DRAIN
= 1 mA,
V
COMP
= SGND, T
J
= 25 °C
V
DS
= 400 V, V
COMP
= SGND, T
J
= 25 °C
I
DRAIN
= 200 mA, T
J
= 25 °C
I
DRAIN
= 200 mA, T
J
= 125 °C
V
GS
= 0; V
DS
= 0 to 640 V,
T
J
= 25 °C
Min.
Typ.
Max.
Unit
800 V
1
20
40
µA
Ω
10 pF
DS11301 - Rev 3 page 5/36
VIPer0P
Electrical characteristics
Table 6. Supply section
Symbol Parameter
High voltage startup current source
V
BVDSS_SU
Breakdown voltage of startup MOSFET
V
HV_START
Drain-source start up voltage
Test conditions Min. Typ. Max. Unit
800
40 80
V
V
I
I
I
R
G
CH1
CH2
CH3
Startup resistor
VCC charging current at startup
VCC charging current at startup
Max. VCC charging current in selfsupply
V
DRAIN
= 400 V, V
DRAIN
= 600 V
V
FB
> V
FB_REF
,
V
CC
= 0 V, T
J
= 25 °C
V
FB
> V
FB_REF
, V
DRAIN
= 100 V
V
CC
= 1 V, T
J
= 25 °C
V
FB
> V
FB_REF
, V
DRAIN
= 100 V
V
CC
= 6 V, T
J
= 25 °C
V
FB
> V
FB_REF
, V
DRAIN
= 100 V
28
0.7
2.3
6.4
34
1
3.2
7.8
40
1.3
4.1
9.2
MΩ mA
IC supply and consumptions
I
V
CC
V
CCclamp
I clamp max t clamp max
V
CCon
V
CSon
V
CCoff
I q
I q_ZPM
CC
Operating voltage range
Clamp voltage
Clamp shutdown current
Clamp time before shutdown
V
CC startup threshold
HV current source turn-on threshold
UVLO
Quiescent current
Quiescent current in ZPM
Operating supply current, switching
I referred to SGND, V
EAGND
= 0 referred to EAGND, V
EAGND
< 0
CC
V
= I
CC clamp_max
> V
CCclamp
4.5
30
29
32.5
35
5
30
35
41
V
V mA ms
V
FB
= 1.2 V,V
DRAIN
= 400 V
V
CC
falling
V
FB
= 1.2 V,V
DRAIN
= 400 V
Not switching, V
FB
> V
FB_REF
7.5
4
3.75
8
4.25
4
8.5
4.5
4.25
0.25 0.35
V
V
V mA
Not switching, V
FB
> V
FB_REF
, V
DRAIN
= 325 V 20
F
OSC
= 60 kHz, V
DS
= 150 V, V
COMP
=1.2 V 0.6
0.9
1.2
F
OSC
= 120 kHz, V
DS
= 150 V, V
COMP
=1.2 V 0.9
1.2
1.5
µA mA
1. Current supplied only during the main MOSFET OFF time.
E/A
Symbol
V
EAGND
V
FB_REF
V
FB_DIS
I
FB PULL UP
G
M
I
COMP1
I
COMP2
R
COMP(DYN)
Parameter
E/A ground reference voltage
E/A reference voltage
E/A disable voltage
Pull-up current
Trans conductance
Max. source current
Max. sink current
Dynamic resistance
Table 7. Controller section
Test conditions
Referred to SGND
Referred to EAGND
Referred to EAGND
V
COMP
= 1.5 V, V
FB
> V
FB_REF
V
FB
= 0.5 V, V
COMP
= 1.5 V
V
FB
= 2 V, V
COMP
= 1.5 V
V
COMP
= 2.7 V, V
FB
= EAGND
Min.
300
75
75
55
-20
1.175
150
0.5
Typ.
1.2
250
1
550
100
100
65
Max.
Unit
700
125
125
75
0
1.225
350
1.5
µA/V
µA
µA kΩ
V
V mV
µA
DS11301 - Rev 3 page 6/36
VIPer0P
Electrical characteristics
Symbol
I
DLIM
Parameter
V
COMPH
V
COMPL
OLP and timing
Current limitation threshold
PFM threshold
Drain current limitation
Test conditions
Referred to SGND
Referred to SGND
I t t
I
2 f
DLIM_PFM
OVL
OVL_MAX
Power coefficient
Drain current limitation at light load
Overload delay time
Max. overload delay time
T
J
= 25 °C
VIPER0PL
VIPER0PH
T
J
= 25 °C
V
COMP
= V
COMPL
F
OSC
= 60 kHz (VIPER0PL)
F
OSC
= 120 kHz (VIPER0PH)
F
OSC
= F
OSC_MIN
(VIPER0PL)
F
OSC
= F
OSC_MIN
(VIPER0PH) t
SS
Soft-start time t
ON_MIN
Minimum turn-on time
V
FB
= V
FB_REF
V
CC
= 9 V, V
COMP
= 1 V, t
RESTART
ZPM
V
OFFth
V
OFF
R
OFF t
DEB_OFF
V
ONth
V
ON
R
ON t
DEB_ON
Oscillator
Restart time after fault
ZPM entering threshold
Operating voltage level
Pull-up resistor on OFF pin
OFF debounce time
ZPM exiting threshold
Operating voltage level
Pull-up resistor on ON pin
ON debounce time
During normal operation V
Pin floating
During ZPM
Pin floating
F
OSC
Switching frequency
VIPER0PL
VIPER0PH
F
OSC_MIN
F
D
Minimum switching frequency
Modulation depht
F
M
Modulation frequency
D
MAX
Max. duty cycle
Thermal shutdown
T
SD
Thermal shutdown temperature
1. See
Section 5.10 Pulse frequency modulation .
2. Parameter assured by design, characterization, and statistical correlation.
3. See
.
CC
= 7 V
Min.
2.65
0.7
Typ.
3.2
0.9
Max.
3.75
1.1
Unit
V
V
380
-10%
60
400
9.6
19.2
95
420 mA
+10% A 2 ·kHz
130 mA
45
180
360
230
50
200
400
8
55
220
440 ms
350 ms ms ns s 1
1 0.75
3.75
32
0.75
3.75
32
41
10
1
1.25
4.75
50
16
1.25
4.75
50
35 ms
V
V kΩ
µs
V
V kΩ
41
20
54
108
13.5
60
120
15
±7% F
OSC
260
66
132
16.5
70 80 kHz kHz kHz
Hz
%
150 160 °C
DS11301 - Rev 3 page 7/36
VIPer0P
Typical electrical characteristics
4
Typical electrical characteristics
Figure 3. I
DLIM
vs T
J
1.1
I
DLIM
/(I
DLIM
@25°C)
1
0.9
-50 0 50
T j
(°C)
100 150
GIPD160720151000MT
1.05
Figure 5. F
OSC
vs T
J
F
OSC
/(F
OSC
@25°C)
1
0.95
-50 0
T j
50
(°C)
100 150
GIPD160720151002MT
Figure 7. V
FB_REF
vs T
J
1.05
VFB_REF / (VFB_REF @ 25 ° C)
1
0.95
-50 0 50
T j
(°C)
100 150
GIPD160720151005MT
Figure 4. I
ON
vs V
ON
30
I
ON
(µA)
25
20
15
10
5
0
2.75
3.25
V
ON
3.75
(V)
4.25
GIPD160720151001MT
Figure 6. V
HV_START
vs T
J
1.5
V
HV_START
/(V
HV_START
@25°C)
1.25
1
0.75
0.5
-50 0
T j
50
(°C)
100 150
GIPD160720151004MT
Figure 8. Quiescent current I q
vs T
J
1.2
I q
/(I q
@25°C)
1.1
1
0.9
0.8
-50 0 50
T j
(°C)
100 150
GIPD160720151006MT
DS11301 - Rev 3 page 8/36
Figure 9. Operating current I
CC
vs T
J
1.1
I
CC
/(I
CC
@25°C)
1
VIPer0P
Typical electrical characteristics
Figure 10. I
COMP
vs T
J
1.1
I
COMP
/(I
COMP
@25°C)
1
0.9
-50
1
0.8
-50
0 50
T j
(°C)
100 150
GIPD160720151007MT
1.5
I
CH1
/(I
CH1
@25°C)
Figure 11. I
CH1
vs T
J
1.25
1
0.75
0.5
-50 0
T j
100 150
GIPD160720151008MT
1.2
I
CH2
/(I
CH2
@25°C)
Figure 13. I
CH2
vs T
J
0
T j
50
(°C)
100 150
GIPD160720151010MT
0.9
-50 0
T j
50
(°C)
100 150
GIPD160720151015MT
1.1
1
Figure 12. I
CH1
vs V
DRAIN
1.2
I
CH1
/(I
CH1
@V
DRAIN
=100V)
0.9
0.8
50 100 150 200
V
DRAIN
250
[V]
300 350 400
GIPD160720151009MT
1.1
0.9
1
Figure 14. I
CH2
vs V
DRAIN
1.2
I
CH2
/(I
CH2
@V
DRAIN
=100V)
0.8
50 100 150 200
V
DRAIN
250
[V]
300 350 400
GIPD160720151011MT
DS11301 - Rev 3 page 9/36
VIPer0P
Typical electrical characteristics
1.2
I
CH3
/(I
CH3
@25°C)
1
Figure 15. I
CH3
vs T
J
0.8
-50 0
T j
50
(°C)
100 150
GIPD160720151012MT
1.2
G
M
/(G
M
@25°C)
Figure 17. G
M
vs T
J
1.1
1
0.9
Figure 16. I
CH3
vs V
DRAIN
1.2
I
CH3
/(I
CH3
@V
DRAIN
=100V)
0.8
50 100 150 200
V
DRAIN
250
[V]
300 350 400
GIPD160720151013MT
Figure 18. R
DS(on)
vs T
J
2.5
R
DS(on)
/(R
DS(on)
@25°C)
1 1.5
0.8
-50 0
T j
50
(°C)
100 150
GIPD160720151014MT
Figure 19. Static drain source on resistance
1.2
R
DS(on)
/(R
DS(on)
@I
DRAIN
=200mA)
1.1
1
0.9
0.8
0 100
T= 25°C
200
I
DRAIN
[mA]
300 400 500
GIPD160720151017MT
0.5
-50 0 50
T j
(°C)
100 150
GIPD160720151016MT
Figure 20. Output characteristic
900
800
700
600
500
400
300
200
100
0
0
I
DRAIN
[mA]
1
T= 50°C
T= 25°C
T= 125°C
2 3 4
V
D-S
[V]
5 6 7 8
GIP D160720151018M T
DS11301 - Rev 3 page 10/36
VIPer0P
Typical electrical characteristics
0.9
-50
Figure 21. V
BVDSS
1.1
V
BVDSS
/( V
BVDSS
@25°C)
1
0
T j
50
(°C)
vs T
J
100 150
GIPD160720151019MT
0.8
0.6
0.4
0.2
0
0
Figure 22. Max avalache energy vs T
J
1.2
EAS/(EAS@ 25°C)
1
15 30 45 60
T j
75 90 105 120 135 150
(°C)
GIPD200820151330MT
Figure 23. SOA SO16N package
1.0E+01
I
DRAIN
[A]
1.0E+00
1.0E-01
Operation in
this
area
is
DS(on) limited by Max R
10µs
100µs
1ms
10ms
1.0E-02
1.0E-03
1.0E-04
1.0E-05
0 1 10
V
D-S
[V]
100
Tj=150° C
Tc=25°C
Single pulse
1,000
GIPD160720151020MT
DS11301 - Rev 3 page 11/36
5
5.1
General description
Block diagram
Figure 24. Block diagram
VIPer0P
General description
5.2
5.3
5.4
Typical power capability
Table 8. Typical power
Adapter
10 W
Vin: 230 V
AC
12 W
Adapter
6 W
Vin: 85-265 V
AC
7 W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heatsinking.
Primary MOSFET
The primary switch is implemented with an avalanche rugged N-channel MOSFET with minimum breakdown voltage 800 V, V
BVDSS
, and maximum on-resistance of 20 Ω, R
DS(on)
. The sense-FET is embedded and it allows a virtually lossless current sensing. The startup-MOSFET is embedded and it allows the HV voltage startup operation.
The MOSFET gate driver controls the gate current during both turn-on and turn-off in order to minimize EMI.
High voltage startup
The embedded high voltage startup includes both the 800 V startup FET, whose gate is biased through the resistor R
G
, and the switchable HV current source, delivering the current I
HV
. The major portion of I
HV
, (I
CH
), charges the capacitor connected to VCC. A minor portion is sunk by the controller block.
At start up, as the voltage across the DRAIN pin exceeds the V
HV_START
threshold, the HV current source is turned on, charging linearly the Cs capacitor. At the very beginning of the start-up, when Cs is fully discharged, the charging current is low (I
CH1
= 1 mA typ.) in order to avoid IC damaging in case VCC is accidentally shorted to
SGND. As V
CC
exceeds 1 V, I
CH
is increased to I
CH2
(3.2 mA, typ.) in order to speed up the charging of C
S
.
DS11301 - Rev 3 page 12/36
DS11301 - Rev 3
VIPer0P
High voltage startup
As V
CC
reaches the startup threshold V
CCon
(8 V typ.) the chip starts operating, the primary MOSFET is enabled to switch, the HV current source is disabled and the device is powered by the energy stored in the C
S
capacitor.
In steady-state the IC supports two different kind of supplies: self-supply and external supply, as shown in
Figure 25. IC supply modes: self-supply and external supply .
Figure 25. IC supply modes: self-supply and external supply
Self -supply
I
CH
C
S
VCC
External supply
I
CH
V
OUT
VCC
I
CH
C
S
C
S
V
Aux
VCC
from the output from auxiliary winding
GIPD160720151024MT
In self-supply only a capacitor C
S
is connected to the VCC and the device is supplied by the energy stored in C
S
After the IC startup, due to its internal consumption, the V
CC
decays to V
Cson
(4.25 V, typ.) and the HV current
.
source is turned on delivering the current I
CH3
(7.8 mA typ.) until V
CC
is recharged to V
CCon
. The HV current source is reactivated when V
CC
decays to VCS on
again. The I
CH3
is supplied during the switching OFF time only.
In external supply the HV current source is always kept off by maintaining the V
CC
above VCS on
. This can be obtained through a transformer auxiliary winding or a connection from the output, the latter only in case of nonisolated topology. In this case the residual consumption is given by the power dissipated on R
G
, calculated as follows:
P d
=
V 2
INDC
R
G
At the nominal input voltage, 230 V
AC consumption (R
G
, the typical consumption (R
= 28 MΩ) is 3.9 mW.
G
= 34 MΩ) is 3.2 mW and the worst-case
When the IC is disconnected from the mains, or there is a mains interruption, for some time the converter will keep on working, powered by the energy stored in the input bulk capacitor. When this is discharged below a critical value, the converter is no longer able to keep the output voltage regulated. During the power down, when the DRAIN voltage becomes too low, the HV current source (I
HV
) remains off and the IC is stopped as soon as the
V
CC
drops below the UVLO threshold, V
CCoff
.
page 13/36
Figure 26. Power-ON and power-OFF
VIPer0P
Soft start up
5.5
Soft start up
The internal soft-start function of VIPer0P progressively increases the cycle-by-cycle current limitation set point from zero up to I
DLIM
in 8 steps of 50 mA each. The soft-start time, t
SS
, is internally set at 8 ms. This function is activated at any attempt of converter start-up and at any restart after a fault event. The feature protects the system at the startup when the output load presents itself like a short-circuit and the converter would work at its maximum drain current limitation.
Figure 27. Soft startup
DS11301 - Rev 3 page 14/36
5.6
5.7
VIPer0P
Oscillator
Oscillator
The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by approximately ±7% kHz F
OSC
at 260 Hz rate. The purpose of the jittering is to get a spread-spectrum action that distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having the same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially when measured with the average detection method or, which is the same, to pass the EMI tests with an input filter of smaller size with respect to the one that should be needed in absence of jittering feature. Two options with different switching frequencies, F
OSC
, are available: 60 kHz (L type) and 120 kHz (H type).
•
•
Pulse skipping
The IC embeds a pulse skip circuit that operates in the following way: each time the DRAIN peak current exceeds I
DLIM
level within t
ON_MIN
, the switching cycle is skipped. The cycles can be skipped until the minimum switching frequency is reached, F
OSC_MIN
(15 kHz, typ.).
each time the DRAIN peak current does not exceed I
DLIM
within t
ON_MIN
, a switching cycle is restored. The cycles can be restored until the nominal switching frequency is reached, F
OSC
(60 or 120 kHz, typ.)
If the converter is indefinitely operated at F
OSC_MIN
, the IC is turned off after the time t
OVL_MAX
(200 ms or 400 ms typ., depending on F
OSC
) and then automatically restarted with soft start phase, after the time t
RESTART
(1 sec, typ.).
The protection is intended in order to avoid the so called "flux runaway" condition often present at converter startup or in case of a dead-short at converter output and due to the fact that the primary MOSFET, which is turned on by the internal oscillator, cannot be turned off before the minimum on-time.
During the on-time, the inductor is charged through the input voltage and if it cannot be discharged by the same amount during the off-time, in every switching cycle there is a net increase of the average inductor current, that can reach dangerously high values until the output capacitor is not charged enough to ensure the inductor discharge rate needed for the volt-second balance. This condition is common at converter startup, because of the low output voltage.
In the following
Figure 28. Pulse skipping during start-up for F
the effect of pulse skipping feature on the DRAIN peak current shape is shown (solid line), compared with the DRAIN peak current shape when pulse skipping feature is not implemented (dashed line). Providing more time for cycle-by-cycle inductor discharge when needed, this feature is effective in keeping low the maximum DRAIN peak current avoiding the flux runaway condition.
DS11301 - Rev 3 page 15/36
Figure 28. Pulse skipping during start-up for F
OSC
= 60 kHz
VIPer0P
Direct feedback
5.8
5.9
5.10
Direct feedback
The IC embeds a transconductance type error amplifier (E/A) whose inverting input, ground reference and output are FB, EAGND and COMP, respectively. The internal reference voltage of the E/A is V
FB_REF
(1.2 V typical value referred to EAGND). In non-isolated topologies this makes it possible to tightly regulate positive output voltages through a simple voltage divider applied among the output voltage terminal, FB and EAGND, and soldering SGND to EAGND. Since EAGND can float down to -12.5 V with respect to the ground of the IC (SGND), negative output voltages can be regulated as well, connecting EAGND to the negative rail, and the voltage divider among FB,
EAGND and SGND, as shown in Figure 34. Negative output flyback converter (non-isolated) .
The E/A output is scaled down and fed into the PWM comparator, where it is compared to the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-by-cycle drain current limitation.
An R-C network connected on the output of the E/A (COMP) is usually used to stabilize the overall control loop.
The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is accidentally left floating.
Secondary feedback
When a secondary feedback is required, the internal E/A has to be disabled shorting FB to EAGND (V
FB
<
V
FB_DIS
). With this setting COMP is internally connected to a pre-regulated voltage through the pull-up resistor
R
COMP(DYN)
, (65 kΩ, typ.) and the voltage across COMP is set by the current sunk.
This allows the output voltage value to be set through an external error amplifier (TL431 or similar) placed on the secondary side, whose error signal is used to set the DRAIN peak current setpoint corresponding to the output power demand. If isolation is required, the error signal must be transferred through an optocoupler, with the phototransistor collector connected across COMP and SGND.
Pulse frequency modulation
If the output load is decreased, the feedback loop reacts lowering the V
COMP
voltage, which reduces the DRAIN peak current setpoint, down to the minimum value of I
DLIM_PFM
when the V
COMPL
threshold is reached.
If the load is further decreased, the DRAIN peak current value is maintained at I
DLIM_PFM
and some PWM cycles are skipped. This mode of operation is referred to as “pulse frequency modulation” (PFM), the number of the skipped cycles depends on the balance between the output power demand and the power transferred from the
DS11301 - Rev 3 page 16/36
VIPer0P
Zero power mode
5.11
input. The result is an equivalent switching frequency which can go down to some hundreds Hz, thus reducing all the frequency-related losses.
This kind of operation, together with the extremely low IC quiescent current, allows very low input power consumption in no load and light load, while the low DRAIN peak current value, I
DLIM_PFM
, prevents any audible noise which could arise from low switching frequency values. When the load is increased, V
COMP
increases and
PFM is exited. V
COMP
reaches its maximum at V
COMPH
and corresponding to that value, the DRAIN current limitation (I
DLIM
) is reached.
•
•
•
Zero power mode
The zero-power mode (ZPM) is a special idle state of VIPer0P, characterized by the following features: there is no switching activity, then neither voltage nor power, available at the output the HV current source charges V
CC
at 13 V and does not perform its usual functions all IC circuits, except the ones needed to exit ZPM, are turned off, reducing the controller consumption to very low values
The IC enters ZPM if OFF is forced to SGND for more than t
DEB_OFF
(10 ms, typ.), the IC exits ZPM if ON is forced to SGND for a more than t
DEB_ON
(20 μs, typ.).
The ZPM can be managed manually or by a microcontroller (MCU) or in mixed mode. In case of mixed ZPM
shuts down the SMPS by pulling low OFF through one of its GPIOs, cutting also its own supply voltage. The restart is commanded by a pushbutton or a tactile switch pressed by the user that directly operates pin ON. For safety reasons, this switch should operate at low voltage (SELV level). The MCU wakes up after the SMPS is again up and running. This arrangement provides the minimum consumption from the power line.
In case of ZPM management by MCU only (see
Figure 30. ZPM fully managed by MCU
) the MCU shuts down the
SMPS by pulling low OFF and wakes it up as well by pulling low ON. Two of its GPIOs are used. The MCU is powered also during ZPM using the resistive pull-up available at ON (R
ON
, 45 kΩ typical), provided that it is rated for 3.3 V supply voltage, and equipped with an ultra-low consumption Standby Mode.
Since in ZPM the device is supplied with extremely low current, it is naturally prone to pick up noise. If the device is required to work in a noisy environment, it is recommended to connect a film capacitor (tens to some hundreds pF) across ON and OFF versus SGND. If the device is disconnected from the mains or there is a mains interruption while in ZPM, the information in the logic is lost. When the input source is applied again, the IC will be restarted in normal mode.
The ultimate aim of ZPM function is to enable the realization of PSUs able to comply with the European regulation
1275/2008 as far as the standby and off-mode power consumption of appliances is concerned. To meet this target a careful system-level design is required.
The total input consumption is therefore reduced to the residual consumption lower than 4 mW at 230 V
AC
that can be rounded to zero based on the IEC62301 that sets to 10 mW the minimum accuracy of the standby power measurements.
DS11301 - Rev 3 page 17/36
C
B
VIPer0P
Overload protection (OLP)
Figure 29. ZPM managed in mixed mode
V
AUX
GPIO
MCU
Active low output
OFF
ON
VIPer0P
Power-ON
GIPD280420151131MT
Figure 30. ZPM fully managed by MCU
4 V
45 k W
VIPer0P
ON
OFF
C
B
Active low outputs
MCU
GPIO
GPIO
V
AUX
Power-ON/OFF
5.12
GIPD250820151513FSR
Overload protection (OLP)
In order to manage the overload condition the IC embeds the following main blocks: the OCP comparator to turn off the power MOSFET when the drain current reaches its limit (I
DLIM
), the up and down OCP counter to define the turn off delay time in case of continuous overload (t
OVL
= 50 ms typ.) and the timer to define the restart time after protection tripping (t
RESTART
= 1 sec, typ.).
In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn off of the power switch will be triggered by the OCP comparator instead of by the PWM comparator. Every cycle this condition is met, the OCP counter is incremented and if the fault condition persists for a time greater than t
OVL
(corresponding to the counter end-of-count), the protection is tripped, the PWM is disabled for t
RESTART
, then it resumes switching with soft-start and, if the fault is still present, it is disabled again after t
OVL
. The OLP management prevents that the IC could be indefinitely operated at I
DLIM
and the low repetition rate of the restart attempts of the converter avoids overheating the IC in case of repeated fault events.
After the fault removal, the IC resumes working normally. If the fault is removed before the protection tripping
(before t
OVL
), the t
OVL
-counter is decremented on a cycle-by-cycle basis down to zero and the protection is not tripped. If the fault is removed during t resuming switching.
RESTART
, the IC waits for that the t
RESTART
period has elapsed before
In fault condition the V
CC
ranges between V
CSon
and V
CCon
levels, due to the periodical activation of the HV current source recharging the V
CC
capacitor.
DS11301 - Rev 3 page 18/36
V
CC
V
CCon
V
CSon
I
DRAIN
I
DLIM
Overload occurs
Figure 31. Overload condition
Overload removed
VIPer0P
Max. duty cycle counter protection time
5.13
5.14
5.15
t
OVL t
OVL time t
RESTART t
RESTART t
SS t
SS
GIPD270420151208MT
Max. duty cycle counter protection
The IC embeds a max duty-cycle counter, which disables the PWM if the MOSFET is turned off by max duty cycle
(70% min, 80% max) for ten consecutive switching cycles. After protection tripping, the PWM is stopped for t
RESTART
and then activated again with soft-start phase until the fault condition is removed.
In some cases (i.e. breaking of the loop) even if V
COMP
is saturated high, the OLP cannot be triggered because at every switching cycle the PWM is turned off by maximum duty cycle before the DRAIN peak current can reach the
I
DLIM
setpoint. As a result, the output voltage V
OUT
could increases out of control and be maintained indefinitely at much higher value than nominal one with risk for the output capacitor, the output diode and the IC itself. The max duty cycle counter protection prevents this kind of failures.
V
CC
clamp protection
This protection can be invoked when the IC is supplied by auxiliary winding or diode from the output voltage, when an output over-voltage produces an increase of V
CC
.
If V
CC
reaches the clamp level V
CCclamp
(30 V, min. referred to EAGND) the current injected into the pin is monitored and if it exceeds the internal threshold I clamp_max
PWM is disabled for t
RESTART
(30 mA, typ.) for more than t clamp_max
(5 ms, typ.), the
(1 sec, typ.) and then activated again with soft-start phase. The protection is disabled during the soft-start time.
Thermal shutdown
If the junction temperature becomes higher than the internal threshold T
SD
(160 °C, typ.), the PWM is disabled.
After t
RESTART
time, a single switching cycle is performed, during which the temperature sensor embedded in the
Power MOSFET section is checked. If a junction temperature above T
SD
is still measured, the PWM is maintained disabled for t
RESTART
time, otherwise it resumes switching with soft-start phase.
During t
RESTART
V
CC
is maintained between V
CSon
and V
CCon
levels by the HV current source periodical activation. Such a behavior is summarized in
Figure 32. Thermal shutdown timing diagram .
DS11301 - Rev 3 page 19/36
VIPer0P
Thermal shutdown
V
CC
V
CCon
V
CSon
I
DRAIN
I
DLIM
I
PEAK
T
J
> T
SD
Figure 32. Thermal shutdown timing diagram
T
J
< T
SD t
RESTART t
RESTART time t
SS time
GIPD270420151404MT
DS11301 - Rev 3 page 20/36
VIPer0P
Application information
6
Application information
6.1
Typical schematics
Cs
~ AC
Figure 33. Flyback converter (non-isolated) optional if Vout >= 5V
Da ux
Din Rin
T
Dout
Cin
Ccl
Rcl
Cout
Vout
GND
VIPER0P
VCC DRAIN
ON
CONTROL
OFF
COMP FB EAGND SGND PGND
C1
R1
R2
~ AC
Cs
GIPD030920151438MT1609
Figure 34. Negative output flyback converter (non-isolated)
T
Din Rin
GND
Cin Ccl
Rcl
Dout
Cout ne ga tive ra il
Vout (< 0V)
Daux
VIPER0P
VCC DRAIN
ON
CONTROL
OFF
COMP FB EAGND SGND PGND optiona l
R1
C1
R2
GIPD030620151439MT
DS11301 - Rev 3 page 21/36
DS11301 - Rev 3
VIPer0P
Typical schematics
~ AC
Figure 35. Isolated flyback converter with secondary feedback
T
Din Rin
Cin Ccl
Dout
Cout
Rcl
Vout
GND
Da ux
Cs
OPTO optional
VIPER0P
VCC DRAIN
ON
CONTROL
OFF
COMP FB EAGND SGND PGND
C1
OPTO R1
R2
~ AC
Cs
R1
GIPD150920151017MT
Figure 36. Primary side regulation isolated flyback converter
T
Din Rin
Dout
Vout
Cin Ccl
Rcl
Cout
GND
Daux
VIPER0P
VCC DRAIN
ON
CONTROL
OFF
COMP FB EAGND SGND PGND
R2 C1
GIPD030920151441MT page 22/36
VIPer0P
Example of ZPM management using MCU
~ AC
Din Rin
Cin
Figure 37. Buck converter (positive output)
VIPER0P
VCC DRAIN
ON
CONTROL
OFF
COMP FB EAGND SGND PGND
C1 optiona l if Vout >= 5V
Daux
Cs
R1
C2
D
R2
Lout
Dout
Cout
Vout
6.2
~ AC
Din Rin
Cin
Figure 38. Buck-boost converter (negative output)
GIPD030920151442MT
VIPER0P
VCC DRAIN
ON
CONTROL
OFF
COMP FB EAGND SGND PGND
C1 optional if IVoutI >= 5V
Daux
R1
Cs
C2
R2 D
Dout
Lout
Vout (< 0V)
Cout
GIPD030920151443MT
Example of ZPM management using MCU
Sometimes the SMPS provides a -5 V bus for instance to enable triac driving to control the motor of a washing machine. In this case, not to generate an additional +5 V bus, the ground of the MCU can be connected to the -5
V bus and its positive supply voltage to the ground of SMPS and VIPer0P. This connection requires an interface
a linear regulator is needed in between, in order to avoid that during normal operation the AMR of the MCU is exceeded.
DS11301 - Rev 3 page 23/36
6.3
VIPer0P
Energy saving performances
Figure 39. Example of interfacing the VIPer0P to a MCU supplied from a negative rail
EAGND
ON
VIPer0P
GND
OFF
220 pF 220 pF
0 V
56 k W
56 k W
LDO
VCC
GPIO
MCU
GPIO
GND
-5 V
GIPD250820151541FSR
Energy saving performances
VIPer0P allows designing applications compliant with the most stringent energy saving regulations. In order to show the typical performances achievable, the active mode average efficiency and the efficiency at 10% of the rated output power of a single output flyback converter using VIPer0P have been measured and are reported in
in ZPM and no load and Figure 41. P
.
V
IN
115 V
AC
230 V
AC
Table 9. Power supply efficiency, V
OUT
= 12 V
10% output load efficiency [%]
78.0
71.1
Active mode average efficiency [%]
80.9
81.0
V
IN
115 V
AC
230 V
AC
Table 10. Input power consumption
P
IN
in ZPM [mW]
0.8
3.3
P
IN
@ no-load [mW]
6.5
9.0
DS11301 - Rev 3 page 24/36
6.4
VIPer0P
Layout guidelines and design recommendations
14
12
10
8
6
4
2
0
Figure 40. P
IN
versus V
IN
in ZPM and no load
P
IN
[ mW] no load
ZPM
90 115 150
V
IN
[V
AC
]
180 230 265
GIPD160720151022MT
Figure 41. P
IN
versus V
IN
in light load
400
350
P
IN
[ mW]
150
100
50
0
300
250
200
90
P
OUT
= 250 mW
P
OUT
= 50 mW
115 150
V
IN
[V
AC
]
180
P
OUT
= 25 mW
230 265
GIPD160720151023MT
Layout guidelines and design recommendations
•
•
A proper printed circuit board layout is essential for correct operation of any switch-mode converter and this is true for the VIPer0P as well. The main reasons to have a proper PCB layout are:
Provide clean signals to the IC, ensuring good immunity against external noises and switching noises
Reduce the electromagnetic interferences, both radiated and conducted, to pass more easily the EMC
When designing a SMPS using VIPer0P, the following basic rules should be considered:
• Separating signal from power tracks: generally, traces carrying signal currents should run far from others carrying pulsed currents or with quickly swinging voltages. Signal ground traces should be connected to the
IC signal ground, SGND, using a single "star point", placed close to the IC. Power ground traces should be connected to the IC power ground, PGND. SGND and PGND are then to be connected to each other with the shortest track as possible. The compensation network should be connected to the COMP, maintaining the trace to SGND as short as possible. In case of two layer PCB, it is a good practice to route signal traces on one PCB side and power traces on the other side.
•
•
Filtering sensitive pins: some crucial points of the circuit need or may need filtering. A small highfrequency bypass capacitor to SGND might be useful to get a clean bias voltage for the signal part of the IC and protect the IC itself during EFT/ESD tests. A low ESL ceramic capacitor (a few hundreds pF up to 0.1
μF) should be connected across VCC and SGND, placed as close as possible to the IC. With flyback topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary return and then to the main GND using a single track. In case of nosy environment, it is strongly recommended to filter ON and OFF with small ceramic capacitors (tens to hundreds pF) connected to
SGND, in order to improve the system noise immunity.
Keep power loops as confined as possible: minimize the area circumscribed by current loops where high pulsed currents flow, in order to reduce its parasitic self-inductance and the radiated electromagnetic field: this will greatly reduce the electromagnetic interferences produced by the power supply during the switching.
In a flyback converter the most critical loops are: the one including the input bulk capacitor, the power switch,
DS11301 - Rev 3 page 25/36
DS11301 - Rev 3
VIPer0P
Layout guidelines and design recommendations
•
•
• the power transformer, the one including the snubber, the one including the secondary winding, the output rectifier and the output capacitor. In a buck converter the most critical loop is the one including the input bulk capacitor, the power switch, the power inductor, the output capacitor and the free-wheeling diode.
Reduce line lengths: any wire will act as an antenna. With the very short rise times exhibited by EFT pulses, any antenna has the capability of receiving high voltage spikes. By reducing line lengths, the level of radiated energy that is received will be reduced, and the resulting spikes from electrostatic discharges will be lower. This will also keep both resistive and inductive effects to a minimum. In particular, all of traces carrying high currents, especially if pulsed (tracks of the power loops) should be as short and fat as possible.
Optimize track routing: as levels of pickup from static discharges are likely to be greater closer to the extremities of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines will often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon as possible where applicable. Since vias are to be considered inductive elements, it is recommended to minimize their number in the signal path and avoid them when designing the power path.
Improve thermal dissipation: an adequate copper area has to be provided under the DRAIN pins as heat sink, while it is not recommended to place large copper areas on the SGND and PGND.
Figure 42. Recommended routing for flyback converter
T
~ AC
Din Rin
Cin Ccl
Rcl
Daux
Cs
OPTO
VIPER0P
VCC DRAIN
ON
CONTROL
OFF
COMP FB EAGND SGND PGND
C1
Dout
OPTO
Cout
R1
R2
Vout
GND
GIPD030920151537MT page 26/36
DS11301 - Rev 3
VIPer0P
Layout guidelines and design recommendations
Figure 43. Recommended routing for buck converter
~ AC
Din Rin1
Cin
VIPER0P
VCC DRAIN
ON
OFF
COMP FB
CONTROL
EAGND SGND PGND
C1
Daux
Cs
R1
R2
C2
D
Lout
Dout
Cout
Vout
GIPD030920151538MT page 27/36
7
7.1
VIPer0P
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
SO16N package information
Figure 44. SO16N package outline
DS11301 - Rev 3 page 28/36
Dim.
e h
L
E
E1 k ccc
A
A1
A2 b c
D
Table 11. SO16N mechanical data
Min.
mm
Typ.
0.1
1.25
0.31
0.17
9.8
5.8
3.8
0.25
0.4
0
9.9
6
3.9
1.27
VIPer0P
SO16N package information
Max.
1.75
0.25
0.51
0.25
10
6.2
4
0.5
1.27
8
0.1
DS11301 - Rev 3 page 29/36
VIPer0P
Ordering information
8
Ordering information
Order code
VIPER0PLD
VIPER0PHD
VIPER0PLDTR
VIPER0PHDTR
Table 12. Order codes
Package Packing
Tube
SO16N
Tape and reel
F
OSC
± jitter
60 kHz ±7%
120 kHz ±7%
60 kHz ±7%
120 kHz ±7%
DS11301 - Rev 3 page 30/36
VIPer0P
Revision history
Table 13. Document revision history
Date
18-Aug-2015
Revision
1 Initial release
12-Apr-2016
01-Oct-2018
2
3
Changes
Updated Table 4: "Avalanche characteristics", Table 6: "Supply section" and Table 7: "Controller section".Minor text changes.
Updated V
OFF
and V
ON
values in
DS11301 - Rev 3 page 31/36
VIPer0P
Contents
Contents
DS11301 - Rev 3 page 32/36
VIPer0P
Contents
DS11301 - Rev 3 page 33/36
VIPer0P
List of tables
List of tables
Table 9. Power supply efficiency, V
DS11301 - Rev 3 page 34/36
VIPer0P
List of figures
List of figures
Figure 8. Quiescent current I q
Figure 22. Max avalache energy vs T
Figure 28. Pulse skipping during start-up for F
= 60 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DS11301 - Rev 3 page 35/36
VIPer0P
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS11301 - Rev 3 page 36/36
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