STMicroelectronics VIPER11 Datasheet
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VIPer11
SSOP10
Features
800 V avalanche-rugged power MOSFET allowing ultra wide VAC input range to be covered
Embedded HV startup and sense-FET
Current mode PWM controller
Drain current limit protection
– 370 mA (VIPER113)
– 480 mA (VIPER114)
– 590 mA (VIPER115)
Wide supply voltage range: 4.5 V to 30 V
Minimized system input power consumption:
– Less than 10 mW at 230 V
AC condition
in no-load
– Less than 400 mW at 230 V
AC mW load
with 250
Jittered switching frequency reduces the EMI filter cost:
– 30 kHz ± 7% (type X)
– 60 kHz ± 7% (type L)
– 120kHz ± 7%(type H)
Embedded E/A with 1.2 V reference
Protections with automatic restart: overload/short-circuit (OLP), line or output
OVP, max. duty cycle counter, VCC clamp
Pulse-skip protection to prevent flux- runaway
Embedded thermal shutdown
Built-in soft-start for improved system reliability
Energy saving offline high voltage converter
Datasheet
-
production data
Applications
Low power SMPS for home appliances, home automation, industrial, consumer, lighting
Low power adapters
Description
The device is a high voltage converter smartly integrating an 800 V avalanche-rugged power
MOSFET with PWM current mode control. The power MOSFET with 800 V breakdown voltage allows the extended input voltage range to be applied, as well as the size of the DRAIN snubber circuit to be reduced. This IC meets the most stringent energy-saving standards as it has very low consumption and operates in pulse frequency modulation under light load. The design of flyback, buck and buck boost converters is supported. The integrated HV startup, sense-
FET, error amplifier and oscillator with jitter allow a complete application to be designed with the minimum number of components.
Figure 1. Basic application schematic
".
April 2020
This is information on a product in full production.
DS11873 Rev 5 1/37 www.st.com
Contents
Contents
2/37
VIPer11
Electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pulse frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Max. duty cycle counter protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Energy saving performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout guidelines and design recommendations . . . . . . . . . . . . . . . . . . . 32
SSOP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DS11873 Rev 5
VIPer11
Contents
DS11873 Rev 5 3/37
37
Pin setting
1 Pin setting
Figure 2. Connection diagram
VIPer11
4/37
SSOP10 Name
1
2
3
4
GND
VCC
DIS
FB
Table 1. Pin description
Function
Ground and MOSFET source.
Connection of source of the internal MOSFET and the return of the bias current of the device. All groundings of bias components must be tied to a trace going to this pin and kept separate from the pulsed current return.
Controller supply.
An external storage capacitor has to be connected across this pin and GND. The pin, internally connected to the high voltage current source, provides the VCC capacitor charging current at startup. A small bypass capacitor (0.1 F typ.) in parallel, placed as close as possible to the IC, is also recommended, for noise filtering purpose.
Disable.
If its voltage exceeds the internal threshold V
DIS_th more than t
DEB
time (1 ms, typ.), the PWM is disabled for t
(1.2 V typ.) for
DIS_RESTART
(500msec, typ.) in auto-restart mode, resuming normal operation as soon as
V
DIS
falls below V
DIS_th
. An input overvoltage protection can be built by connecting a voltage divider between the DIS pin and the rectified mains. In case of non-isolated topologies, with the same principle an output overvoltage protection can be implemented. If the disable function is not required, the DIS pin must be soldered to GND, which excludes the function.
Direct feedback.
It is the inverting input of the internal transconductance E/A, which is internally referenced to 1.2 V with respect to GND. In case of non- isolated converter, the output voltage information is directly fed into the pin through a voltage divider. In case of primary regulation, the FB voltage divider is connected to the VCC. The E/A is disabled soldering FB to GND.
DS11873 Rev 5
VIPer11 Pin setting
SSOP10 Name
Table 1. Pin description (continued)
Function
5 COMP
6 to 10 DRAIN
Compensation. It is the output of the internal E/A. A compensation network is placed between this pin and GND to achieve stability and good dynamic performance of the control loop. In case of secondary feedback, the internal E/A must be disabled and the COMP directly driven by the optocoupler to control the
DRAIN peak current setpoint.
MOSFET drain.
The internal high voltage current source sinks current from this pin to charge the VCC capacitor at startup and during steady-state operation.
These pins are mechanically connected to the internal metal PAD of the
MOSFET in order to facilitate heat dissipation. On the PCB a copper area must be placed under these pins in order to decrease the total junction-to-ambient thermal resistance thus facilitating the power dissipation.
DS11873 Rev 5 5/37
37
Electrical and thermal ratings
2 Electrical and thermal ratings
VIPer11
Symbol Pin
Table 2. Absolute maximum ratings
Parameter
(1)
,
(2)
Min.
Max.
Unit
V
DS
I
DRAIN
6 to 10 Drain-to-source (ground) voltage
6 to 10 Pulsed drain current (pulse-width limited by SOA) -
800
2
V
CC
I
CC
V
DIS
V
FB
V
COMP
P
TOT
T
J
T
STG
2
2
3
4
5
-
-
-
VCC voltage
VCC internal Zener current (pulsed)
DIS voltage
FB voltage
COMP voltage
Power dissipation at T
Junction temperature operating range
Storage temperature amb
< 50 °C
-0.3
-
-0.3
-0.3
-0.3
-
-40
-55
Internally limited
45
5
5
5(
1
(3)
(4)
(4)
(4)
(5)
150
150
1. Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability.
3. Pulse-width limited by maximum power dissipation, P
TOT
.
4. The AMR value is intended when V
CC
5 V, otherwise the value V
CC
+ 0.3 V has to be considered.
5. When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 μm thick).
V
A
V mA
V
V
V
W
°C
°C
Symbol
R
TH-JC
R
TH-JA
R
TH-JC
R
TH-JA
Table 3. Thermal data
Parameter
Thermal resistance junction to case
(1)
(Dissipated power = 1 W)
Thermal resistance junction ambient
(Dissipated power = 1 W)
Thermal resistance junction to case
(2)
(Dissipated power = 1 W)
Thermal resistance junction ambient
(2)
(Dissipated power = 1 W)
Max. value Unit
10
155
5
95
1. When mounted on a standard single side FR4 board with minimum copper area.
2. When mounted on a standard single side FR4 board with 100 mm
2
(0.155 sq in) of Cu (35 μm thick).
°C/W
°C/W
°C/W
°C/W
6/37 DS11873 Rev 5
VIPer11 Electrical and thermal ratings
Figure 3. R thJA
/ (R thJA at A = 100 mm²)
Symbol
I
AR
E
AS
Parameter
Table 4. Avalanche characteristics
Test conditions
Avalanche current
Single pulse avalanche energy
(1)
Repetitive and non-repetitive.
Pulse-width limited by T
Jmax
I
AS
= I
AR VDS
= 100 V
Starting T
J
= 25 °C
1. Parameter derived by characterization.
Min. Typ. Max. Unit
0.8
A
1 mJ
DS11873 Rev 5 7/37
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Electrical characteristics
3 Electrical characteristics
VIPer11
T j
= -40 to 125 °C, V
CC
= 9 V (unless otherwise specified).
Symbol
V
BVDSS
Breakdown voltage
I
DSS
I
OFF
Parameter
Drain-source leakage current
OFF-state drain current
Table 5. Power section
Test conditions
R
DS(on)
Static drain-source ON-resistance
I
DRAIN
= 1 mA
V
COMP
= GND
T
J
= 25 °C
V
DS
= 400 V
V
COMP
T
J
= GND
= 25 °C
V
DRAIN
V
COMP
= max. rating
= GND
T
J
= 25 °C
I
DRAIN
= 295 mA
T
J
= 25 °C
I
DRAIN
= 295 mA
T
J
= 125 °C
Min.
Typ.
Max.
Unit
800
-
-
-
-
-
-
-
-
-
1
45
17
34
V
μA
Symbol Parameter
Table 6. Supply section
Test conditions
High voltage start-up current source
V
BVDSS_SU
Breakdown voltage of start-up
MOSFET
V
HV_START
I
I
I
R
G
CH1
CH2
CH3
(1)
T
J
= 25 °C
Drain-source start-up voltage -
Start-up resistor
VCC charging current at startup
VCC charging current at startup
Max. VCC charging current in self-supply
V
FB
> V
FB_REF
V
DRAIN
= 400 V
V
DRAIN
= 600 V
V
DRAIN
= 100 V
V
CC
= 0 V
V
FB
> VF
FB_REF
V
DRAIN
= 100 V
V
CC
= 6 V
V
FB
> V
FB_REF
V
DRAIN
= 100 V
V
CC
= 6 V
IC supply and consumptions
V
CC
V
CCclamp
Operating voltage range
Clamp voltage
VGND = 0 V
I
CC
= I clamp_max
Min.
Typ.
Max. Unit
800
-
28
0.7
2
-
-
34
1
3
-
26
V
V
40 M
1.3
4 mA
6.5
7.5
8.5
4.5
-
30 32.5
30
35
V
V
8/37 DS11873 Rev 5
VIPer11 Electrical characteristics
Symbol
Table 6. Supply section (continued)
Parameter Test conditions
I clamp max t clamp max
Clamp shutdown current
Clamp time before shutdown -
(2)
V
CCon
VCC start-up threshold
V
FB
= 1.2 V
V
DRAIN
= 400 V
V
CSon
HV current source turn-on threshold
V
CC
falling
V
I
CCoff
I q
CC
UVLO
Quiescent current
Operating supply current, switching
V
FB
= 1.2 V
V
DRAIN
= 400 V
Not switching
V
FB
> V
FB_REF
V
DS
= 150 V
V
COMP
= 1.2 V
F
OSC
= 30 kHz
V
DS
= 150 V
V
COMP
F
OSC
= 1.2 V
= 60 kHz
V
DS
= 150 V
V
COMP
= 1.2 V
F
OSC
= 120 kHz
1. Current supplied during the main MOSFET OFF time only.
2. Parameter assured by design and characterization.
Min.
Typ.
Max. Unit
30 35 40 mA
325 500 675 μs
15
4
3.75
-
-
-
-
16
4.25
4.5
4
0.3
0.45
mA
1
1.25
1.5
1.5
17
4.25
V
1.2
1.8
V
V mA
Symbol
E/A
V
FB_REF
V
FB_DIS
I
FB PULL UP
G
M
I
COMP1
I
COMP2
Parameter
Reference voltage
E/A disable voltage
Pull-up current
Transconductance
Max. sink current
Table 7. Controller section
Test conditions
Max. source current
R
COMP(DYN)
Dynamic resistance
-
-
-
V
COMP
= 1.5 V
V
FB
> V
FB_REF
V
COMP
= 1.5 V
V
FB
= 0.5 V
V
FB
= 2 V
V
COMP
= 1.5 V
V
COMP
= 2.7 V
V
FB
= GND
Min.
1.175
150
0.9
350
75
75
55
Typ.
Max.
Unit
1.2
180
1
500
100
100
65
1.225
210
1.1
650
V mV
μA
μA/V
125
125
75
μA
μA k
DS11873 Rev 5 9/37
37
Electrical characteristics VIPer11
Symbol
Table 7. Controller section (continued)
Parameter Test conditions Min.
H
COMP
ΔV
COMP
/ ΔI
DRAIN
VIPer11 3 *
VIPer11 4 *
VIPer11 5 *
5.9
4.3
3.8
V
COMPH
Current limitation threshold
V
COMPL
PFM threshold
OLP and timing t
I t
V
I
I
2 f
DLIM_PFM t t
DLIM
DIS_th
DIS_RESTART
OVL_MAX t
DIS
OVL
SS
-
-
-
-
Drain current limitation
Power coefficient
Drain current limitation at light load
Disable threshold voltage
T
J
= 25 °C
VIPER11 3 *
T
J
= 25 °C
VIPER11 4 *
350
456
T
J
= 25 °C
VIPER11 5 *
I
DLIM_TYP
2
x F
OSC_TYPP
T
V
J
= 25 °C
COMP
= V
VIPER11 3 *
COMPL
(1)
560
0.9 ·I
2 f
75
T
V
J
= 25 °C
COMP
= V
VIPER11 4 *
COMPL
(1) 90
T
V
J
= 25 °C
COMP
= V
VIPER11 5 *
COMPL
(1)
V
CC
= 9 V
V
COMP
= 1 V
V
FB
= V
FB_REF
105
1.15
Debounce time before
DIS protection tripping
Restart time after DIS protection tripping
Overload delay time
-
0.65
325
45
Max. overload delay time
Soft-start time
-
VIPER11*X
F
OSC
= F
OSC MIN
VIPER11*L
F
OSC
= F
OSC MIN
-
VIPER11*H
F
OSC
= F
OSC MIN
90
180
360
5
Typ.
Max.
Unit
10.5
8
7
V/A
3
0.8
370
480
590
I
2 f
100
115
130
1.2
1
500
50
100
200
400
8
-
-
389
504
V
V
620
1.1 ·I
2 f A
2
·kHz
135
140
155
1.25
1.35
675
55
110
220
440
11 mA mA
V ms ms ms ms ms
10/37 DS11873 Rev 5
VIPer11 Electrical characteristics
Symbol t
ON_MIN
Table 7. Controller section (continued)
Parameter Test conditions Min.
Minimum turn-on time
Restart time after fault -
V
CC
= 9 V
V
COMP
= 1 V
V
FB
= V
FB_REF
250
0.65
t
RESTART
Oscillator
F
OSC
Switching frequency
T
J
= 25 °C
VIPER11*X
T
J
= 25 °C
VIPER11*L
T
J
= 25 °C
VIPER11*H
T
J
= 25 °C
(2)
F
OSC_MIN
Minimum switching frequency
F
D
Modulation depth
(3)
F
M
Modulation frequency
D
MAX
Max. duty cycle
Thermal shutdown
T
SD
Thermal shutdown temperature
1. See
Section 5.10: Pulse frequency modulation on page 21 .
2. See
Section 5.7: Pulse-skipping on page 20 .
3. Parameter assured by design and characterization.
27
54
108
13.5
-
-
70
150
Typ.
Max.
Unit
300
1
30
60
120
15
±7
FOSC
260
160
350
1.35
33
66
132
16.5
-
-
80 ns s kHz kHz
°C
%
Hz
%
DS11873 Rev 5 11/37
37
Typical electrical characteristics
4 Typical electrical characteristics
Figure 4. I
DLIM
vs T
J
Figure 5. I
FOSC
vs T
J
VIPer11
Figure 6. V
HV_START
vs T
J
Figure 7. V
FB_REF
vs T
J
Figure 8. Quiescent current Iq vs T
J
Figure 9. Operating current I
CC
vs T
J
12/37 DS11873 Rev 5
VIPer11
Figure 10. I
CH1
vs T
J
Typical electrical characteristics
Figure 11. I
CH1
vs V
DRAIN
Figure 12. I
CH2
vs T
J
Figure 13. I
CH2
vs V
DRAIN
Figure 14. I
CH3
vs T
J
Figure 15. I
CH3
vs V
DRAIN
DS11873 Rev 5 13/37
37
Typical electrical characteristics
Figure 16. G
M
vs T
J
Figure 17. I
COMP
vs T
J
VIPer11
Figure 18. R
DS(on)
vs T
J
Figure 19. Static drain-source on-resistance
14/37 DS11873 Rev 5
VIPer11
Figure 20. Power MOSFET capacitance variation vs VDS @ VGS=0, f=1MHz
Typical electrical characteristics
Figure 21. VBVDSS vs. TJ
Figure 22. Output characteristic Figure 23. SOA SSOP10 package
Figure 24. Maximum avalanche energy vs TJ
DS11873 Rev 5 15/37
37
General description
5 General description
5.1 Block diagram
Figure 25. Block diagram
VIPer11
',6B5(67$57
5.2 Typical power capability
Table 8. Typical power
Vin: 230 V
AC
Open frame
(2)
Adapter
Vin: 85-265 V
AC
Open frame Adapter
(1)
10 W 12 W 6 W 7 W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat-sinking.
16/37 DS11873 Rev 5
VIPer11
5.3
General description
Primary MOSFET
The primary switch is implemented with an avalanche-rugged N-channel MOSFET with minimum breakdown voltage 800 V, V
BVDSS
, and maximum on-resistance of 20 , R
The sense-FET is embedded and it allows a virtually lossless current sensing.
DS(on)
.
The MOSFET gate driver controls the gate current during both turn-on and turn-off in order to minimize EMI. Under UVLO conditions the embedded pull-down circuit holds the gate low in order to ensure that the MOSFET cannot be turned on accidentally.
5.4 High voltage startup
The embedded high voltage startup includes both the 800V-rated auxiliary N-channel power
MOSFET, whose gate is biased through the resistor R
G
, and the switchable HV current source, delivering the current I
HV
. The major portion of I
HV
, (I
CH
), charges the capacitor connected to VCC. A minor portion is sunk by the controller block.
At startup, as the voltage across the DRAIN pin exceeds the V
HV_START current source is turned on, charging linearly the C
S damaging in case V to I
CH2
CC
in order to speed up the charging of C
S
.
capacitor. At the very beginning of the startup, when Cs is fully discharged, the charging current is low, I
CH1
is accidentally shorted to GND. As V
CC
threshold, the HV
, in order to avoid IC
exceeds 1 V, I
CH
is increased
As V
CC
reaches the start-up threshold V
CCon
the chip starts operating, the primary MOSFET is enabled to switch, the HV current source is disabled and the device is powered by the energy stored in the C
S
capacitor.
In steady-state the IC can be supplied from the output (in case of non-isolated topologies) or through an auxiliary winding (in case of isolated topologies), as shown in
Figure 26. IC supply modes
DS11873 Rev 5 17/37
37
General description VIPer11
In external supply the HV current source is always kept off by maintaining the V
CC
above
V
CSon
. In this case the residual consumption is given by the power dissipated on R calculated as follows:
G
,
Equation 1
P =
V
2
I INDC
R
G
At the nominal input voltage, 230 V
AC the worst-case consumption (R
G
, the typical consumption (R
= 28 M ) is 3.9 mW.
G
= 34 M ) is 3.2 mW and
When the IC is disconnected from the mains, or there is a mains interruption, for some time the converter keeps on working, powered by the energy stored in the input bulk capacitor.
When it is discharged below a critical value, the converter is no longer able to keep the output voltage regulated. During the power down, when the DRAIN voltage becomes too low, the HV current source (I
HV below the UVLO threshold, V
) remains off and the IC is stopped as soon as the V
CC
CCoff
.
drops
Figure 27. Power-ON and power-OFF
18/37 DS11873 Rev 5
VIPer11
5.5
General description
Soft-start
The internal soft-start function of the device progressively increases the cycle-by-cycle current limitation set point from zero up to I
DLIM
in 8 steps. The soft-start time, t
SS
, is internally set at 8 ms. This function is activated at any attempt of converter startup and at any restart after a fault event. The feature protects the system at startup, when the converter would run at its maximum drain current limitation because the output capacitor is fully discharged and behaves like a short-circuit.
Figure 28. Soft startup
5.6 Oscillator
The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by approximately ± 7% kHz F
OSC
at 260 Hz rate. The purpose of the jittering is to get a spread-spectrum action that distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having the same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially when measured with the average detection method or, which is the same, to pass the EMI tests with an input filter of smaller size than that needed in absence of jittering feature.
Three options with different switching frequencies, F
OSC
60 kHz (L type) and 120 kHz (H type).
, are available: 30 (X type),
DS11873 Rev 5 19/37
37
General description
5.7 Pulse-skipping
VIPer11
The IC embeds a pulse-skip circuit that operates in the following ways:
Each time the DRAIN peak current exceeds I
DLIM
level within t
ON_MIN
, one switching cycle is skipped. The cycles can be skipped until the minimum switching frequency is reached, F
OSC_MIN
(15 kHz).
Each time the DRAIN peak current does not exceed I
DLIM
within t
ON_MIN
, one switching cycle is restored. The cycles can be restored until the nominal switching frequency is reached, F
OSC
(30, 60 or 120 kHz).
The protection is intended to avoid the so called “flux-runaway” condition often present at converter startup and due to the fact that the primary MOSFET, which is turned on by the internal oscillator, cannot be turned off before the minimum on-time.
During the on-time, the inductor is charged by the input voltage and if it cannot be discharged by the same amount during the off-time, in every switching cycle there is a net increase of the average inductor current, that can reach dangerously high values until the output capacitor is not charged enough to ensure the inductor discharge rate needed for the volt-second balance. This condition may happen at converter startup, because of the low output voltage.
In
Figure 29 the effect of pulse-skipping feature on the DRAIN peak current shape is shown
(solid line), compared with the DRAIN peak current shape when pulse-skipping feature is not implemented (dashed line).
Providing more time for cycle-by-cycle inductor discharge when needed, this feature is effective by keeping low the maximum DRAIN peak current avoiding the flux-runaway condition.
Figure 29. Pulse-skipping during startup
20/37 DS11873 Rev 5
VIPer11
5.8
General description
Direct feedback
The IC embeds a transconductance type error amplifier (E/A) whose inverting input and output are FB and COMP, respectively. The internal reference voltage of the E/A is V
FB_REF
(1.2 V typical value referred to GND). In non-isolated topologies, positive output voltages are tightly set through a simple voltage divider applied to the output voltage terminal, FB and
GND.
The E/A output is scaled down and fed into the PWM comparator, where it is compared with the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-by- cycle drain current limitation.
An R-C network connected across COMP (the output of the E/A) and GND pins is usually used to stabilize the overall control loop.
The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is accidentally left floating.
The E/A is disabled if the FB voltage is lower than V
FB_DIS
(200 mV, typ.).
5.9 Secondary feedback
When a secondary feedback is required, the internal E/A has to be disabled shorting FB to
GND (V
FB
< V
FB_DIS
). With this setting, COMP is internally connected to a pre-regulated voltage through the pull-up resistor R
COMP(DYN) current sunk.
and the voltage across COMP is set by the
This allows the output voltage value to be set through an external error amplifier (TL431 or similar) placed on the secondary side, whose error signal is used to set the DRAIN peak current setpoint corresponding to the output power demand. If isolation is required, the error signal must be transferred through an optocoupler, with the phototransistor collector connected across COMP and GND.
5.10 Pulse frequency modulation
If the output load is decreased, the feedback loop reacts lowering the V
COMP
voltage, which reduces the DRAIN peak current setpoint, down to the minimum value of I
DLIM_PFM the V
COMPL
threshold is reached.
when
If the load is furtherly decreased, the DRAIN peak current value is maintained at I
DLIM_PFM and some PWM cycles are skipped. This kind of operation is referred to as “pulse frequency modulation” (PFM), the number of the skipped cycles depends on the balance between the output power demand and the power transferred from the input. The result is an equivalent switching frequency which can go down to some hundreds Hz, thus reducing all the frequency-related losses.
This kind of operation, together with the extremely low IC quiescent current, allows very low input power consumption in no-load and light load, while the low DRAIN peak current value, I
DLIM_PFM
, prevents any audible noise which could arise from low switching frequency values. When the load is increased, V
COMP reaches its maximum at V limitation (I
DLIM
COMPH
) is reached.
increases and PFM is exited. V
and corresponding to that value, the DRAIN current
COMP
DS11873 Rev 5 21/37
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General description VIPer11
5.11 Overload protection
To manage the overload condition, the IC embeds the following main blocks: the OCP comparator to turn off the power MOSFET when the drain current reaches its limit (I
DLIM the up and down OCP counter to define the turn-off delay time in case of continuous
) , overload (t
OVL
(t
RESTART
= 50 ms typ.) and the timer to define the restart time after protection tripping
= 1 s typ.).
In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn-off of the power switch is triggered by the
OCP comparator instead of PWM comparator. Every cycle where this condition is met, the
OCP counter is incremented. If the fault condition lasts longer than t
OVL
(corresponding to the counter end-of-count), the protection is tripped, the PWM is disabled for t
RESTART
, then it resumes switching with soft-start and, if the fault is still present, it is disabled again after t
OVL
. If the converter is definitively operated at F the IC is turned off after the time t
OVL_MAX
F
OSC
OSC_MIN
, (see
Section 5.7: Pulse-skipping ),
(100 ms or 200 ms or 400 ms typ., depending on
) and then automatically restarted with soft-start phase, after t
RESTART
.
The OLP management prevents IC from operating indefinitely at I
DLIM
and the low repetition rate of the restart attempts of the converter avoids IC overheating in case of repeated fault events.
After the fault removal, the IC resumes working normally. If the fault is removed earlier than the protection tripping (before t
OVL
), the t
OVL
-counter is decremented on a cycle-by-cycle basis down to zero and the protection is not tripped. If the fault is removed during t
RESTART the IC waits for the t
RESTART
period has elapsed before resuming switching.
,
In fault condition the V
CC
ranges between V
CSon
and V activation of the HV current source recharging the V
CC
CCon
levels, due to the periodical
capacitor.
Figure 30. Short-circuit condition
22/37 DS11873 Rev 5
VIPer11 General description
5.12 Max. duty cycle counter protection
The IC embeds a max. duty cycle counter, which disables the PWM if the MOSFET is turned off by max. duty cycle (70% min., 80% max.) for ten consecutive switching cycles. After protection tripping, the PWM is stopped for t
RESTART phase until the fault condition is removed.
and then activated again with soft- start
In some cases (i.e. breaking of the loop) even if V
COMP
is saturated high, the OLP cannot be triggered because at every switching cycle the PWM is turned off by maximum duty cycle before than DRAIN peak current reaches the I
DLIM
V
OUT
setpoint. As a result, the output voltage
can increase without control by keeping a value much higher than the nominal one with the risk for the output capacitor, the output diode and the IC itself. The max. duty cycle counter protection avoids this kind of failures.
5.13 VCC clamp protection
This protection can occur when the IC is supplied by auxiliary winding or diode from the output voltage, when an output overvoltage produces an increase of V
CC
.
If VCC reaches the clamp level V
CCclamp
(30 V, min. referred to GND) the current injected into the pin is monitored and if it exceeds the internal threshold I clamp_max more than t clamp_max
(500 μs, typ.), the PWM is disabled for t
RESTART
(30 mA, typ.) for
(1 s, typ.) and then activated again in soft-start phase. The protection is disabled during the soft-start time.
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General description VIPer11
5.14 Disable function
When the voltage across the DIS pin exceeds the internal threshold V
DIS_th time filter t
DIS
(1 msec, typ.) is activated.
(1.2 V typ.), a
If, at the end of t
DIS
, the condition is no more met, the occurrence of a temporary disturbance is assumed and the IC continues to work normally; otherwise, a fault condition is recognized and the IC is disabled in auto-restart for t
DIS_RESTART
(500 msec, typ.).
When V
DIS
falls below V normal operation.
DIS_th
, the IC completes the current t
DIS_RESTART
, then resumes
During the fault, the VCC voltage is maintained between V
CCSON current source periodical activation.
and V
CCoN
through the HV
A simple input overvoltage protection can be realized by connecting a voltage divider between the DIS pin and the rectified mains, as shown in
Figure 31. Connection for input overvoltage protection (isolated or non-isolated topologies)
24/37
In case of non-isolated topologies, with the same principle an output overvoltage protection can be implemented, as shown in
.
If the Disable function is not required, DIS pin must be soldered to GND, which excludes the function.
DS11873 Rev 5
VIPer11 General description
Figure 32. Connection for output overvoltage protection (non-isolated topologies)
If V
OVP
is the desired input/output overvoltage threshold, the resistors R
H
and R
L
of the voltage divider are to be selected according to the following formula:
Equation 2
The power dissipation associated to the DIS network is:
Equation 3 in case of connection for the input overvoltage detection and
Equation 4 in case of connection for the output overvoltage detection.
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General description VIPer11
5.15 Thermal shutdown
If the junction temperature becomes higher than the internal threshold T
SD the PWM is disabled. After t
RESTART
(160 °C, typ.),
time, a single switching cycle is performed, during which the temperature sensor embedded in the power MOSFET section is checked. If a t junction temperature above T
SD
RESTART
is still measured, the PWM is maintained disabled for
time, otherwise it resumes switching with soft-start phase.
During t
RESTART
V
CC
is maintained between V
CSon
and V
CCon
levels by the HV current source periodical activation. Such a behavior is summarized in below figure:
Figure 33. Thermal shutdown timing diagram
26/37 DS11873 Rev 5
VIPer11 General description
5.16 Auto-restart
When a fault occurs, the PWM is disabled in auto-restart until the fault is removed.
This means that:
1.
PWM stops switching for a restart time, namely:
t
RESTART
(1 sec, typ.), in case the fault is one of the following: overload/short-circuit, max. duty cycle counter, V
CC
clamp, overtemperature.
t
DIS_RESTART overvoltage).
(0.5 sec, typ.), in case the fault is triggered at the DIS pin (input/output
2. At the end of restart time:
– if the fault is still present, the protection is tripped in the same way after a debounce
time (see Figure 34 ), namely:
t
SS
+ t
OVL
(8 + 50msec, typ.) in case the fault is overload/short-circuit;
t clamp_max
(0.5 msec, typ.) in case the fault is V
CC
clamp;
t
DIS
(1 msec, typ) in case the fault is triggered at the DIS pin (input/output overvoltage);
10 switching cycles in case the fault is max. duty cycle counter;
1 switching cycle in case the fault is overtemperature;
– if the fault is no longer present, normal operation is restored, as shown in
3. During restart time, the HV generator is activated periodically, maintaining the VCC pin voltage between V
CSon
and V
CCon
.
Figure 34. Protection timing diagram with auto-restart option
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Application information
6 Application information
6.1 Typical schematics
Figure 35. Flyback converter (non-isolated)
VIPer11
Figure 36. Flyback converter with line OVP (non-isolated)
28/37 DS11873 Rev 5
VIPer11
Figure 37. Flyback converter (isolated)
Application information
Figure 38. Primary side regulation isolated flyback converter
DS11873 Rev 5 29/37
37
Application information
Figure 39. Buck converter (positive output)
VIPer11
Figure 40. Buck-boost converter (negative output)
30/37 DS11873 Rev 5
VIPer11 Application information
6.2 Energy saving performance
The device allows designing applications to be compliant with the most stringent energy saving regulations. In order to show the typical performance is achievable, the active mode average efficiency and the efficiency at 10% of the rated output power of a 5 V/1.6 A nonisolated flyback and 5 V/360 mA buck converters adopting VIPer11, have been measured and are reported in
Table 9 . In addition, no-load and light load consumptions are shown
from
Parameter
Table 9. Power supply efficiency, V
OUT
= 5 V
VIN
10 % output load efficiency [%]
Active mode average efficiency [%]
Pin at no-load [mW]
Flyback non iso. 5 V/1.6 A
Buck 5 V/360 mA
(1)
115 V
AC
230 V
AC
115 V
AC
230 V
AC
1. 5 mW bleeder connected at the output.
78.3
71.4
73.9
69.1
78.5
79.4
71.6
69.8
3.9
8.2
12.1
16.2
Figure 41. P
IN
versus V
IN
in no-load non isolated flyback converter (5 V/1.6 A)
Figure 42. P
IN
versus V
IN
in light load non isolated flyback converter (5 V/1.6 A)
Figure 43. P
IN
versus V
IN
in no-load non isolated buck converter (5 V/360 mA)
Figure 44. P
IN
versus V
IN
in light load non isolated buck converter (5 V/360 mA)
DS11873 Rev 5 31/37
37
Application information
6.3 Layout guidelines and design recommendations
VIPer11
A proper printed circuit board layout ensures the correct operation of any switch-mode converter and this is true for the VIPer as well. The main reasons to have a proper PCB layout are:
Providing clean signals to the IC, ensuring good immunity against external and switching noises.
Reducing the electromagnetic interferences, both radiated and conducted, to pass the
EMC tests more easily.
If the VIPer is used to design a SMPS, the following basic rules should be considered:
Separating signal from power tracks.
Generally, traces carrying signal currents should run far from others carrying pulsed currents or with fast swinging voltages.
Signal ground traces should be connected to the IC signal ground, GND, using a single
“star point”, placed close to the IC. Power ground traces should be connected to the IC power ground, GND. The compensation network should be connected to the COMP, maintaining the trace to GND as short as possible. In case of two-layer PCB, it is a good practice to route signal traces on one PCB side and power traces on the other side.
Filtering sensitive pins. Some crucial points of the circuit need or may need filtering.
A small high-frequency bypass capacitor to GND might be useful to get a clean bias voltage for the signal part of the IC and protect the IC itself during EFT/ESD tests. A low
ESL ceramic capacitor (a few hundreds pF up to 0.1 F) should be connected across
VCC and GND, placed as close as possible to the IC. With flyback topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary return and then to the main GND using a single track.
Keeping power loops as confined as possible.
The area circumscribed by current loops where high pulsed current flow should be minimized to reduce its parasitic self- inductance and the radiated electromagnetic field. As a consequence, the electromagnetic interferences produced by the power supply during the switching are highly reduced. In a flyback converter the most critical loops are: the one including the input bulk capacitor, the power switch, the power transformer, the one including the snubber, the one including the secondary winding, the output rectifier and the output capacitor. In a buck converter the most critical loop is the one including the input bulk capacitor, the power switch, the power inductor, the output capacitor and the free- wheeling diode.
Reducing line lengths. Any wire acts as an antenna. With the very short rise times exhibited by EFT pulses, any antenna can receive high voltage spikes. By reducing line lengths, the level of received radiated energy is reduced, and the resulting spikes from electrostatic discharges are lower. This also keeps both resistive and inductive effects to a minimum. In particular, all traces carrying high currents, especially if pulsed (tracks of the power loops) should be as short and wide as possible.
Optimizing track routing.
As levels of pickup from static discharges are likely greater near the edges of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon as possible where applicable. Since vias are to be considered inductive elements, it is recommended to minimize their number in the signal path and avoid them in the power path.
Improving thermal dissipation.
An adequate copper area has to be provided under the DRAIN pins as heatsink, while it is not recommended to place large copper areas on the GND.
32/37 DS11873 Rev 5
VIPer11 Application information
Figure 45. Recommended routing for flyback converter
Figure 46. Recommended routing for buck converter
DS11873 Rev 5 33/37
37
Package information
7 Package information
VIPer11
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
7.1 SSOP10 package information
Figure 47. SSOP10 package outline
34/37 DS11873 Rev 5
VIPer11
Symbol
D
E b c
A
A1
A2
E1 e h
L
K
Table 10. SSOP10 package mechanical data
Dimensions (mm)
Min.
-
0.10
1.25
0.31
0.17
4.80
5.80
3.80
-
0.25
0.40
0°
Typ.
-
-
4.90
6
-
-
-
3.90
1
-
-
-
Figure 48. SSOP10 recommended footprint
Package information
Max.
1.75
0.25
-
0.51
0.25
5
6.20
4
-
0.50
0.90
8°
DS11873 Rev 5 35/37
37
Ordering information
8 Ordering information
Order code
VIPER11 3 XSTR
VIPER11 4 XSTR
VIPER11 5 XSTR
VIPER11 3 LSTR
VIPER11 4 LSTR
VIPER11 5 LSTR
VIPER11 4 HSTR
VIPER11 5 HSTR
VIPer11
Table 11. Order code
I
DLIM
(OCP) F
OSC
± jitter
3 70 mA
4 80 mA
5 90 mA
3 70 mA
4 80 mA
5 90 mA
4 80 mA
5 90 mA
30 kHz ± 7%
60 kHz ± 7%
120 kHz ± 7%
Package
SSOP10 tape and reel
9 Revision history
Date
11-Apr-2018
19-Apr-2018
14-Dec-2018
02-Sept-2019
07-Apr-2020
Table 12. Document revision history
Revision Changes
1
2
3
4
5
Initial release.
Document status changed from preliminary to production data.
Amended the Features on page 1, Updated Tables
. Amended Table 1 , amended Figures
34 . Minor changes in sections
;
. Amended sections
;
.
36/37 DS11873 Rev 5
VIPer11
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