STMicroelectronics VIPER01B Datasheet
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VIPer01B
SSOP10
Features
800 V avalanche-rugged power MOSFET allowing ultra wide V
AC
input range to be covered
Embedded HV startup and sense-FET
Current mode PWM controller
Drain current limit protection (OCP)
Wide supply voltage range: 4.5 V to 30 V
Self-supply option allows the auxiliary winding or bias components to be removed
Minimized system input power consumption:
– Less than 10 mW at 230 V
AC condition
in no-load
– Less than 400 mW at 230 V
AC mW load
with 250
Jittered switching frequency reduces the EMI filter cost:
– 60 kHz ± 7% (type L)
– 120 kHz ± 7% (type H)
Embedded E/A with 1.2 V reference
Protections with automatic restart: overload/short-circuit (OLP), line or output
OVP, V
CC
clamp
Pulse-skip protection to prevent flux-runaway
Embedded thermal shutdown
Built-in soft-start for improved system reliability
Energy saving off-line high voltage converter
Datasheet
-
production data
Applications
Low power SMPS for home appliances, building and home control, small industrial, consumers, lighting, motion control
Low power adapters
Description
The device is a high voltage converter smartly integrating an 800 V avalanche-rugged power
MOSFET with PWM current mode control. The power MOSFET with 800 V breakdown voltage allows the extended input voltage range to be applied, as well as the size of the DRAIN snubber circuit to be reduced. This IC meets the most stringent energy-saving standards as it has very low consumption and operates in pulse frequency modulation under light load. The design of flyback, buck and buck boost converters is supported. The integrated HV startup, sense-
FET, error amplifier and oscillator with jitter allow a complete application to be designed with the minimum number of components.
Figure 1. Basic application schematic
April 2018
This is information on a product in full production.
DocID031727 Rev 1 1/37 www.st.com
Contents
Contents
VIPer01B
Electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pulse frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Energy saving performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout guidelines and design recommendations . . . . . . . . . . . . . . . . . . . 32
SSOP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/37 DocID031727 Rev 1
VIPer01B
Contents
DocID031727 Rev 1 3/37
37
List of tables
List of tables
VIPer01B
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/37 DocID031727 Rev 1
VIPer01B
List of figures
List of figures
(R thJA
vs. T
J at A = 100 mm²) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
vs. T
J
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
J
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
vs. T
J
vs. V
DRAIN
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
vs. V
DRAIN
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
vs. V
DRAIN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
M
vs. T
J
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum avalanche energy vs. T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Connection for input overvoltage protection (isolated or non-isolated topologies) . . . . . . . 25
versus V
versus V
IN
IN
in no-load, V
OUT
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
in light load, V
OUT
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DocID031727 Rev 1 5/37
37
Pin setting VIPer01B
Figure 2. Connection diagram
SSOP10 Name
1
2
3
4
5
6 to 10
GND
VCC
DIS
FB
COMP
DRAIN
Table 1. Pin description
Function
Ground and MOSFET source.
Connection of source of the internal MOSFET and the return of the bias current of the device. All groundings of bias components must be tied to a trace going to this pin and kept separate from the pulsed current return.
Controller supply.
An external storage capacitor has to be connected across this pin and
GND. The pin, internally connected to the high voltage current source, provides the VCC capacitor charging current at startup and during steady-state operation, if the self-supply mode is selected. A small bypass capacitor (0.1 F typ.) in parallel, placed as close as possible to the IC, is also recommended, for noise filtering purpose.
Disable.
If its voltage exceeds the internal threshold V
DIS_th
(1.2 V typ.) for more than t
DEB time (1 ms, typ.), the PWM is disabled in auto-restart mode. An input overvoltage protection can be built by connecting a voltage divider between DIS pin and the rectified mains. In case of non-isolated topologies, with the same principle an output overvoltage protection can be implemented. If the disable function is not required, DIS pin must be soldered to GND, which excludes the function.
Direct feedback. It is the inverting input of the internal transconductance E/A, which is internally referenced to 1.2 V with respect to GND. In case of non- isolated converter, the output voltage information is directly fed into the pin through a voltage divider. In case of primary regulation, the FB voltage divider is connected to the VCC. The E/A is disabled soldering FB to GND.
Compensation.
It is the output of the internal E/A. A compensation network is placed between this pin and GND to achieve stability and good dynamic performance of the control loop. In case of secondary feedback, the internal E/A must be disabled and the COMP directly driven by the optocoupler to control the DRAIN peak current setpoint.
MOSFET drain.
The internal high voltage current source sinks current from this pin to charge the VCC capacitor at startup and during steady-state operation. These pins are mechanically connected to the internal metal PAD of the MOSFET in order to facilitate heat dissipation. On the PCB, copper area must be placed under these pins in order to decrease the total junction-to-ambient thermal resistance thus facilitating the power dissipation.
6/37 DocID031727 Rev 1
VIPer01B
2 Electrical and thermal ratings
Electrical and thermal ratings
Symbol Pin
Table 2. Absolute maximum ratings
Parameter (1) , (2) Min.
Max.
Unit
I
V
DS
DRAIN
6 to 10 Drain-to-source (ground) voltage
6 to 10
Pulsed drain current (pulse-width limited by
SOA)
-0.3
-
800
2
V
A
V
CC
I
CC
V
DIS
V
FB
V
COMP
P
TOT
T
J
T
STG
2
2
3
4
5
-
-
-
VCC voltage
VCC internal Zener current (pulsed)
DIS voltage
FB voltage
COMP voltage
Power dissipation at T
Junction temperature operating range
Storage temperature amb
< 50 °C
-0.3
-0.3
-0.3
-0.3
-40
-55
Internally limited
45
(3)
4.25
1
(4)
(5)
150
150
1. Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability.
3. Pulse-width limited by maximum power dissipation, P
TOT
.
4. The AMR value is intended when VCC 5 V, otherwise the value VCC + 0.3 V has to be considered.
5. When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 m thick).
V mA
V
V
V
W
°C
°C
Table 3. Thermal data
Max. value
Symbol Parameter Unit
SSOP10
R
R thJP thJA
(1)
Thermal resistance junction-pin
Thermal resistance junction-ambient (dissipated power 1 W)
Thermal resistance junction-ambient (dissipated power 1 W)
(2)
35
145
90
1. Derived by characterization.
2. When mounted on a standard single side FR4 board with 100 mm² (0.155² inch) of Cu (35 µm thick).
°C/W
DocID031727 Rev 1 7/37
37
Electrical and thermal ratings
Figure 3. R thJA/
(R thJA at A = 100 mm²)
VIPer01B
Symbol Parameter
Table 4. Avalanche characteristics
Test conditions
I
E
AR
AS
Avalanche current
Single pulse avalanche energy (1)
Repetitive and non-repetitive
Pulse-width limited by T
Jmax
L = 1 mH
I
AS
= 0.8 A
V
DS
R
G
= 50 V
= 47
Starting T
J
= 25 °C
1. Parameter derived by characterization.
Min. Typ. Max. Unit
0.8
A
1 mJ
8/37 DocID031727 Rev 1
VIPer01B Electrical and thermal ratings
Electrical characteristics
T j
= -40 to 125 °C, V
CC
= 9 V (unless otherwise specified).
Symbol
V
BVDSS
I
DSS
I
OFF
R
DS(on)
C
OSS EQ
Table 5. Power section
Parameter Test conditions
Breakdown voltage
Drain-source leakage current
OFF-state drain current
Static drain-source ON-resistance
Equivalent output capacitance
I
DRAIN
= 1 mA
V
COMP
T
J
= GND
= 25 °C
VDS = 400 V
V
COMP
= GND
T
J
= 25 °C
V
DRAIN
= max.rating
V
COMP
T
J
= GND
= 25 °C
I
DRAIN
= 360 mA
T
J
= 25 °C
I
DRAIN
= 360 mA
T
J
= 125 °C
V
GS
= 0
V
DS
= 0 to 640 V
T
J
= 25 °C
Min.
Typ.
Max. Unit
800
-
-
-
-
-
-
-
-
-
-
10
1
45
30
60
-
V
µA
pF
Symbol
R
G
I
CH1
I
CH2
I
CH3
(1)
Table 6. Supply section
Parameter
High voltage start-up current source
V
BVDSS_SU
V
HV_START
Breakdown voltage of start-up MOSFET
Drain-source start-up voltage
Start-up resistor
VCC charging current at startup
VCC charging current at startup
Max. VCC charging current in self-supply
Test conditions Min.
Typ.
Max.
Unit
-
T
J
= 25 °C
V
FB
> V
FB_REF
V
DRAIN
= 400 V
V
DRAIN
= 600 V
V
DRAIN
= 100 V
V
CC
= 0 V
V
FB
> V
FB_REF
V
DRAIN
= 100 V
V
CC
= 6 V
VF
FB
> V
FB_REF
V
DRAIN
= 100 V
V
CC
= 6 V
800
-
22
1.4
3.5
7.6
-
-
30
1.9
4.5
8.8
-
18
38
2.4
5.5
10
V
V
M mA
IC supply and consumptions
V
CC
V
CCclamp
Operating voltage range
Clamp voltage
V
GND
= 0 V
I
CC
= I clamp_max
4.5
-
30 32.5
30
35
V
V
DocID031727 Rev 1 9/37
37
Electrical and thermal ratings VIPer01B
Symbol
I clamp max t clamp max
V
CCon
V
CSon
V
CCoff
I q
I
CC
Table 6. Supply section (continued)
Parameter Test conditions Min.
Typ.
Max.
Unit
(2)
Clamp shutdown current
Clamp time before shutdown
30
325 500
mA
675 µs
VCC start-up threshold
HV current source turn-on threshold
UVLO
Quiescent current
Operating supply current, switching
-
V
FB
= 1.2 V
V
DRAIN
= 400 V
V
CC
falling
V
FB
= 1.2 V
V
DRAIN
= 400 V
Not switching
V
FB
> V
FB_REF
V
DS
= 150 V
V
COMP
= 1.2 V
F
OSC
= 60 kHz
V
DS
= 150 V
V
COMP
= 1.2 V
F
OSC
= 120 kHz
7.5
4
3.75
-
-
-
8
4.25
4
0.3
0.45
0.85
1.25
1
8.5
4.5
4.25
1.5
V
V
V
A mA
1. Current supplied during the main MOSFET OFF time only.
2. Parameter assured by design and characterization.
Symbol
E/A
V
FB_REF
V
FB_DIS
I
FB PULL UP
G
M
I
COMP1
I
COMP2
R
COMP(DYN)
Dynamic resistance
V
COMPH
V
COMPL
Parameter
Reference voltage
E/A disable voltage
Pull-up current
Transconductance
Max. source current
Max. sink current
Current limitation threshold
PFM threshold
Table 7. Controller section
Test conditions
-
-
-
-
V
COMP
= 1.5 V
V
FB
> V
FB_REF
V
COMP
= 1.5 V
V
FB
= 0.5 V
-
V
FB
= 2 V
V
COMP
= 1.5 V
V
COMP
= 2.7 V
V
FB
= GND
Min.
Typ.
Max.
Unit
1.175
150
0.9
350
1.2
180
1
500
1.225
210
1.1
650
V mV
µA
µA/V
65
70
50
-
-
100
105
58
3
0.8
135
140
66
-
-
µA
µA k
V
V
10/37 DocID031727 Rev 1
VIPer01B Electrical and thermal ratings
Symbol
Table 7. Controller section (continued)
Parameter Test conditions
OLP and timing
I t
I
V t t
DLIM
DLIM_PFM t
DIS_RESTART t t t
I
2 f
DISth
DIS
OVL
OVL_MAX
SS
ON_MIN
RESTART
Oscillator
Drain current limitation
Power coefficient
T
J
= 25 °C
VIPer012BHS
T
J
= 25 °C
VIPer013BLS
I
DLIM_TYP
2
X
F
OSC_TYP
T
V
J
= 25 °C
COMP
= V
COMPL
(1)
VIPer012BHS rain current limitation at light load
T
V
J
= 25 °C
COMP
= V
VIPer013BLS
Disable threshold voltage
Debounce time before DIS protection tripping
-
V
CC
= 9 V
V
COMP
= 1 V
V
FB
= V
FB_REF
Restart time after DIS protection tripping
Overload delay time
-
Max. overload delay time
Soft-start time
Minimum turn-on time
Restart time after fault
-
-
VIPer013BLS
F
OSC
= F
OSC MIN
VIPer012BHS
F
OSC
= F
OSC MIN
-
V
CC
= 9 V
V
COMP
= 1 V
V
FB
= V
FB_REF
F
F
OSC
OSC_MIN
F
D
Switching frequency
Minimum switching frequency
Modulation depth
T
J
= 25 °C
VIPer013BLS
T
J
= 25 °C
VIPer012BHS
T
J
= 25 °C
(2)
(3)
Min.
228
342
0.9 ·I
2 f
45
60
1.15
0.65
325
45
180
360
5
250
0.65
54
108
13.5
-
Typ.
240
360
I
2 f
65
80
1.2
1
500
50
200
400
8
-
1
60
120
15
±7
F
OSC
Max.
252
378
85
100
1.25
1.35
132
16.5
-
675
55
220
440
11
360
1.35
66
Unit mA
1.1 ·I
2 f A
2
·kHz mA
V ms ms ms ms ms ns s kHz kHz
%
DocID031727 Rev 1 11/37
37
Electrical and thermal ratings
Symbol
Table 7. Controller section (continued)
Parameter Test conditions Min.
F
M
D
MAX
Modulation frequency
Max. duty cycle
Thermal shutdown
-
70
TSD Thermal shutdown temperature
150
1. See Section 4.10: Pulse frequency modulation on page 23 .
2. See Section 4.7: Pulse-skipping on page 21
.
3. Parameter assured by design and characterization.
Typ.
260
-
Max.
-
80
Unit
Hz
%
160 -
VIPer01B
°C
12/37 DocID031727 Rev 1
VIPer01B
3 Typical electrical characteristics
Typical electrical characteristics
Figure 4. I
DLIM
vs. T
J
Figure 6. V
HV_START
vs. T
J
Figure 8. Quiescent current Iq vs. T
J
Figure 9. Operating current I
CC
vs. T
J
DocID031727 Rev 1 13/37
37
Typical electrical characteristics
Figure 10. I
CH1
vs. T
J
Figure 11. I
CH1
vs. V
DRAIN
VIPer01B
Figure 12. I
CH2
vs. T
J
Figure 13. I
CH2
vs. V
DRAIN
Figure 14. I
CH3
vs. T
J
Figure 15. I
CH3
vs. V
DRAIN
14/37 DocID031727 Rev 1
VIPer01B Typical electrical characteristics
Figure 16. G
M
vs. T
J
Figure
Figure 18. R
DS(on)
vs. T
J
Figure 19. Static drain-source on-resistance
Figure 20. V
BVDSS
vs. T
J
Figure 21. Output characteristic
DocID031727 Rev 1 15/37
37
Typical electrical characteristics
Figure 22. SOA SSOP10 package
VIPer01B
Figure 23. Maximum avalanche energy vs. T
J
8IFONPVOUFEPOBTUBOEBSETJOHMFTJEF'3CPBSE
XJUINN TRJOPG$V UIJDL
16/37 DocID031727 Rev 1
VIPer01B
Figure 24. Block diagram
General description
4.2 Typical power capability
Table 8. Typical power
Vin: 230 VAC Vin: 85-265 VAC
Adapter
(1)
Open frame
(2)
7 W 8 W 4 W 4.5 W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat-sinking.
DocID031727 Rev 1 17/37
37
General description VIPer01B
4.4
18/37
The primary switch is implemented with an avalanche-rugged N-channel MOSFET with minimum breakdown voltage 800 V, V
BVDSS
, and maximum on-resistance of 30 , R
The sense-FET is embedded and it allows a virtually lossless current sensing. The
DS(on)
.
MOSFET is embedded and it allows the HV voltage start-up operation.
The MOSFET gate driver controls the gate current during both turn-on and turn-off in order to minimize EMI. Under UVLO conditions the embedded pull-down circuit holds the gate low in order to ensure that the MOSFET cannot be turned on accidentally.
High voltage startup
The embedded high voltage startup includes both the 800 V start-up FET, whose gate is biased through the resistor R
G
, and the switchable HV current source, delivering the current
IHV. The major portion of I
HV
, (I
CH
), charges the capacitor connected to VCC. A minor portion is sunk by the controller block.
At startup, as the voltage across the DRAIN pin exceeds the V
HV_START current source is turned on, charging linearly the C
S
threshold, the HV
capacitor. At the very beginning of the startup, when Cs is fully discharged, the charging current is low, I
CH1
, in order to avoid IC damaging in case V
CC to I
CH2
is accidentally shorted to GND. As V
CC
in order to speed up the charging of C
S
.
exceeds 1 V, I
CH
is increased
As V
CC
reaches the start-up threshold V
CCon
(8 V typ.) the chip starts operating, the primary
MOSFET is enabled to switch, the HV current source is disabled and the device is powered by the energy stored in the C
S
capacitor.
In steady-state the IC supports two different kind of supplies: self-supply and external supply, as shown in
.
Figure 25. IC supply modes: self-supply and external supply
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GSPNUIFPVUQVU GSPN BVYJMJBSZ XJOEJOH
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In self-supply only one capacitor C
S the energy stored in C
S decays to V
CCson
I
CH3
until V
CC
. After the IC startup, due to its internal consumption, the VCC
(4.25 V, typ.) and the HV current source is turned on delivering the current
is recharged to V decays to V
CCson
again. The I
CH3
is connected to the VCC and the device is supplied by
CCon.
The HV current source is reactivated when V
CC
is supplied during the switching OFF time only. In external
DocID031727 Rev 1
VIPer01B General description supply the HV current source is always kept off by maintaining the V
CC
above V
CSon
. This can be obtained through a transformer auxiliary winding or a connection from the output, the latter in case of non-isolated topology only. In this case the residual consumption is given by the power dissipated on R
G
, calculated as follows:
Equation 1
P =
V
2
R
G
At the nominal input voltage, 230 V
AC the worst-case consumption (R
G
, the typical consumption (R
= 22 M ) is 4.8 mW.
G
= 30 M ) is 3.5 mW and
When the IC is disconnected from the mains, or there is a mains interruption, for some time the converter keeps on working, powered by the energy stored in the input bulk capacitor.
When it is discharged below a critical value, the converter is no longer able to keep the output voltage regulated. During the power down, when the DRAIN voltage becomes too low, the HV current source (I
HV
) remains off and the IC is stopped as soon as the VCC drops below the UVLO threshold, V
CCoff
.
Figure 26. Power-ON and power-OFF
DocID031727 Rev 1 19/37
37
General description VIPer01B
4.5 Soft-start
The internal soft-start function of the device progressively increases the cycle-by-cycle current limitation set point from zero up to I
DLIM
in 8 steps. The soft-start time, t
SS
, is internally set at 8 ms. This function is activated at any attempt of converter startup and at any restart after a fault event. The feature protects the system at the startup when the output load occurs like a short-circuit and the converter works at its maximum drain current limitation.
Figure 27. Soft startup
4.6 Oscillator
The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by approximately ± 7% kHz F
OSC
at 260 Hz rate. The purpose of the jittering is to get a spread-spectrum action that distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having the same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially when measured with the average detection method or, which is the same, to pass the EMI tests with an input filter of smaller size than that needed in absence of jittering feature.
Two options with different switching frequencies, F
OSC
120 kHz (H type).
, are available: 60 (L type) and
20/37 DocID031727 Rev 1
VIPer01B General description
4.7 Pulse-skipping
The IC embeds a pulse-skip circuit that operates in the following ways:
Each time the DRAIN peak current exceeds I
DLIM level within t
ON_MIN,
the switching cycle is skipped. The cycles can be skipped until the minimum switching frequency is reached, F
OSC_MIN
(15 kHz).
Each time the DRAIN peak current does not exceed I
DLIM
within t
ON_MIN
, a switching cycle is restored. The cycles can be restored until the nominal switching frequency is reached, F
OSC
(60 or 120 kHz).
If the converter is operated at F
OSC_MIN or 400 ms typ., depending on F
OSC after the time t
RESTART
(1 s, typ.).
, the IC is turned off after the time t
OVL_MAX
(200 ms
) and then automatically restarted with soft-start phase,
The protection is intended to avoid the so called “flux-runaway” condition often present at converter startup and due to the fact that the primary MOSFET, which is turned on by the internal oscillator, cannot be turned off before than the minimum on-time.
During the on-time, the inductor is charged by the input voltage and if it cannot be discharged by the same amount during the off-time, in every switching cycle there is an increase of the average inductor current, that can reach dangerously high values until the output capacitor is not charged enough to ensure the inductor discharge rate needed for the volt-second balance. This condition may happen at converter startup, because of the low output voltage.
In Figure 28 the effect of pulse-skipping feature on the DRAIN peak current shape is shown
(solid line), compared with the DRAIN peak current shape when pulse-skipping feature is not implemented (dashed line).
Providing more time for cycle-by-cycle inductor discharge when needed, this feature is effective by keeping low the maximum DRAIN peak current avoiding the flux-runaway condition.
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General description
Figure 28. Pulse-skipping during startup
VIPer01B
22/37
The IC embeds a transconductance type error amplifier (E/A) whose inverting input, ground reference and output are FB and COMP, respectively. The internal reference voltage of the
E/A is V
FB_REF
(1.2 V typical value referred to GND). In non-isolated topologies this tightly regulates positive output voltages through a simple voltage divider applied to the output voltage terminal, FB and GND.
The E/A output is scaled down and fed into the PWM comparator, where it is compared to the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-by- cycle drain current limitation.
An R-C network connected on the output of the E/A (COMP) is usually used to stabilize the overall control loop.
The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is accidentally left floating.
The E/A is disabled if the FB voltage is lower than V
FB_DIS
(200 mV, typ.).
DocID031727 Rev 1
VIPer01B General description
When a secondary feedback is required, the internal E/A has to be disabled shorting FB to
GND (V
FB
< V
FB_DIS
). With this setting, COMP is internally connected to a pre-regulated voltage through the pull-up resistor R
COMP(DYN) is set by the current sunk.
, (60 k , typ.) and the voltage across COMP
This allows the output voltage value to be set through an external error amplifier (TL431 or similar) placed on the secondary side, whose error signal is used to set the DRAIN peak current setpoint corresponding to the output power demand. If isolation is required, the error signal must be transferred through an optocoupler, with the phototransistor collector connected across COMP and GND.
4.10 Pulse frequency modulation
If the output load is decreased, the feedback loop reacts lowering the V
COMP
voltage, which reduces the DRAIN peak current setpoint, down to the minimum value of I
DLIM_PFM the V
COMPL
threshold is reached.
when
If the load is furtherly decreased, the DRAIN peak current value is maintained at I
DLIM_PFM and some PWM cycles are skipped. This kind of operation is referred to as “pulse frequency modulation” (PFM), the number of the skipped cycles depends on the balance between the output power demand and the power transferred from the input. The result is an equivalent switching frequency which can go down to some hundreds Hz, thus reducing all the frequency-related losses.
This kind of operation, together with the extremely low IC quiescent current, allows very low input power consumption in no-load and light load, while the low DRAIN peak current value, I
DLIM_PFM
, prevents any audible noise which could arise from low switching frequency values. When the load is increased, V
COMP reaches its maximum at V limitation (I
DLIM
COMPH
) is reached.
increases and PFM is exited. V
and corresponding to that value, the DRAIN current
COMP
To manage the overload condition, the IC embeds the following main blocks: the OCP comparator to turn off the power MOSFET when the drain current reaches its limit (I
DLIM the up and down OCP counter to define the turn-off delay time in case of continuous
) , overload (t
OVL
(t
RESTART
= 50 ms typ.) and the timer to define the restart time after protection tripping
= 1 s typ.).
In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn-off of the power switch is triggered by the
OCP comparator instead of PWM comparator. Every cycle where this condition is met, the
OCP counter is incremented and if the fault condition lasts longer than t
OVL
(corresponding to the counter end-of-count), the protection is tripped, the PWM is disabled for t
RESTART
, then it resumes switching with soft-start and, if the fault is still present, it is disabled again after t
OVL
. The OLP management prevents IC from operating indefinitely at IDLIM and the low repetition rate of the restart attempts of the converter avoids IC overheating in case of repeated fault events.
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General description VIPer01B
After the fault removal, the IC resumes working normally. If the fault is removed earlier than the protection tripping (before t
OVL
), the t
OVL
-counter is decremented on a cycle-by-cycle basis down to zero and the protection is not tripped. If the fault is removed during t
RESTART the IC waits for the t
RESTART
period has elapsed before resuming switching.
,
In fault condition the V
CC
ranges between V
CSon
and V activation of the HV current source recharging the V
CC
CCon
levels, due to the periodical
capacitor.
Figure 29. Short-circuit condition
4.12 VCC clamp protection
This protection can occur when the IC is supplied by auxiliary winding or diode from the output voltage, when an output overvoltage produces an increase of V
CC
.
If VCC reaches the clamp level V
CCclamp
(30 V, min. referred to GND) the current injected into the pin is monitored and if it exceeds the internal threshold I clamp_max more than t clamp_max
(500 µs, typ.), the PWM is disabled for t
RESTART
(30 mA, typ.) for
(1 s, typ.) and then activated again in soft-start phase. The protection is disabled during the soft-start time.
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VIPer01B General description
When the voltage across the pin is externally pulled above V
DIS_th t
DEB
(1.2 V typ.) for more than
(for instance by a voltage divider connected to some higher voltages), the PWM is disabled. If the voltage divider on the DIS pin is connected to the rectified mains, as shown in
Figure 30 , an input overvoltage protection can be built.
Figure 30. Connection for input overvoltage protection (isolated or non-isolated topologies)
In case of non-isolated topologies, by following the same principle an output overvoltage
protection can be built, as shown in Figure 31
.
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General description VIPer01B
Figure 31. Connection for output overvoltage protection (non-isolated topologies)
26/37
If V
OVP
is the desired input/output overvoltage threshold, the resistors R
H
and R voltage divider are to be selected according to the following formula:
L
of the
Equation 2
R
H
= (V
OVP
/V
DIS_th
- 1) · R
L
The power dissipation associated to the DIS network is:
Equation 3
P
DIS
V
IN
= P
RH
+ P
RL
=
V
IN
–
R
V
H
2
+
V
R
L
2 in case of connection for the input overvoltage detection and
Equation 4
P
DIS
V
OUT
= P
RH
+ P
RL
=
V
OUT
– V
DIS
R
H
2
+
V
DIS
R
L
2 in case of connection for the output overvoltage detection.
DocID031727 Rev 1
VIPer01B General description
If the junction temperature becomes higher than the internal threshold TSD (160 °C, typ.), the PWM is disabled. After t
RESTART
time, three switching cycles are performed, during which the temperature sensor embedded in the power MOSFET section is checked. If a t junction temperature above T
SD
RESTART
is still measured, the PWM is maintained disabled for
time, otherwise it resumes switching with soft-start phase.
During t
RESTART
V
CC
is maintained between V
CSon
and V
CCon
levels by the HV current source periodical activation. Such a behavior is summarized in
.
Figure 32. Thermal shutdown timing diagram
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37
Application information
Figure 33. Flyback converter (non-isolated)
VIPer01B
Figure 34. Flyback converter with line OVP (non-isolated)
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VIPer01B
Figure 35. Flyback converter (isolated)
Application information
Figure 36. Primary side regulation isolated flyback converter
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37
Application information
Figure 37. Buck converter (positive output)
VIPer01B
Figure 38. Buck-boost converter (negative output)
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VIPer01B
5.2
Application information
Energy saving performance
The device allows designing applications to be compliant with the most stringent energy saving regulations. In order to show the typical performance is achievable, the active mode average efficiency and the efficiency at 10% of the rated output power of a single output flyback converter have been measured and are reported in
. In addition, no-load and light load consumptions are shown in
V
IN
115 V
AC
230 V
AC
Table 9. Power supply efficiency, V
OUT
= 5 V
10% output load efficiency [%]
Active mode average efficiency [%]
Pin at no-load [mW]
72.2
65.1
74.6
75.1
4.5
8.6
Figure 39. P
IN
versus V
IN
in no-load, V
OUT
= 5 V
Figure 40. P
IN
versus V
IN
in light load, V
OUT
= 5 V
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Application information VIPer01B
32/37
A proper printed circuit board layout ensures the correct operation of any switch-mode converter and this is true for the VIPer as well. The main reasons to have a proper PCB layout are:
Providing clean signals to the IC, ensuring good immunity against external and switching noises.
Reducing the electromagnetic interferences, both radiated and conducted, to pass the
EMC tests more easily.
If the VIPer is used to design a SMPS, the following basic rules should be considered:
Separating signal from power tracks.
Generally, traces carrying signal currents should run far from others carrying pulsed currents or with fast swinging voltages.
Signal ground traces should be connected to the IC signal ground, GND, using a single
“star point”, placed close to the IC. Power ground traces should be connected to the IC power ground, GND. The compensation network should be connected to the COMP, maintaining the trace to GND as short as possible. In case of two-layer PCB, it is a good practice to route signal traces on one PCB side and power traces on the other side.
Filtering sensitive pins.
Some crucial points of the circuit need or may need filtering.
A small high-frequency bypass capacitor to GND might be useful to get a clean bias voltage for the signal part of the IC and protect the IC itself during EFT/ESD tests. A low
ESL ceramic capacitor (a few hundreds pF up to 0.1 F) should be connected across
VCC and GND, placed as close as possible to the IC. With flyback topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary return and then to the main GND using a single track.
Keeping power loops as confined as possible. The area circumscribed by current loops where high pulsed current flow should be minimized to reduce its parasitic self- inductance and the radiated electromagnetic field. As a consequence, the electromagnetic interferences produced by the power supply during the switching are highly reduced. In a flyback converter the most critical loops are: the one including the input bulk capacitor, the power switch, the power transformer, the one including the snubber, the one including the secondary winding, the output rectifier and the output capacitor. In a buck converter the most critical loop is the one including the input bulk capacitor, the power switch, the power inductor, the output capacitor and the free- wheeling diode.
Reducing line lengths. Any wire acts as an antenna. With the very short rise times exhibited by EFT pulses, any antenna can receive high voltage spikes. By reducing line lengths, the level of received radiated energy is reduced, and the resulting spikes from electrostatic discharges are lower. This also keeps both resistive and inductive effects to a minimum. In particular, all traces carrying high currents, especially if pulsed (tracks of the power loops) should be as short and wide as possible.
Optimizing track routing. As levels of pickup from static discharges are likely greater near the edges of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon as possible where applicable. Since vias are to be considered inductive elements, it is recommended to minimize their number in the signal path and avoid them in the power path.
Improving thermal dissipation.
An adequate copper area has to be provided under the DRAIN pins as heatsink, while it is not recommended to place large copper areas on the GND.
DocID031727 Rev 1
VIPer01B Application information
Figure 41. Recommended routing for flyback converter
Figure 42. Recommended routing for buck converter
DocID031727 Rev 1 33/37
37
Package information VIPer01B
6.1
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
SSOP10 package information
Figure 43. SSOP10 package outline
34/37 DocID031727 Rev 1
VIPer01B
Symbol
D
E b c
A
A1
A2
E1 e h
L
K
Table 10. SSOP10 package mechanical data
Dimensions (mm)
Min.
-
0.10
1.25
0.31
0.17
4.80
5.80
3.80
-
0.25
0.40
0°
Typ.
-
-
4.90
6
-
-
-
3.90
1
-
-
-
Figure 44. SSOP10 recommended footprint
Package information
Max.
1.75
0.25
4
-
0.50
0.90
8°
0.51
0.25
5
6.20
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Ordering information VIPer01B
Order code
VIPer013BLSTR
VIPer012BHSTR
Table 11. Order code
IDLIM (OCP) FOSC ± jitter
360 mA
240 mA
60 kHz ± 7%
120 kHz ± 7%
Package
SSOP10 (tape and reel)
Date
04-Apr-2018
Table 12. Document revision history
Revision Changes
1 Initial release.
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VIPer01B
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STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
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