STMicroelectronics A3G4250D Datasheet

A3G4250D

MEMS motion sensor:

3-axis digital output gyroscope

Features

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Wide supply voltage: 2.4 V to 3.6 V

±245 dps full scale

I

2

C/SPI digital output interface

16-bit rate value data output

8-bit temperature data output

Two digital output lines (interrupt and data ready)

Integrated low and high-pass filters with userselectable bandwidth

Ultra-stable over temperature and time

Low-voltage-compatible IOs (1.8 V)

Embedded power-down and sleep mode

Embedded temperature sensor

Embedded FIFO

High shock survivability

Extended operating temperature range (-40 °C to +85 °C)

ECOPACK

®

RoHS and “Green” compliant

AEC-Q100 qualification

Applications

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In-dash car navigation

Telematics, e-Tolling

Motion control with MMI (man-machine interface)

Appliances and robotics

LGA-16 (4x4x1.1 mm

3

)

Description

The A3G4250D is a low-power 3-axis angular rate sensor able to provide unprecedented stability at zero rate level and sensitivity over temperature and time. It includes a sensing element and an IC interface capable of providing the measured angular rate to the external world through a standard SPI digital interface. An I

2

C-compatible interface is also available.

The sensing element is manufactured using a dedicated micro-machining process developed by

STMicroelectronics to produce inertial sensors and actuators on silicon wafers.

The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics.

The A3G4250D has a full scale of ±245 dps and is capable of measuring rates with a userselectable bandwidth.

The A3G4250D is available in a plastic land grid array (LGA) package and can operate within a temperature range of -40 °C to +85 °C.

Table 1.

Device summary

Order code Temperature range (°C)

A3G4250D

A3G4250DTR

-40 to +85

-40 to +85

Package

LGA-16 (4x4x1.1 mm

3

)

LGA-16 (4x4x1.1 mm

3

)

Packing

Tray

Tape and reel

February 2012 Doc 022768 Rev 3 1/44 www.st.com

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Contents

Contents

1

2

3

A3G4250D

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Mechanical and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4

Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.1

2.4.2

SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6.1

2.6.2

2.6.3

Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Stability over temperature and time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7

Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Main digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2

FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2.1

3.2.2

3.2.3

3.2.4

Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1

I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.1

I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2

SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2.1

5.2.2

SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/44 Doc 022768 Rev 3

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A3G4250D Contents

5.2.3

SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1

WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2

CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.3

CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.4

CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.5

CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.6

CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7

REFERENCE/DATACAPTURE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.8

OUT_TEMP (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.9

STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.10

OUT_X_L (28h), OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.11

OUT_Y_L (2Ah), OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.12

OUT_Z_L (2Ch), OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.13

FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.14

FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.15

INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.16

INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.17

INT1_THS_XH (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.18

INT1_THS_XL (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.19

INT1_THS_YH (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.20

INT1_THS_YL (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.21

INT1_THS_ZH (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.22

INT1_THS_ZL (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.23

INT1_DURATION (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Doc 022768 Rev 3 3/44

List of tables

List of tables

A3G4250D

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Temp. sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9.

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 10.

PLL low-pass filter component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11.

Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12.

I2C terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13.

SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14.

Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 15.

Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16.

Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 23

Table 17.

Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23

Table 18.

Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19.

WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20.

CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21.

CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 22.

DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 23.

Power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 24.

CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 25.

CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 26.

High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 27.

High-pass filter cut-off frequency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 28.

CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 29.

CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 30.

CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 31.

CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 32.

Self-test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 33.

CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 34.

CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 35.

Out_Sel configuration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 36.

INT_SEL configuration settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 37.

REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 38.

REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 39.

OUT_TEMP register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 40.

OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 41.

STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 42.

STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 43.

REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 44.

REFERENCE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 45.

FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 46.

FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 47.

FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 48.

INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4/44 Doc 022768 Rev 3

A3G4250D List of tables

Table 49.

INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 50.

INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 51.

INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 52.

INT1_THS_XH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 53.

INT1_THS_XH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 54.

INT1_THS_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 55.

INT1_THS_XL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 56.

INT1_THS_YH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 57.

INT1_THS_YH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 58.

INT1_THS_YL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 59.

INT1_THS_YL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 60.

INT1_THS_ZH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 61.

INT1_THS_ZH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 62.

INT1_THS_ZL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 63.

INT1_THS_ZL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 64.

INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 65.

INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 66.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Doc 022768 Rev 3 5/44

List of figures

List of figures

A3G4250D

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3.

A3G4250D external low-pass filter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4.

SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5.

I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7.

Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8.

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9.

Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10.

FIFO access sequence in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11.

A3G4250D electrical connections and external component values . . . . . . . . . . . . . . . . . . 19

Figure 12.

Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13.

SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14.

Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15.

SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16.

Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17.

SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18.

INT1_Sel and Out_Sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 19.

Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20.

Wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 21.

LGA-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6/44 Doc 022768 Rev 3

A3G4250D

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

+

Ω

x,y,z

X+

Y+

Z+

M

U

X

Z-

Y-

X-

CHARGE

AMP

MIXER LOW-PA SS

FILTER

DRIVING MA SS

Feed ba ck loop

E

R

A

T

E

M

P

T

U

R

E

S

O

R

S

E

N

A

D

C

1

A

D

C

2

I

T

A

L

D

I

G

T

E

R

I

N

G

F

I

L

I2C

S PI

C S

S CL/ S PC

S DA/ S DO/ S DI

S DO

REFERENCE

TRIMMING

CIRCUIT S

FIFO

CLOCK

&

PHA S E GENERATOR

CONTROL LOGIC

&

INTERRUPT GEN.

INT1

DRDY/INT2

AM07225v1

The vibration of the structure is maintained by drive circuitry in a feedback loop. The sensing signal is filtered and appears as a digital signal at the output.

Figure 2.

Pin connection

+Ω

Z

1

X

+Ω

Y

+Ω

X

(TOP VIEW)

DIRECTION

S

OF THE

DETECTABLE

ANGULAR RATE

S

RE

S

12

RE

S

RE

S

RE

S 9

1 3 16

8

BOTTOM

VIEW

1

4

Vdd_IO

S

CL/

S

PC

S

DA/

S

DI/

S

DO

S

DO/

S

A0

5

AM07226v1

Doc 022768 Rev 3 7/44

Block diagram and pin description A3G4250D

12

13

14

15

16

6

7

8

9

10

11

Table 2.

Pin#

1

2

3

4

5

Pin description

Name Function

Vdd_IO

SCL

SPC

SDA

SDI

SDO

SDO

SA0

CS

Power supply for I/O pins

I

2

C serial clock (SCL)

SPI serial port clock (SPC)

I

2

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

SPI serial data output (SDO)

I

2

C least significant bit of the device address (SA0)

SPI enable

I

2

C/SPI mode selection (1: SPI idle mode / I

2

C communication enabled; 0: SPI communication mode / I

2

C disabled)

DRDY/INT2 Data ready/FIFO interrupt

INT1

Reserved

Programmable interrupt

Connect to GND

Reserved

Reserved

Reserved

Connect to GND

Connect to GND

Connect to GND

Reserved

GND

PLLFILT

Reserved

Vdd

Connect to GND

0 V supply

Phase-locked loop filter (see

Figure 3

)

Connect to Vdd

Power supply

Figure 3.

A3G4250D external low-pass filter values

(a)

#APACITORFOR

,OWPASSFILTER

TOPIN

#

# 2

'.$

!-V

8/44 a.

Pin 14 PLLFILT maximum voltage level is equal to Vdd.

Doc 022768 Rev 3

A3G4250D

Table 3.

Filter values

Parameter

C1

C2

R2

Block diagram and pin description

Typical value

10 nF

470 nF

10 k

Ω

Doc 022768 Rev 3 9/44

Mechanical and electrical characteristics

2 Mechanical and electrical characteristics

A3G4250D

@ Vdd = 3.0 V, T = -40... +85 °C, unless otherwise noted

(b)

.

Table 4.

Mechanical characteristics

Test condition Symbol

FS

So

Parameter

Measurement range

(2)

Sensitivity

(3)

SoDr

Sensitivity change vs. temperature

DVoff Digital zero-rate level

(3)

OffDr

NL

Zero-rate level change vs. temperature

Non linearity

(2)

DST Self-test output change

Best fit straight line

Min.

7.4

-25

-5

55

Rn Rate noise density BW = 50 Hz

ODR Digital output data rate

Top

Operating temperature range

1.

Typical specifications are not guaranteed; typical values at +25 °C.

2.

Guaranteed by design.

3.

Across temperature and after MSL3 preconditioning.

89/176/

357/714

-40

Typ.

(1)

±245

8.75

±2

±0.03

0.2

130

0.03

105/208/

420/840

Max.

10.1

+25

+5

245

0.15

121/239/

483/966

+85

Unit dps mdps/digit

% dps dps/°C

% FS dps dps/ sqrt(Hz)

Hz

°C

10/44 b.

The product is factory calibrated at 3.0 V. The operational power supply range is specified in

Table 5

.

Doc 022768 Rev 3

A3G4250D Mechanical and electrical characteristics

@ Vdd = 3.0 V, T = -40... +85 °C, unless otherwise noted

(c)

.

Table 5.

Symbol

Electrical characteristics

Parameter

Vdd Supply voltage

Vdd_IO I/O pins supply voltage

(2)

Idd Supply current

Test condition Min.

2.4

1.71

4.8

Typ.

(1)

3.0

6.1

Max.

3.6

Vdd+0.1

7.0

IddSL

IddPdn

Top

Supply current in sleep mode

(3)

Supply current in power-down mode

(4)

Operating temperature range

Selectable by digital interface

Selectable by digital interface

-40

1.5

5 10

+85

1.

Typical specifications are not guaranteed; typical values at +25 °C.

2.

It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off.

3.

Sleep mode introduces a faster turn-on time compared to power-down mode.

4.

Verified at wafer level.

Unit

V

V mA mA

µA

°C

@ Vdd = 3.0 V, T = 25 °C, unless otherwise noted

(d)

.

Table 6.

Symbol

Temp. sensor characteristics

Parameter Test condition

TSDr

TODR

Top

Temperature sensor output change vs. temperature

Temperature refresh rate

Operating temperature range

-

1.

Typical specifications are not guaranteed; typical values at +25 °C.

Min.

-40

Typ.

(1)

-1

1

Max.

Unit

+85

°C/digit

Hz

°C c.

The product is factory calibrated at 3.0 V.

d.

The product is factory calibrated at 3.0 V.

Doc 022768 Rev 3 11/44

Mechanical and electrical characteristics A3G4250D

2.4.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 7.

SPI slave timing values

Value

(1)

Symbol Parameter Unit

Min.

Max.

tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO)

SPI clock cycle

SPI clock frequency

CS setup time

CS hold time

SDI input setup time

SDI input hold time

SDO valid output time

SDO output hold time

SDO output disable time

100

5

8

5

15

6

10

50 ns

MHz ns

50

1.

Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not tested in production.

Figure 4.

SPI slave timing diagram

(e)

&6

W

VX&6

63&

W

VX6,

W

K6,

6', 06%,1

W

Y62

W

F63&

6'2 06%287

W

K62

W

K&6

/6%,1

W

GLV62

/6%287

!-V e.

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

12/44 Doc 022768 Rev 3

A3G4250D Mechanical and electrical characteristics

2.4.2 I

2

C - inter IC control interface

Subject to general operating conditions for Vdd and Top.

Table 8.

I

2

C slave timing values

I

2

C standard mode

(1)

Symbol Parameter

Min.

Max.

f

(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)

SCL clock frequency

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

START condition hold time

0

4.7

4.0

250

0

4

100

3.45

t su(SR)

Repeated START condition setup time

4.7

t su(SP)

STOP condition setup time 4 t w(SP:SR)

Bus free time between STOP and START condition

4.7

1.

Data based on standard I

2

C protocol requirement; not tested in production.

Figure 5.

I

2

C slave timing diagram

(f)

I

2

C fast mode

(1)

Min.

0

Max.

400

1.3

0.6

100

0

0.6

0.9

0.6

0.6

1.3

µs

Unit kHz

µs ns

µs

6'$

67$57

W

VX65

W

Z6365

5(3($7('

67$57

67$57

W

I6'$

W

U6'$

W

VX6'$

W

K6'$

W

VX63

6723

6&/

W

K67

W

Z6&//

W

Z6&/+

W

U6&/

W

I6&/

!-V f.

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

Doc 022768 Rev 3 13/44

Mechanical and electrical characteristics A3G4250D

Any stress above that listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 9.

Symbol

Absolute maximum ratings

Ratings

Vdd

T

STG

Sg

Supply voltage

Storage temperature range

Acceleration g for 0.1 ms

ESD Electrostatic discharge protection

Maximum value

-0.3 to 4.8

-40 to +125

10,000

2 (HBM)

Unit

V

°C g kV

This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part

This is an ESD sensitive device, improper handling can cause permanent damage to the part

14/44 Doc 022768 Rev 3

A3G4250D Mechanical and electrical characteristics

2.6 Terminology

2.6.1 Sensitivity

An angular rate gyroscope is a device that produces a positive-going digital output for counter-clockwise rotation around the sensitive axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time.

2.6.3

The zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and, therefore, the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time.

Stability over temperature and time

Thanks to the unique single-driving mass approach and optimized design, ST gyroscopes are able to guarantee a perfect match of the MEMS mechanical mass and the ASIC interface, and deliver unprecedented levels of stability over temperature and time.

With the zero-rate level and sensitivity performances, up to ten times better than equivalent products currently available on the market, the A3G4250D allows the user to avoid any further compensation and calibration during production for a faster time to market, easy application implementation, higher performance, and cost saving.

The LGA package is compliant with the ECOPACK

®

, RoHS and “Green” standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “pin 1 indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com/ .

Doc 022768 Rev 3 15/44

Main digital blocks

3 Main digital blocks

A3G4250D

Figure 6.

Block diagram

!$# ,0&

/UT?3EL

(0&

(0EN

,0&

).4?3EL

$ATA2EG

&)&/

XX

)NTERRUPT

GENERATOR

) #

30)

3#22%'

#/.&2%'

).4

!-V

3.2 FIFO

The A3G4250D embeds a 32-slot, 16-bit data FIFO for each of the three output channels: yaw, pitch, and roll. This allows consistent power saving for the system, as the host processor does not need to continuously poll data from the sensor. Instead, it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work in five different modes. Each mode is selected by the FIFO_MODE bits in FIFO_CTRL_REG.

Programmable watermark level, FIFO_empty or FIFO_Full events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3), and event detection information is available in FIFO_SRC_REG. The watermark level can be configured to WTM4: 0 in FIFO_CTRL_REG.

16/44

In bypass mode, the FIFO is not operational and for this reason it remains empty. As illustrated in

Figure 7 , only the first address is used for each channel. The remaining FIFO

slots are empty. When new data is available, the old data is overwritten.

Doc 022768 Rev 3

A3G4250D

Figure 7.

Bypass mode

X

I

Y

I

Z

I

X

EMPTY

X

X

Y

Y

I

Z

Z

Z

Main digital blocks

X Y Z

!-V

In FIFO mode, data from the yaw, pitch, and roll channels are stored in the FIFO. A watermark interrupt can be enabled (I2_WMK bit in CTRL_REG3), which is triggered when the FIFO is filled to the level specified in the WTM 4: 0 bits of FIFO_CTRL_REG. The FIFO continues filling until it is full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the

FIFO stops collecting data from the input channels. To restart data collection, it is necessary to write FIFO_CTRL_REG back to bypass mode.

FIFO mode is represented in

Figure 8 .

Doc 022768 Rev 3 17/44

Main digital blocks

Figure 8.

FIFO mode

X

I

Y

I

Z

I

X

X

X

Y

Y

I

Z

Z

Z

A3G4250D

X Y Z

!-V

In stream mode, data from yaw, pitch, and roll measurements are stored in the FIFO. A watermark interrupt can be enabled and set as in FIFO mode. The FIFO continues filling until full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the FIFO discards the older data as the new data arrives. Programmable watermark level events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3).

Stream mode is represented in

Figure 9 .

18/44 Doc 022768 Rev 3

A3G4250D

Figure 9.

Stream mode

X

I

Y

I

Z

I

X

X

X

X

X

Y

Y

Y

Y

Y

Z

Z

Z

Z

Z

Main digital blocks

3.2.4

!-V

Retrieve data from FIFO

FIFO data is read through the OUT_X, OUT_Y, and OUT_Z registers. When the FIFO is in stream, trigger or FIFO mode, a read operation to the OUT_X, OUT_Y or OUT_Z registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest pitch, roll, and yaw data are placed in the OUT_X, OUT_Y and OUT_Z registers, and both single read and read_burst (X, Y & Z with auto-incremental address) operations can be used. In read_burst mode, when data included in OUT_Z_H is read, the system again starts to read information from addr OUT_X_L.

The reading from FIFO may be executed either in synchronous or asynchronous mode. For correct data acquisition, the following points need to be followed:

1.

If reading is synchronous, all data should be acquired within one ODR cycle

2. If reading is asynchronous, an appropriate FIFO access sequence must be applied: a) A single dummy read @ 28h (increment bit = 0) to update data out b) A burst read of 6 bytes from 2Ah (Y low) up to 29h:

– Y(2A-2Bh)

– Z(2C - 2Dh)

– X(28-29h)

Figure 10

illustrates the correct sequence with a flow diagram:

Doc 022768 Rev 3 19/44

Main digital blocks

Figure 10.

FIFO access sequence in asynchronous mode

A3G4250D

No

WTM = ‘1’

Yes

Read FIFO SRC (2Fh) n = FSS<4-0> n--

No

Dummy Read from ‘28h’

(increment bit =‘0’)

Burst Read from ‘2Ah’ of

6 registers (Y, Z, X)

Yes

n = 0

Example:

FSS = 1 read twice

FSS = 2 read 3 times

AM1024 8 V1

If the above sequence is not followed, the acquisition from FIFO may lead to corrupted data.

20/44 Doc 022768 Rev 3

A3G4250D Application hints

Figure 11.

A3G4250D electrical connections and external component values

Vdd GND GND

+Ω

Z

100 nF 10 µ F

1

X

+Ω

Y

+Ω

X

(TOP VIEW)

DIRECTION S OF THE

DETECTABLE

ANGULAR RATE S

Vdd_IO

S CL/ S PC

S DA_ S DI_ S DO

S DO/ S A0

1

16

TOP

VIEW

1 3

12

4

5 8

9

10nF

C1

10kOhm

R2

C2

470nF

C S DR INT

Vdd I2C bus

Rp u Rp u = 10kOhm

S CL/ S PC

S DA_ S DI_ S DO

P u llu p to b e a dded when I2C interf a ce i s us ed

AM07949V1

Power supply decoupling capacitors (100 nF ceramic or polyester +10 µF) should be placed as near as possible to the device (common design practice).

If Vdd and Vdd_IO are not connected together, power supply decoupling capacitors

(100 nF and 10 µF between Vdd and common ground, 100 nF between Vdd_IO and common ground) should be placed as near as possible to the device (common design practice).

The A3G4250D IC includes a PLL (phase locked loop) circuit to synchronize driving and sensing interfaces. Capacitors and resistors must be added at the PLLFILT pin (as shown in

Figure 11 ) to implement a second-order low-pass filter. Table 10

summarizes the PLL lowpass filter component values.

Table 10.

PLL low-pass filter component values

Component

C1

Value

10 nF ± 10%

Doc 022768 Rev 3 21/44

Application hints

Table 10.

PLL low-pass filter component values

Component

C2

R2

Value

470 nF ± 10%

10 k

Ω

± 10%

A3G4250D

22/44 Doc 022768 Rev 3

A3G4250D Digital interfaces

The registers embedded in the A3G4250D may be accessed through both the I

2

C and SPI serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire interface mode.

The serial interfaces are mapped onto the same pins. To select/exploit the I

2

C interface, the

CS line must be tied high (i.e., connected to Vdd_IO).

Table 11.

Serial interface pin description

Pin name Pin description

CS

SCL/SPC

SDA/SDI/SDO

SDO

SPI enable

I

2

C/SPI mode selection (1: SPI idle mode / I

2

C communication enabled; 0: SPI communication mode / I

2

C disabled)

I

2

C serial clock (SCL)

SPI serial port clock (SPC)

I

2

C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

SPI serial data output (SDO)

I

2

C least significant bit of the device address

5.1 I

2

C serial interface

The A3G4250D I

2

C is a bus slave. The I

2

C is employed to write data to registers whose content can also be read back.

The relevant I

2

C terminology is given in the table below.

Table 12.

I

2

C terminology

Term

Transmitter

Receiver

Master

Slave

Description

The device which sends data to the bus

The device which receives data from the bus

The device which initiates a transfer, generates clock signals and terminates a transfer

The device addressed by the master

There are two signals associated with the I

2

C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bi-directional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free both the lines are high.

The I

2

C interface is compliant with fast mode (400 kHz) I

2

C standards as well as with normal mode.

Doc 022768 Rev 3 23/44

Digital interfaces A3G4250D

5.1.1 I

2

C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first 7 bits after a start condition with its address. If they match, the device considers itself addressed by the master.

The slave address (SAD) associated with the A3G4250D is 110100xb. The SDO pin can be used to modify the least significant bit (LSb) of the device address. If the SDO pin is connected to the voltage supply, LSb is ‘1’ (address 1101001b). Otherwise, when the SDO pin is connected to ground, the LSb value is ‘0’ (address 1101000b). This solution permits the connection and addressing of two different gyroscopes to the same I

2

C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I

2

C embedded in the A3G4250D behaves like a slave device, and the following protocol must be adhered to. After the START (ST) condition, a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address is transmitted. The 7 LSb represent the actual register address while the MSb enables address auto-increment. If the

MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow multiple data read/write.

The slave address is completed with a read/write bit. If the bit is ‘1’ (read), a REPEATED

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write) the master transmits to the slave with the direction unchanged.

Table 13

describes how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 13.

SAD+read/write patterns

Command SAD[6:1] SAD[0] = SDO

Read

Write

Read

Write

110100

110100

110100

110100

1

1

0

0

R/W

1

0

1

0

SAD+R/W

11010001 (D1h)

11010000 (D0h)

11010011 (D3h)

11010010 (D2h)

Table 14.

Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA

Slave SAK SAK SAK

SP

24/44 Doc 022768 Rev 3

A3G4250D Digital interfaces

Table 15.

Transfer when master is writing multiple bytes to slave

Master ST SAD + W SUB DATA DATA

Slave SAK SAK SAK SAK

SP

Table 16.

Transfer when master is receiving (reading) one byte of data from slave

Master ST SAD + W SUB SR SAD + R NMAK SP

Slave SAK SAK SAK DATA

Table 17.

Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA DATA DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit

(MSb) first. If a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e., it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1, while SUB(6-0) represents the address of the first register to be read.

In the presented communication format, MAK is “master acknowledge” and NMAK is “no master acknowledge”.

5.2 SPI interface

The SPI is a bus slave. The SPI allows writing and reading of the device registers. The serial interface interacts with the external world through 4 wires: CS, SPC, SDI, and SDO .

Doc 022768 Rev 3 25/44

Digital interfaces A3G4250D

Figure 12.

Read and write protocol

CS

SPC

SDI

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. These lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .

Both the read register and write register commands are completed in 16 clock pulses, or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, etc.) starts at the last falling edge of SPC just before the rising edge of CS .

Bit 0 : RW bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip drives SDO at the start of bit 8.

Bit 1 : MS bit. When 0, the address remains unchanged in multiple read/write commands.

When 1, the address is auto-incremented in multiple read/write commands.

Bit 2-7 : address AD(5:0). This is the address field of the indexed register.

Bit 8-15 : data DI(7:0) (write mode). This is the data that is written to the device (MSb first).

Bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands, further blocks of 8 clock periods are added. When the MS bit is 0, the address used to read/write data remains the same for every block. When the MS bit is 1, the address used to read/write data is incremented at every block.

The function and the behavior of SDI and SDO remain unchanged.

Figure 13.

SPI read protocol

CS

SPC

SDI

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

26/44 Doc 022768 Rev 3

A3G4250D Digital interfaces

The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.

Bit 0 : READ bit. The value is 1.

Bit 1 : MS bit. When 0, do not increment address; when 1, increment address in multiple reading.

Bit 2-7 : address AD(5:0). This is the address field of the indexed register.

Bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

Bit 16-...

: data DO(...-8). Further data in multiple byte reading.

Figure 14.

Multiple byte SPI read protocol (2-byte example)

CS

SPC

SDI

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 15.

SPI write protocol

CS

SPC

SDI

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

Bit 0 : WRITE bit. The value is 0.

Bit 1 : MS bit. When 0, do not increment address; when 1, increment address in multiple writing.

Bit 2 -7 : address AD(5:0). This is the address field of the indexed register.

Bit 8-15 : data DI(7:0) (write mode). This is the data that is written to the device (MSb first).

Bit 16-...

: data DI(...-8). Further data in multiple byte writing.

Doc 022768 Rev 3 27/44

Digital interfaces

Figure 16.

Multiple byte SPI write protocol (2-byte example)

CS

SPC

SDI

A3G4250D

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8

5.2.3

Note:

SPI read in 3-wire mode

3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit to 1 in

CTRL_REG2.

Figure 17.

SPI read protocol in 3-wire mode

CS

SPC

SDI/O

RW

MS AD5 AD4 AD3 AD2 AD1 AD0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

The SPI read command is performed with 16 clock pulses:

Bit 0 : READ bit. The value is 1.

Bit 1 : MS bit. When 0, do not increment address; when 1, increment address in multiple reading.

Bit 2-7 : address AD(5:0). This is the address field of the indexed register.

Bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

The multiple read command is also available in 3-wire mode.

If the A3G4250D is used in a multi-SPI slave environment (several devices sharing the same SPI bus), the accelerometer can be forced by software to remain in SPI mode. This objective can be achieved by sending, at the beginning of the SPI communication, the following sequence to the device: a = read(0x05) write(0x05, (0x20 OR a))

The programming of this register makes it possible to enhance the robustness of the SPI system.

28/44 Doc 022768 Rev 3

A3G4250D

6 Output register mapping

Output register mapping

Table 18

below provides a listing of the 8-bit registers embedded in the device and the related addresses:

Table 18.

Register address map

Name

Reserved

WHO_AM_I

Reserved

CTRL_REG1

CTRL_REG2

CTRL_REG3

CTRL_REG4

CTRL_REG5

REFERENCE

OUT_TEMP

STATUS_REG

OUT_X_L

OUT_X_H

OUT_Y_L

OUT_Y_H

OUT_Z_L

OUT_Z_H

FIFO_CTRL_REG

FIFO_SRC_REG

INT1_CFG

INT1_SRC

INT1_TSH_XH

INT1_TSH_XL

INT1_TSH_YH

INT1_TSH_YL

INT1_TSH_ZH

INT1_TSH_ZL

INT1_DURATION

Type r rw r rw r rw r r r r r r rw rw rw rw rw rw rw rw rw rw rw r

-

r rw

Register address

Default

Binary

-

000 1111 11010011

-

010 0000 00000111

010 0001 00000000

010 0010 00000000

010 0011 00000000

010 0100 00000000

010 0101 00000000

010 0110 Output

010 0111 Output

010 1000 Output

010 1001 Output

010 1010 Output

010 1011 Output

010 1100 Output

010 1101 Output

010 1110 00000000

010 1111 Output

011 0000 00000000

011 0001 Output

011 0010 00000000

011 0011 00000000

011 0100 00000000

011 0101 00000000

011 0110 00000000

011 0111 00000000

011 1000 00000000

Hex

2D

2E

2F

30

31

32

27

28

29

2A

2B

2C

33

34

35

36

37

38

21

22

23

24

25

26

00-0E

0F

10-1F

20

Comment

Doc 022768 Rev 3 29/44

Output register mapping A3G4250D

Registers marked as Reserved must not be changed. Writing to those registers may change calibration data and therefore lead to a non-proper working device.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.

30/44 Doc 022768 Rev 3

A3G4250D Register description

The device contains a set of registers which are used to control its behavior and to retrieve rate data. The register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface.

Table 19.

WHO_AM_I register

1 1 0

Device identification register.

1 0 0 1 1

Table 20.

CTRL_REG1 register

DR1 DR0 BW1 BW0 PD Zen

Table 21.

CTRL_REG1 description

DR1-DR0 Output data rate selection. Refer to

Table 22

BW1-BW0

PD

Zen

Yen

Xen

Bandwidth selection. Refer to Table 22

Power-down mode enable. Default value: 0

(0: power-down mode, 1: normal mode or sleep mode)

Z-axis enable. Default value: 1

(0: Z-axis disabled; 1: Z-axis enabled)

Y-axis enable. Default value: 1

(0: Y-axis disabled; 1: Y-axis enabled)

X-axis enable. Default value: 1

(0: X-axis disabled; 1: X-axis enabled)

Yen Xen

DR<1:0> is used to set ODR selection. BW <1:0> is used to set Bandwidth selection.

In the following table (

Table 22 ) all frequencies resulting in a combination of DR / BW bits

are reported.

Table 22.

DR and BW configuration setting

DR <1:0> BW <1:0>

00

00

00

00

00

01

10

11

100

100

100

100

ODR [Hz]

12.5

25

25

25

Cut-off

Doc 022768 Rev 3 31/44

Register description

Table 22.

DR and BW configuration setting (continued)

DR <1:0> BW <1:0> ODR [Hz]

01

10

10

01

01

01

10

10

11

11

11

11

11

00

01

00

01

10

10

11

00

01

10

11

200

200

200

200

400

400

400

400

800

800

800

800

70

20

25

12.5

25

50

50

110

30

35

50

110

A3G4250D

Cut-off

Combination of PD, Zen, Yen, and Xen are used to set the device in different modes

(power-down / normal / sleep mode) according to the following table.

Table 23.

Power mode selection configuration

Mode PD Zen

Power-down 0

Sleep 1

Normal 1 -

-

0

-

-

0

Yen

-

-

0

Xen

32/44

Table 24.

CTRL_REG2 register

0 (1)

0

(1)

HPM1 HPM1

1.

Value loaded at boot. This value must not be changed.

HPCF3

Table 25.

CTRL_REG2 description

HPM1-

HPM0

High-pass filter mode selection. Default value: 00

Refer to

Table 26

HPCF3-

HPCF0

High-pass filter cut-off frequency selection

Refer to

Table 28

HPCF2 HPCF1

Table 26.

High-pass filter mode configuration

HPM1 HPM0 High-pass filter mode

0 0 Normal mode (reset reading HP_RESET_FILTER)

Doc 022768 Rev 3

HPCF0

A3G4250D Register description

Table 26.

High-pass filter mode configuration

0 1 Reference signal for filtering

1

1

0

1

Normal mode

Auto-reset on interrupt event

Table 27.

High-pass filter cut-off frequency configuration [Hz]

HPCF3 ODR= 100 Hz ODR= 200 Hz ODR= 400 Hz

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

8

4

2

1

0.5

0.2

0.1

0.05

0.02

0.01

15

8

4

2

1

0.5

0.2

0.1

0.05

0.02

30

15

8

4

2

1

0.5

0.2

0.1

0.05

ODR= 800 Hz

56

30

4

2

1

15

8

0.5

0.2

0.1

Table 28.

CTRL_REG1 register

I1_Int1 I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty

Table 29.

CTRL_REG3 description

I1_Int1 Interrupt enable on the INT1 pin. Default value 0. (0: disable; 1: enable)

I1_Boot

H_Lactive

Boot status available on INT1. Default value 0. (0: disable; 1: enable)

Interrupt active configuration on INT1. Default value 0. (0: high; 1: low)

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

Push-pull / open drain. Default value: 0. (0: push-pull; 1: open drain)

Date ready on DRDY/INT2. Default value 0. (0: disable; 1: enable)

FIFO watermark interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)

FIFO overrun interrupt on DRDY/INT2 Default value: 0. (0: disable; 1: enable)

FIFO empty interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)

Table 30.

CTRL_REG4 register

0 BLE 0 0

Doc 022768 Rev 3

ST1 ST0 SIM

33/44

Register description

Table 31.

CTRL_REG4 description

BLE Big/little endian data selection. Default value 0.

(0: data LSB @ lower address; 1: data MSB @ lower address)

ST1-ST0 Self-test enable. Default value: 00

(00: self-test disabled; Other: see

Table )

SIM SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 32.

Self-test mode configuration

ST1 ST0

0

0

1

1

0

1

0

1

1.

DST sign (absolute value in

Table 4

).

Normal mode

Self-test 0 (+)

(1)

--

Self-test 1 (-)

(1)

Self-test mode

A3G4250D

Table 33.

CTRL_REG5 register

BOOT FIFO_EN -HPen INT1_Sel1 INT1_Sel0 Out_Sel1 Out_Sel0

Table 34.

CTRL_REG5 description

BOOT Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO_EN

HPen

INT1_Sel1-

INT1_Sel0

Out_Sel1-

Out_Sel1

FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO enable)

High-pass filter enable. Default value: 0

(0: HPF disabled; 1: HPF enabled (see

Figure 19 )

INT1 selection configuration. Default value: 0

(see Figure 19 )

Out selection configuration. Default value: 0

(see Figure 19 )

34/44 Doc 022768 Rev 3

A3G4250D Register description

Figure 18.

INT1_Sel and Out_Sel configuration block diagram

O u t_ S el <1:0>

00

01

D a t a Reg

0

LPF2

10

11

FIFO

3 2x16x 3

ADC LPF1 HPF

1

HPen

10

11

INT1_ S el <1:0>

01

00

Interr u pt gener a tor

AM07949V2

Table 35.

Out_Sel configuration settings

Hpen OUT_SEL1 OUT_SEL0 x x

0

1

0

0

1

1

0

1 x x

Description

Data in DataReg and FIFO are non-highpass-filtered

Data in DataReg and FIFO are high-passfiltered

Data in DataReg and FIFO are low-passfiltered by LPF2

Data in DataReg and FIFO are high-pass and low-pass-filtered by LPF2

Table 36.

INT_SEL configuration settings

Hpen INT_SEL1 INT_SEL2 x x

0

1

0

0

1

1

0

1 x x

Description

Non-high-pass-filtered data are used for interrupt generation

High-pass-filtered data are used for interrupt generation

Low-pass-filtered data are used for interrupt generation

High-pass and low-pass-filtered data are used for interrupt generation

Doc 022768 Rev 3 35/44

Register description A3G4250D

Table 37.

REFERENCE register

Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1

Table 38.

REFERENCE register description

Ref 7-Ref0 Reference value for interrupt generation. Default value: 0

Ref0

Table 39.

OUT_TEMP register

Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1

Table 40.

OUT_TEMP register description

Temp7-Temp0 Temperature data.

Temp0

36/44

Table 41.

STATUS_REG register

ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

Table 42.

STATUS_REG description

ZYXOR

X, Y, Z-axis data overrun. Default value: 0

(0: no overrun has occurred; 1: new data has overwritten the previous one before it was read)

ZOR

YOR

Z-axis data overrun. Default value: 0

(0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one)

Y-axis data overrun. Default value: 0

(0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one)

XOR

X-axis data overrun. Default value: 0

(0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one)

ZYXDA X, Y, Z-axis new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

ZDA

YDA

XDA

Z-axis new data available. Default value: 0

(0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available)

Y-axis new data available. Default value: 0

(0: a new data for the Y-axis is not yet available;1: a new data for the Y-axis is available)

X-axis new data available. Default value: 0

(0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available)

Doc 022768 Rev 3

A3G4250D

7.10 OUT_X_L (28h), OUT_X_H (29h)

X-axis angular rate data. The value is expressed as 2’s complement.

Register description

7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh)

Y-axis angular rate data. The value is expressed as 2’s complement.

7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh)

Z-axis angular rate data. The value is expressed as 2’s complement.

Table 43.

REFERENCE register

FM2 FM1 FM0 WTM4 WTM3

Table 44.

REFERENCE register description

FM2-FM0 FIFO mode selection. Default value: 00

WTM4-WTM0 FIFO threshold. Watermark level setting

WTM2 WTM1 WTM0

0

0

0

Table 45.

FIFO mode configuration

FM2 FM1 FM0

0

0

1

0

1

0

Bypass mode

FIFO mode

Stream mode

FIFO mode

Table 46.

FIFO_SRC register

WTM OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0

Table 47.

FIFO_SRC register description

WTM Watermark status. (0: FIFO filling is lower than WTM level; 1: FIFO filling is equal or higher than WTM level)

OVRN Overrun bit status.

(0: FIFO is not completely filled; 1: FIFO is completely filled)

Doc 022768 Rev 3 37/44

Register description

Table 47.

FIFO_SRC register description (continued)

EMPTY FIFO empty bit.

(0: FIFO not empty; 1: FIFO empty)

FSS4-FSS1 FIFO stored data level

A3G4250D

Table 48.

INT1_CFG register

AND/OR LIR ZHIE ZLIE YHIE YLIE XHIE XLIE

Table 49.

INT1_CFG description

AND/OR

AND/OR combination of interrupt events. Default value: 0

(0: OR combination of interrupt events 1: AND combination of interrupt events

LIR

ZHIE

ZLIE

YHIE

YLIE

XHIE

XLIE

Latch interrupt request. Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

Cleared by reading the INT1_SRC reg.

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value higher than preset threshold)

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value lower than preset threshold)

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value higher than preset threshold)

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value lower than preset threshold)

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value higher than preset threshold)

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request; 1: enable interrupt request on measured rate value lower than preset threshold)

Configuration register for interrupt source.

Table 50.

INT1_SRC register

0 IA ZH ZL YH YL XH XL

38/44 Doc 022768 Rev 3

A3G4250D Register description

ZL

YH

YL

XH

XL

Table 51.

INT1_SRC description

IA

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

ZH Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0 (0: no interrupt, 1: X high event has occurred)

X low. Default value: 0 (0: no interrupt, 1: X low event has occurred)

Interrupt source register. Read only register.

Reading at this address clears the INT1_SRC IA bit (and eventually the interrupt signal on the INT1 pin) and allows the refreshment of data in the INT1_SRC register if the latched option is chosen.

Table 52.

INT1_THS_XH register

THSX14 THSX13 THSX12 THSX11 THSX10 THSX9 THSX8

Table 53.

INT1_THS_XH description

THSX14 - THSX9 Interrupt threshold. Default value: 0000 0000

Table 54.

INT1_THS_XL register

THSX7 THSX6 THSX5 THSX4 THSX3 THSX2

Table 55.

INT1_THS_XL description

THSX7 - THSX0 Interrupt threshold. Default value: 0000 0000

THSX1 THSX0

Table 56.

INT1_THS_YH register

THSY14 THSY13 THSY12 THSY11 THSY10 THSY9 THSY8

Table 57.

INT1_THS_YH description

THSY14 - THSY9 Interrupt threshold. Default value: 0000 0000

Doc 022768 Rev 3 39/44

Register description A3G4250D

Table 58.

INT1_THS_YL register

THSR7 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0

Table 59.

INT1_THS_YL description

THSY7 - THSY0 Interrupt threshold. Default value: 0000 0000

Table 60.

INT1_THS_ZH register

THSZ14 THSZ13 THSZ12 THSZ11 THSZ10 THSZ9 THSZ8

Table 61.

INT1_THS_ZH description

THSZ14 - THSZ9 Interrupt threshold. Default value: 0000 0000

Table 62.

INT1_THS_ZL register

THSZ7 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0

Table 63.

INT1_THS_ZL description

THSZ7 - THSZ0 Interrupt threshold. Default value: 0000 0000

40/44

Table 64.

INT1_DURATION register

WAIT D6 D5 D4 D3 D2 D1 D0

Table 65.

INT1_DURATION description

WAIT WAIT enable. Default value: 0 (0: disable; 1: enable)

D6 - D0 Duration value. Default value: 000 0000

D6 - D0 bits set the minimum duration of the interrupt event to be recognized. Duration steps and maximum values depend on the ODR chosen.

WAIT bit has the following meaning:

Wait =’0’: the interrupt falls immediately if signal crosses the selected threshold.

Doc 022768 Rev 3

A3G4250D Register description

Wait =’1’: if signal crosses the selected threshold, the interrupt falls only after the duration has counted a number of samples at the selected data rate, written into the duration counter register.

Figure 19.

Wait disabled

Figure 20.

Wait enabled

Doc 022768 Rev 3 41/44

Package information A3G4250D

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com.

ECOPACK is an ST trademark.

Figure 21.

LGA-16: mechanical data and package dimensions

Dimen s ion s

N2

P1

P2

T1

T2 k

D1

E1

L2

M

N1

A1

A2

A 3 d

1.100

3 .

8 50

3 .

8 50

0.975

1.750

1.525

0.400

0.

3 00

0.050

0.

8 55

0.200

0.

3 00

4.000

4.000

1.950

0.100

0.650

4.150

4.150

LGA-16 (4x4x1.1 mm

Land Grid Array Packa

3 g

) e

42/44 Doc 022768 Rev 3

A3G4250D Revision history

Table 66.

Document revision history

Date

02-Feb-2012

08-Feb-2012

14-Feb-2012

Revision

1

2

3

Changes

Initial release.

Updated notes in Table 4: Mechanical characteristics

.

Updated Figure 21: LGA-16: mechanical data and package dimensions .

Doc 022768 Rev 3 43/44

A3G4250D

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

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