STMicroelectronics LSM6DS1 Datasheet

LSM6DS1

LGA-16L (3x3x0.86 mm)

Features

 Analog supply voltage: 1.71 V to 3.6 V

 Independent IOs supply (1.71 V)

 “Always on” eco power mode down to 1.8 mA

 3 independent acceleration channels and 3 angular rate channels

 ±2/±4/±8 g full scale

 ±245/±500/±2000 dps full scale

 SPI/I

2

C serial interface

 Embedded temperature sensor

 Embedded FIFO

 Embedded sensor hub

 ECOPACK

®

, RoHS and “Green” compliant

iNEMO inertial module:

3D accelerometer and 3D gyroscope

Datasheet

-

preliminary data

Description

The LSM6DS1 is a system-in-package featuring a

3D digital accelerometer and a 3D digital gyroscope. ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes.

The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using

CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics.

The LSM6DS1 has a full-scale acceleration range of ±2/±4/±8 g and an angular rate range of

±245/±500/±2000 dps. The LSM6DS1 has two operating modes in that the accelerometer and gyroscope sensors can be either activated at the same ODR or the accelerometer can be enabled while the gyroscope is in power-down.

The LSM6DS1 is available in a plastic land grid array (LGA) package.

Applications

 GPS navigation systems

 Impact recognition and logging

Table 1. Device summary

Part number

Temp. range [°C]

Package Packing

LSM6DS1 -40 to +85

LSM6DS1TR -40 to +85

LGA-16L

(3x3x0.86 mm)

Tray

Tape and reel

 Motion-activated functions

 Intelligent power saving for handheld devices

 Vibration monitoring and compensation

 Free-fall detection

 6D orientation detection

November 2014 DocID025605 Rev 3

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/80 www.st.com

LSM6DS1 Contents

Contents

1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.1

Recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4

Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.1

2.4.2

SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

I 2

C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.6.1

2.6.2

Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Zero-g and zero rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2

Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3

Multiple reads (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4

Digital block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5

FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.5.1

3.5.2

3.5.3

Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.5.4

Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.6

3.5.5

Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Obsolete Product(s) - Obsolete Product(s)

3.6.1

Sensor hub description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.6.2

Sensor hub block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.7

Embedded functionalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1

I

2

C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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LSM6DS1 Contents

4.1.1

I 2

C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2

SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.1

4.2.2

4.2.3

SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.1

INT_GEN_CFG2_XL (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.2

INT_GEN_THS2_XL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.3

INT_GEN_DUR2_XL (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.4

ACT_THS (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.5

ACT_DUR (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.6

INT_GEN_CFG1_XL (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.7

INT_GEN_THS1_X_XL (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.8

INT_GEN_THS1_Y_XL (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.9

INT_GEN_THS1_Z_XL (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.10

INT_GEN_DUR1_XL (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.11

REFERENCE_G (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.12

INT1_CTRL (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.13

INT2_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.14

WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.15

CTRL_REG1_G (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.16

CTRL_REG2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.17

CTRL_REG3_G (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.18

ORIENT_CFG_G (13h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.20

OUT_TEMP_L (15h), OUT_TEMP_H (16h) . . . . . . . . . . . . . . . . . . . . . . . 51

6.21

STATUS_REG (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.22

OUT_X_G (18h - 19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.23

OUT_Y_G (1Ah - 1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.24

OUT_Z_G (1Ch - 1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.25

CTRL_REG4 (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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Contents LSM6DS1

6.26

CTRL_REG5_XL (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.27

CTRL_REG6_XL (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.28

CTRL_REG7_XL (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.29

CTRL_REG8 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.30

CTRL_REG9 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.31

CTRL_REG10 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.32

INT2_GEN_SRC_XL (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.33

INT1_GEN_SRC_XL (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.34

STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.35

OUT_X_XL (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.36

OUT_Y_XL (2Ah - 2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.37

OUT_Z_XL (2Ch - 2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.38

FIFO_CTRL (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.39

FIFO_SRC (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.40

INT_GEN_CFG_G (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.41

INT_GEN_THS_X_G (31h - 32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.42

INT_GEN_THS_Y_G (33h - 34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.43

INT_GEN_THS_Z_G (35h - 36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.44

INT_GEN_DUR_G (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.45

EXTERNAL_SENSORS_DATA (80h-8Fh) . . . . . . . . . . . . . . . . . . . . . . . . 64

6.46

MASTER_SYNC_REG (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.47

MASTER_FSM_REG (91h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.48

MASTER_STATUS_REG (97h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.49

SLAVE0_I2C_ADD (B0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.50

SLAVE0_SUB_ADD (B1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.51

SLAVE0_DATA_TO_WRITE (B5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.53

SLAVE0_BYTE_TO_READ (B7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.54

SLAVE1_I2C_ADD (B8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.55

SLAVE1_SUB_ADD (B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.56

SLAVE1_DATA_TO_WRITE (BAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.57

SLAVE1_CONFIG (BBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.58

SLAVE1_BYTE_TO_READ (BCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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7

8

9

LSM6DS1 Contents

6.59

SLAVE2_I2C_ADD (BDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.60

SLAVE2_SUB_ADD (BEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.61

SLAVE2_DATA_TO_WRITE (BFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.62

SLAVE2_CONFIG (C0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.63

SLAVE2_BYTE_TO_READ (C1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.64

MAGNETOMETER_ROUTINES (C2h) . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.65

GYRO_OFS_XY_ON_OUT (C9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.66

MAG_CFG (CAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.67

PITCH_ANGLE_L/PITCH_ANGLE_H (CCh, CDh) . . . . . . . . . . . . . . . . . 75

6.68

ROLL_ANGLE_L/ROLL_ANGLE_H (CEh, CFh) . . . . . . . . . . . . . . . . . . . 75

6.69

GYRO_OFS_PITCH_DATA_L/GYRO_OFS_PITCH_DATA_H (D0h, D1h) .

76

6.70

GYRO_OFS_ROLL_DATA_L/GYRO_OFS_ROLL_DATA_H (D2h, D3h) 76

6.71

HEADING_DATA_L/HEADING_DATA_H (D4h, D5h) . . . . . . . . . . . . . . . 76

Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Obsolete Product(s) - Obsolete Product(s)

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LSM6DS1 List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

I

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2

C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Gyroscope operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10.

Operating mode current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11.

Accelerometer turn-on time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12.

Gyroscope turn-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13.

Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14.

I

2

C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15.

SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16.

Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 17.

Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18.

Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 33

Table 19.

Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 33

Table 20.

Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 21.

INT_GEN_CFG2_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 22.

INT_GEN_CFG2_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 23.

INT_GEN_THS2_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 24.

INT_GEN_THS2_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 25.

INT_GEN_DUR2_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 26.

INT_GEN_DUR2_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 27.

ACT_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 28.

ACT_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 29.

ACT_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 30.

ACT_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 31.

INT_GEN_CFG1_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 32.

INT_GEN_CFG1_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 33.

INT_GEN_THS1_X_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 34.

INT_GEN_THS1_X_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 35.

INT_GEN_THS1_Y_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 36.

INT_GEN_THS1_Y_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 37.

INT_GEN_THS1_Z_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 38.

INT_GEN_THS1_Z_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Obsolete Product(s) - Obsolete Product(s)

Table 40.

INT_GEN_DUR1_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 41.

REFERENCE_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 42.

REFERENCE_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 43.

INT1_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 44.

INT1_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 45.

INT2_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 46.

INT2_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 47.

WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 48.

CTRL_REG1_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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LSM6DS1 List of tables

Table 49.

CTRL_REG1_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 50.

ODR and BW configuration setting (after LPF1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 51.

ODR and BW configuration setting (after LPF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 52.

CTRL_REG2_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 53.

CTRL_REG2_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 54.

CTRL_REG3_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 55.

CTRL_REG3_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 56.

Gyroscope high-pass filter cutoff frequency configuration [Hz]. . . . . . . . . . . . . . . . . . . . . . 50

Table 57.

ORIENT_CFG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 58.

ORIENT_CFG_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 59.

INT_GEN_SRC_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 60.

INT_GEN_SRC_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 61.

OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 62.

OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 63.

OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 64.

STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 65.

STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 66.

CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 67.

CTRL_REG4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 68.

CTRL_REG5_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 69.

CTRL_REG5_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 70.

CTRL_REG6_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 71.

CTRL_REG6_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 72.

ODR register setting (accelerometer only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 73.

CTRL_REG7_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 74.

CTRL_REG7_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 75.

Low-pass cutoff frequency in high resolution mode (HR = 1) . . . . . . . . . . . . . . . . . . . . . . . 55

Table 76.

CTRL_REG8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 77.

CTRL_REG8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 78.

CTRL_REG9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 79.

CTRL_REG9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 80.

CTRL_REG10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 81.

CTRL_REG10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 82.

INT2_GEN_SRC_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 83.

INT2_GEN_SRC_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 84.

INT1_GEN_SRC_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 85.

INT1_GEN_SRC_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 86.

STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 87.

STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 88.

FIFO_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 89.

FIFO_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 90.

FIFO mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Obsolete Product(s) - Obsolete Product(s)

Table 92.

FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 93.

FIFO_SRC example: OVR/FSS details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 94.

INT_GEN_CFG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 95.

INT_GEN_CFG_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 96.

INT_GEN_THS_XH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 97.

INT_GEN_THS_XL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 98.

INT_GEN_THS_X_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 99.

INT_GEN_THS_YH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 100. INT_GEN_THS_YL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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List of tables LSM6DS1

Table 101. INT_GEN_THS_Y_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 102. INT_GEN_THS_ZH_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 103. INT_GEN_THS_ZL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 104. INT_GEN_THS_Z_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 105. INT_GEN_DUR_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 106. INT_GEN_DUR_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 107. EXTERNAL_SENSORS_DATA register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 108. EXTERNAL_SENSORS_DATA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 109. MASTER_SYNC_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 110. MASTER_SYNC_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 111. Master trigger mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 112. Slave address writing mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 113. MASTER_FSM_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 114. MASTER_FSM_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 115. Master state machine type of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 116. MASTER _STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 117. MASTER _STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 118. SLAVE0_I2C_ADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 119. SLAVE0_I2C_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 120. SLAVE0_SUB_ADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 121. SLAVE0_SUB_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 122. SLAVE0_DATA_TO_WRITE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 123. SLAVE0_DATA_TO_WRITE register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 124. SLAVE0_CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 125. SLAVE0_CONFIG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 126. SLAVE0_BYTE_TO_READ register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 127. SLAVE0_BYTE_TO_READ register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 128. SLAVE1_I2C_ADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 129. SLAVE1_I2C_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 130. SLAVE1_SUB_ADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 131. SLAVE1_SUB_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 132. SLAVE1_DATA_TO_WRITE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 133. SLAVE1_DATA_TO_WRITE register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 134. SLAVE1_CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 135. SLAVE1_CONFIG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 136. SLAVE1_BYTE_TO_READ register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 137. SLAVE1_BYTE_TO_READ register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 138. SLAVE2_I2C_ADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 139. SLAVE2_I2C_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 140. SLAVE2_SUB_ADD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 141. SLAVE2_SUB_ADD register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 142. SLAVE2_DATA_TO_WRITE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Obsolete Product(s) - Obsolete Product(s)

Table 144. SLAVE2_CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 145. SLAVE2_CONFIG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 146. SLAVE2_BYTE_TO_READ register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 147. SLAVE2_BYTE_TO_READ register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 148. MAGNETOMETER_ROUTINES register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 149. MAGNETOMETER_ROUTINES register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 150. GYRO_OFS_XY_ON_OUT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 151. GYRO_OFS_XY_ON_OUT register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 152. Offset_Enable description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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Table 153. MAG_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 154. MAG_CFG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 155. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Obsolete Product(s) - Obsolete Product(s)

DocID025605 Rev 3 9/80

80

List of figures

List of figures

LSM6DS1

Figure 1.

Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2.

Recommended power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 3.

SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4.

I

2

C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5.

Switching operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6.

Multiple reads: accelerometer only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7.

Multiple reads: accelerometer and gyroscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8.

Digital block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9.

Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 10.

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11.

Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 12.

Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 13.

Bypass-to-Continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14.

LSM6DS1 sensor hub. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15.

Embedded functionalities- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16.

Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 17.

SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 18.

Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 19.

SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 20.

Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 21.

SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 22.

INT_SEL and OUT_SEL configuration gyroscope block diagram . . . . . . . . . . . . . . . . . . . 49

Figure 23.

Wait bit disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 24.

Wait bit enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 25.

LGA 3x3x0.86 16L package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Obsolete Product(s) - Obsolete Product(s)

10/80 DocID025605 Rev 3

LSM6DS1 Pin description

Figure 1. Pin connections

Z

+Ω

Z

X

Y

X

+Ω

Y

(TOP VIEW)

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

(TOP VIEW)

DIRECTIONS OF THE

DETECTABLE

ANGULAR RATES

GND

GND

RES

RES

RES

13

9

14 16

BOTTOM

VIEW

1

5

Vdd_IO

SCL_S/SPC

SDA_S/SDI/SDO

SDO/SA0

CS

8 6

+Ω

X

Obsolete Product(s) - Obsolete Product(s)

DocID025605 Rev 3 11/80

80

Pin description LSM6DS1

Pin#

1

2

3

4

5

9

10

11

12

6

7

8

13

14

15

16

Name

Vdd_IO

(1)

SCL_S

SPC

SDA_S

SDI

SDO

Table 2. Pin description

Function

Power supply for I/O pins

Slave I

2

C serial clock (SCL_S)

SPI serial port clock (SPC)

Slave I

2

C serial data (SDA_S)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

SDO

SA0

INT1

SDA_M

SPI serial data output (SDO)

I

2

C least significant bit of the device address (SA0)

CS

SPI enable

I

2

C/SPI mode selection (1: SPI idle mode / I

2

C communication enabled; 0: SPI communication mode / I

2

C disabled)

INT2/SCL_M Programmable interrupt (INT2)/ Master I

2

C serial clock (SCL_M)

Programmable interrupt

Master I

2

C serial data (SDA_M)

RES

RES

RES

GND

GND

Cap

TRIG_M

Vdd

(3)

Connect to GND

Connect to GND

Connect to Vdd or GND

0 V supply

0 V supply

Connect to GND with ceramic capacitor

(2)

External synchronization signal for master I

2

C

Power supply

1. Recommended 100 nF filter capacitor.

2. 10 nF (±10%), 16 V. 1 nF minimum value has to be guaranteed under 11 V bias condition.

3. Recommended 100 nF plus 10 μ F capacitors.

Obsolete Product(s) - Obsolete Product(s)

12/80 DocID025605 Rev 3

LSM6DS1 Module specifications

@ Vdd = 2.2 V, T = 25 °C unless otherwise noted

(a)

Symbol

Table 3. Mechanical characteristics

Parameter

Test conditions

Min.

Typ.

(1)

Max.

Unit

LA_FS

G_FS

LA_So

G_So

Linear acceleration measurement range

Angular rate measurement range

Linear acceleration sensitivity

Angular rate sensitivity

FS = ±2 g

FS = ±4 g

FS = ±8 g

FS = ±245 dps

FS = ±500 dps

FS = ±2000 dps

±2

±4

±8

±245

±500

±2000

0.061

0.122

0.244

8.75

17.50

70 g dps mg/LSb mdps/LSb

LA_TyOff

Linear acceleration typical zerog level offset accuracy

(2)

G_TyOff Angular rate typical zero-rate level

(3)

FS = ±8 g ±90 m g

FS = ±2000 dps ±30 dps

Gyro ON

952

476

238

119

59.5

14.9

Hz

LA_ODR Linear acceleration output data rate

952

476

238

Gyro OFF

119 Obsolete Product(s) - Obsolete Product(s)

10

Hz a. The product is factory calibrated at 2.2 V. The operational power supply range is from 1.71 V to 3.6 V.

DocID025605 Rev 3 13/80

80

Module specifications

Symbol

G_ODR

Table 3. Mechanical characteristics (continued)

Parameter

Test conditions

Min.

Typ.

(1)

Angular digital output data rate

952

476

238

119

59.5

14.9

Top Operating temperature range

1. Typical specifications are not guaranteed.

2. Typical zero-g level offset value after soldering.

3. Typical zero-rate level offset value after MSL3 preconditioning.

-40

Max.

+85

LSM6DS1

Unit

Hz

°C

Obsolete Product(s) - Obsolete Product(s)

14/80 DocID025605 Rev 3

LSM6DS1 Module specifications

@ Vdd = 2.2 V, T = 25 °C unless otherwise noted

Symbol Parameter

Table 4. Electrical characteristics

Test conditions Min.

Vdd

Vdd_IO

Supply voltage

Power supply for I/O

1.71

1.71

LA_Idd

Accelerometer current consumption in normal mode

ODR = 10 Hz

ODR = 50 Hz

ODR  119Hz

G_Idd

Top

Trise

Twait

Gyroscope current consumption in low-power mode

Operating temperature range

Time for power supply rising

(2)

Time delay between Vdd_IO and Vdd

(2)

-40

0.01

0

1. Typical specifications are not guaranteed.

2. Please refer to Section 2.2.1: Recommended power-up sequence for more details.

Typ.

(1)

60

160

330

1.8

2.2.1

Max.

3.6

Vdd + 0.1

+85

100

10

Unit

V

V

μ A mA

° C ms ms

Recommended power-up sequence

For the power-up sequence please refer to the following figure, where:

 Trise is the time for the power supply to rise from 10% to 90% of its final value

 Twait is the time delay between the end of the Vdd_IO ramp (90% of its final value) and the start of the Vdd ramp

Figure 2. Recommended power-up sequence

Trise

Vdd_IO

0V

Vdd

0V

Trise

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Module specifications LSM6DS1

2.3 Temperature sensor characteristics

@ Vdd = 2.2 V, T = 25 °C unless otherwise noted

(b)

Symbol

TODR

TSen

Top

Table 5. Temperature sensor characteristics

Parameter Test condition Min.

Typ.

(1)

Gyro off

(2)

Temperature refresh rate

50

Temperature Sensitivity

(3)

Gyro on 59.5

16

Operating temperature range -40

Max.

+85

1. Typical specifications are not guaranteed.

2. When the accelerometer ODR is set to 10Hz and the gyroscope part is turned off, the TODR value is 10 Hz.

3. The output of the temperature sensor is 0 (typ.) at 25 °C

Unit

Hz

LSB/°C

°C

Obsolete Product(s) - Obsolete Product(s)

16/80 b. The product is factory calibrated at 2.2 V.

DocID025605 Rev 3

LSM6DS1 Module specifications

2.4 Communication interface characteristics

2.4.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Table 6. SPI slave timing values

Value

(1)

Symbol Parameter Unit

Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)

SPI clock cycle

SPI clock frequency

CS setup time

CS hold time

SDI input setup time

SDI input hold time

SDO valid output time

SDO output hold time

SDO output disable time

100

5

20

5

15

5

10

50

50 ns

MHz ns

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production

Figure 3. SPI slave timing diagram

Obsolete Product(s) - Obsolete Product(s)

Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

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80

Module specifications LSM6DS1

2.4.2 I

2

C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Symbol Parameter

Table 7. I 2 C slave timing values

I

2

C standard mode

(1)

Min Max f

(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)

SCL clock frequency

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

START condition hold time

0

4.7

4.0

250

0

4

100

3.45

t su(SR)

Repeated START condition setup time

4.7

t su(SP)

STOP condition setup time 4 t w(SP:SR)

Bus free time between STOP and START condition

4.7

1. Data based on standard I 2 C protocol requirement, not tested in production.

Figure 4. I

2

C slave timing diagram

0.6

100

0

0.6

I

2

C fast mode

(1)

Min Max

0

1.3

400

0.9

0.6

0.6

1.3

REPEATED

START

START

Unit kHz

μ s ns

μ s

μ s t su(SR)

SDA_S t w(SP:SR)

START t su(SDA) t h(SDA) t su(SP)

STOP

SCL_S

Note: w(SCLH)

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

18/80 DocID025605 Rev 3

LSM6DS1

2.5

Note:

Module specifications

Absolute maximum ratings

Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 8. Absolute maximum ratings

Ratings

Vdd

T

STG

Sg

Supply voltage

Storage temperature range

Acceleration g for 0.1 ms

ESD Electrostatic discharge protection (HBM)

Vin

Input voltage on any control pin

(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)

Maximum value

-0.3 to 4.8

-40 to +125

10,000

2

0.3 to Vdd_IO +0.3

Supply voltage on any pin should never exceed 4.8 V.

This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.

This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.

Unit

V

°C g kV

V

Obsolete Product(s) - Obsolete Product(s)

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Module specifications LSM6DS1

2.6 Terminology

2.6.1 Sensitivity

Linear acceleration sensitivity can be determined for example by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors.

An angular rate gyroscope is device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time.

2.6.2 Zerog and zero rate level

Linear acceleration zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g . Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zerog offset.

Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zerog level change vs. temperature” in

Table 3 . The zero-

g level tolerance

(TyOff) describes the standard deviation of the range of zerog levels of a group of sensors.

The zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time.

Obsolete Product(s) - Obsolete Product(s)

20/80 DocID025605 Rev 3

LSM6DS1

3 Functionality

Functionality

The LSM6DS1 has two operating modes available: only accelerometer active and gyroscope in power-down or both accelerometer and gyroscope sensors active at the same

ODR. Switching from one mode to the other requires one write operation: writing to

CTRL_REG6_XL (20h) , the accelerometer operates in normal mode and the gyroscope is

powered down, writing to

CTRL_REG1_G (10h) both the accelerometer and gyroscope are

activated at the same ODR.

Figure 5 depicts both modes of operation from power down.

Figure 5. Switching operating modes

Accelerometer

Only

Write CTRL_REG6_XL Write CTRL_REG1_G

Power Down

Write CTRL_REG1_G

With CTRL_REG6_XL = PD

Accelerometer

+

Gyro

3.2 Gyroscope power modes

In LSM6DS1, the gyroscope can be configured in three different operating modes: powerdown, low-power and normal mode.

Low-power mode is available for lower ODR (14.9, 59.5, 119 Hz) while for greater ODR

(238, 476, 952 Hz) the device is automatically in normal mode. In

Table 9 summarizes the

ODR configuration (ODR_G[2:0] bits set in

CTRL_REG1_G (10h) ) and corresponding

power modes.

Low-power mode allows reaching low power consumption while maintaining the device

always on, refer to Table 10

.

DocID025605 Rev 3 21/80

80

Functionality

ODR_G [2:0]

Table 9. Gyroscope operating mode

ODR [Hz]

000

001

010

011

Power-down

14.9

59.5

119

100

101

238

476

110 952

1. Gyroscope low-power mode is available for G_FS= ± 2000 dps.

Power mode

(1)

Power-down

Low-power/Normal mode

Low-power/Normal mode

Low-power/Normal mode

Normal mode

Normal mode

Normal mode

LSM6DS1

ODR [Hz]

Table 10. Operating mode current consumption

Power mode

Current consumption

(1)

[mA]

14.9

59.5

119

238

476

952

Low-power

Low-power

Low-power

Normal mode

Normal mode

Normal mode

1.8

2.3

2.9

4.3

4.3

4.3

1. Typical values of gyroscope and accelerometer current consumption based on characterization data.

ODR [Hz]

Table 11. Accelerometer turn-on time

BW = 400 Hz

(1)

BW = 200 Hz

(1)

BW = 100 Hz

(1)

BW = 50 Hz

(1)

14.9

59.5

119

0

0

1

0

0

1

0

0

1

0

0

2

238

476

1

1

1

2

2

4

4

7

952 2 4 7 14

1. The table contains the number of samples to be discarded after switching between power-down mode and normal mode.

22/80 DocID025605 Rev 3

LSM6DS1

3.3

Functionality

ODR [Hz]

Table 12. Gyroscope turn-on time

LPF1 only

(1)

LPF1 and LPF2

(1)

14.9

59.5 or 119

238

476

952

2

3

4

5

8

LPF2 not available

13

14

15

18

1. The table contains the number of samples to be discarded after switching between low-power mode and normal mode.

Multiple reads (burst)

When only the accelerometer is activated and the gyroscope is in power down, starting from

OUT_X_XL (28h - 29h) multiple reads can be performed. Once OUT_Z_XL (2Ch - 2Dh) is

read, the system automatically restarts from

OUT_X_XL (28h - 29h) (see

Figure 6 ).

Figure 6. Multiple reads: accelerometer only x,y,z

Read #1 OUT_TEMP

(15-16)

OUT_X_XL

(28-29)

OUT_Y_XL

(2A-2B)

OUT_Z_XL

(2C-2D) x,y,z

Read #n

OUT_X_XL

(28-29)

OUT_Y_XL

(2A-2B)

OUT_Z_XL

(2C-2D)

When both the accelerometer and gyroscope sensors are activated at the same ODR,

starting from OUT_X_G (18h - 19h) multiple reads can be performed. Once

OUT_Z_XL

(2Ch - 2Dh)

is read, the system automatically restarts from

OUT_X_G (18h - 19h)

(see

Figure 7 ).

Figure 7. Multiple reads: accelerometer and gyroscope x,y,z

OUT_TEMP Read #1

Read #n

(15-16)

OUT_X_G

(18-19)

OUT_Y_G

(1A-1B)

OUT_X_XL

(28-29)

OUT_Y_XL

(2A-2B)

OUT_Z_XL

(2C-2D) Obsolete Product(s) - Obsolete Product(s) x,y,z

OUT_Z_G

(1C-1D)

OUT_X_G OUT_Y_G OUT_Z_G OUT_X_XL OUT_Y_XL OUT_Z_XL

(18-19) (1A-1B) (2A-2B) (1C-1D) (28-29) (2C-2D)

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80

Functionality

3.4 Digital block diagram

Figure 8. Digital block diagram

LPF1 ADC

XL XL

ADC

Gyro

LPF1

Gyro

LPF2

XL

HPF

XL

HR

0

1

HPIS1

0

Interrupt

Generator

XL

1

0

1

FDS

OUT_SEL Data Reg

FIFO

HPF

Gyro

0

1

HP_EN

LPF2

Gyro

INT_SEL

SRC Registers

CFG Registers

Interrupt

Generator

Gyro

LSM6DS1

I2C

SPI

Obsolete Product(s) - Obsolete Product(s)

24/80 DocID025605 Rev 3

LSM6DS1 Functionality

3.5 FIFO

The LSM6DS1 embeds 32 slots of 16-bit data FIFO for each of the gyroscope’s three output channels, yaw, pitch and roll, and 16-bit data FIFO for each of the accelerometer’s three output channels, X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to five different modes: Bypass mode, FIFO mode, Continuous mode,

Continuous-to-FIFO mode and Bypass-to-Continuous. Each mode is selected by the

FMODE [2:0] bits in the

FIFO_CTRL (2Eh)

register. Programmable FIFO threshold status,

FIFO overrun events and the number of unread samples stored are available in the

FIFO_SRC (2Fh)

register and can be set to generate dedicated interrupts on the INT1 pin

using the INT1_CTRL (0Ch)

register.

FIFO_SRC (2Fh)

(FTH) goes to '1' when the number of unread samples (

FIFO_SRC (2Fh)

(FSS5:0)) is greater than or equal to FTH [4:0] in

FIFO_CTRL (2Eh) . If FIFO_CTRL (2Eh)

(FTH[4:0]) is equal to 0,

FIFO_SRC (2Fh) (FTH) goes to ‘0’.

FIFO_SRC (2Fh)

(OVRN) is equal to '1' if a FIFO slot is overwritten.

FIFO_SRC (2Fh) (FSS [5:0]) contains stored data levels of unread samples. When FSS [5:0]

is equal to ‘000000’, FIFO is empty. When FSS [5:0] is equal to ‘100000’, FIFO is full and the unread samples are 32.

The FIFO feature is enabled by writing '1' in CTRL_REG9 (23h)

(FIFO_EN).

To guarantee the correct acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded.

In Bypass mode (

FIFO_CTRL (2Eh) (FMODE [2:0]= 000), the FIFO is not operational and it

remains empty.

Bypass mode is also used to reset the FIFO when in FIFO mode.

As described in

Figure 9 , for each channel only the first address is used. When a new data

is available, the old data is overwritten.

Figure 9. Bypass mode x i

,y i

,z i x

0 y

0 z

0 x

1 y

1 Obsolete Product(s) - Obsolete Product(s) x y empty

2 2 z

1 z

2 x

31 y

31 z

31

DocID025605 Rev 3 25/80

80

Functionality LSM6DS1

In FIFO mode (

FIFO_CTRL (2Eh)

(FMODE [2:0] = 001) data from the output channels are stored in the FIFO until it is overwritten.

To reset FIFO content, Bypass mode should be selected by writing

FIFO_CTRL (2Eh)

(FMODE [2:0]) to '000'. After this reset command, it is possible to restart FIFO mode writing,

FIFO_CTRL (2Eh) (FMODE [2:0]) to '001'.

The FIFO buffer memorizes 32 levels of data, but the depth of the FIFO can be resized by setting the STOP_ON_FTH bit in

CTRL_REG9 (23h) . If the STOP_ON_FTH bit is set to '1',

FIFO depth is limited to FIFO_CTRL (2Eh) (FTH [4:0]) + 1 data.

A FIFO threshold interrupt can be enabled (INT_OVR bit in INT1_CTRL (0Ch)

) in order to be raised when the FIFO is filled to the level specified by the FTH[4:0] bits of

FIFO_CTRL

(2Eh)

. When a FIFO threshold interrupt occurs, the first data has been overwritten and the

FIFO stops collecting data from the input channels.

Figure 10. FIFO mode x i

,y i

,z i x

0 x

1 x

2 i 0 y

1 y

2 z

0 z

1 z

2 x

31 y

31 z

31

Continuous mode ( FIFO_CTRL (2Eh)

(FMODE[2:0] = 110) provides a continuous FIFO update: as new data arrives the older is discarded.

A FIFO threshold flag

FIFO_SRC (2Fh)

(FTH) is asserted when the number of unread samples in FIFO is greater than or equal to

FIFO_CTRL (2Eh) (FTH4:0).

Obsolete Product(s) - Obsolete Product(s)

‘1’in register

INT1_CTRL (0Ch) .

A full-flag interrupt can be enabled,

INT1_CTRL (0Ch)

(INT_ FSS5) = '1' when FIFO becomes saturated and in order to read the contents all at once.

If an overrun occurs, the oldest sample in FIFO is overwritten and the OVRN flag in

FIFO_SRC (2Fh)

is asserted.

In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in

FIFO_SRC (2Fh) (FSS[5:0]).

26/80 DocID025605 Rev 3

LSM6DS1 x i

,y i

,z i

Figure 11. Continuous mode x

0 x

1 x

2 x

30 x

31 y

0 y

1 y

2 y

30 y

31 z

0 z

1 z

2 z

30 z

31

Functionality

In Continuous-to-FIFO mode ( FIFO_CTRL (2Eh) (FMODE [2:0] = 011), FIFO behavior

changes according to the

INT1_GEN_SRC_XL (26h)

(IA1_XL) bit. When the

INT1_GEN_SRC_XL (26h)

(IA1_XL) bit is equal to '1', FIFO operates in FIFO mode. When the

INT1_GEN_SRC_XL (26h)

(IA1_XL) bit is equal to '0', FIFO operates in Continuous mode.

The interrupt generator should be set to the desired configuration by means of

INT_GEN_CFG1_XL (06h)

,

INT_GEN_THS1_X_XL (07h) ,

INT_GEN_THS1_Y_XL (08h) and INT_GEN_THS1_Z_XL (09h) .

CTRL_REG4 (1Eh)

(LIR_XL) bit should be set to '1' in order to have latched interrupt.

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80

Functionality x i

,y i

,z i

Figure 12. Continuous-to-FIFO mode x i

,y i

,z i x

0 x

1 x

2 x

30 x

31 y

0 y

1 y

2 y

30 y

31 z

0 z

1 z

2 z

30 z

31 x

0 x

1 x

2 y

0 y

1 y

2 x

31 y

31 z

31 z

0 z

1 z

2

LSM6DS1

Continuous Mode

Trigger event

FIFO Mode

In Bypass-to-Continuous mode ( FIFO_CTRL (2Eh) (FMODE[2:0] = '100'), data

measurement storage inside FIFO operates in Continuous mode when

INT1_GEN_SRC_XL (26h) (IA1_XL) is equal to '1', otherwise FIFO content is reset (Bypass

mode).

The interrupt generator should be set to the desired configuration by means of

INT_GEN_CFG1_XL (06h)

,

INT_GEN_THS1_X_XL (07h) ,

INT_GEN_THS1_Y_XL (08h) and INT_GEN_THS1_Z_XL (09h) .

The

CTRL_REG4 (1Eh) (LIR_XL) bit should be set to '1' in order to have latched interrupt.

Figure 13. Bypass-to-Continuous mode x i

,y i

,z i x

0 i 0 z

0 x i

,y i

,z i x

0 x

1 x

2 y

0 x

1 y

1 z

1 y

1 y

2 z

0 z

1 z

2 x

2 y

2 z

2 empty x

30 z

30 y

30 x

31 z

31 y

31 z

31 y

31 x

31

Obsolete Product(s) - Obsolete Product(s)

Bypass Mode Continuous Mode

Trigger event

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LSM6DS1 Functionality

3.6.1 Sensor hub description

In the LSM6DS1 the embedded sensor hub allows acquiring data from external sensors and collecting them in dedicated registers and FIFO using the I

2

C master interface. These data can be read by the application processor accessing the LSM6DS1 registers through the

SPI/ I

2

C interfaces.

3.6.2 Sensor hub block diagram

Figure 14. LSM6DS1 sensor hub

Dataready (optional)

Magnetometer

LSM6DS1

Sensor HUB

I

2

C master

Pressure sensor I

2

C master

Others sensors

Registers and

FIFO

I

2

C/SPI slave

Dataready (optional)

I

2

C/SPI slave

Application

Processor

Accelerometer

Temperature

Gyroscope

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Functionality

Sensor HUB

Figure 15. Embedded functionalities- block diagram

Magnetic data

Heading

Heading

LSM6DS1

XL data

Pitch/Roll

Gyro data

Kalmann

Filter

Pitch/Roll

I

2

C/SPI

Slave

GYRO

OFFSET

CORRECTION

Gyro data correction

In the LSM6DS1 the embedded functionalities available are the following:

 Heading: it works if an external magnetometer is connected to the master; output data

can be read in dedicated registers HEADING_DATA_L/HEADING_DATA_H (D4h, D5h)

 Pitch/Roll angular position: it is calculated from the accelerometer data or from the

Kalmann filter; output data can be read in dedicated registers

PITCH_ANGLE_L/PITCH_ANGLE_H (CCh, CDh) and

ROLL_ANGLE_L/ROLL_ANGLE_H (CEh, CFh)

.

 Gyroscope data correction: gyroscope output is stabilized using information coming from the accelerometer. The offset used to correct the output data can be read in dedicated registers

GYRO_OFS_PITCH_DATA_L/GYRO_OFS_PITCH_DATA_H

(D0h, D1h) and GYRO_OFS_ROLL_DATA_L/GYRO_OFS_ROLL_DATA_H (D2h,

D3h) .

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LSM6DS1 Digital interfaces

The registers embedded inside the LSM6DS1 may be accessed through both the I 2 C slave and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4wire interface mode.

The serial interfaces are mapped onto the same pins. To select/exploit the I 2 C slave interface, the CS line must be tied high (i.e connected to Vdd_IO).

Pin name

CS

SCL_S/SPC

SDA_S/SDI/SDO

SDO/SA0

Table 13. Serial interface pin description

Pin description

SPI enable

I

2

C/SPI mode selection (1: SPI idle mode / I2C slave communication enabled;

0: SPI communication mode / I2C slave disabled)

I

2

C slave Serial Clock (SCL_S)

SPI Serial Port Clock (SPC)

I

2

C slave Serial Data (SDA_S)

SPI Serial Data Input (SDI)

3-wire Interface Serial Data Output (SDO)

SPI Serial Data Output (SDO)

I

2

C slave less significant bit of the device address

4.1 I 2 C serial interface

The LSM6DS1 I 2 C slave is a bus slave. The I 2 C slave is employed to write the data to the registers, whose content can also be read back.

The relevant I 2 C terminology is provided in the table below.

Term

Table 14. I 2 C terminology

Description

Transmitter

Receiver

Master

The device which sends data to the bus

The device which receives data from the bus

The device which initiates a transfer, generates clock signals and terminates a transfer

Slave The device addressed by the master Obsolete Product(s) - Obsolete Product(s)

There are two signals associated with the I

2

C slave bus: the serial clock line (SCL_S) and the Serial DAta line (SDA_S). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both the lines are high.

The I

2

C slave interface is implemeted with fast mode (400 kHz) I

2

C standards as well as with the standard mode.

In order to disable the I

2

C block, the I2C_disable bit must be written to ‘1’ in CTRL_REG9

(23h)

.

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Digital interfaces LSM6DS1

4.1.1 I

2

C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a high-to-low transition on the data line while the SCL_S line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.

The Slave ADdress (SAD) associated to the LSM6DS1 is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the voltage supply LSb is ‘1’ (address 1101011b), else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to connect and address two different inertial modules to the same I 2 C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I 2 C embedded inside the LSM6DS1 behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.

The increment of the address is configured by the CTRL_REG8 (22h) (IF_ADD_INC).

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes. If the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.

Table 15 explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Command

Read

Write

Read

Write

Table 15. SAD+Read/Write patterns

SAD[6:1] SAD[0] = SA0 R/W

110101

110101

110101

110101

1

1

0

0

1

0

1

0

SAD+R/W

11010101 (D5h)

11010100 (D4h)

11010111 (D7h)

11010110 (D6h)

SAD + W SUB DATA SP

Slave SAK SAK SAK

Table 17. Transfer when master is writing multiple bytes to slave

Master ST SAD + W SUB DATA DATA

Slave SAK SAK SAK SAK

SP

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LSM6DS1 Digital interfaces

Master

Table 18. Transfer when master is receiving (reading) one byte of data from slave

ST SAD + W SUB SR SAD + R NMAK

Slave SAK SAK SAK DATA

SP

Table 19. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA

DAT

A

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL_S low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low-to-high transition on the SDA_S line while the SCL_S line is high is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In the presented communication format MAK is Master acknowledge and NMAK is No

Master Acknowledge.

4.2 SPI bus interface

The LSM6DS1 SPI is a bus slave. The SPI allows to write and read the registers of the device.

The serial interface connects to applications using 4 wires: CS , SPC , SDI and SDO .

Figure 16. Read and write protocol

CS

SPC

SDI

RW

AD6 AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .

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Digital interfaces LSM6DS1

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .

bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1-7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods will be added. When the

CTRL_REG8 (22h) (IF_ADD_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL_REG8 (22h)

(IF_ADD_INC) bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

Figure 17. SPI read protocol

CS

SPC

SDI

RW

AD6 AD5 AD4 AD3 AD2 AD1 AD0

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).

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LSM6DS1 Digital interfaces

Figure 18. Multiple byte SPI read protocol (2-byte example)

CS

SPC

SDI

SDO

RW

AD6 AD5 AD4 AD3 AD2 AD1 AD0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 19. SPI write protocol

CS

SPC

SDI

RW

AD6 AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : WRITE bit. The value is 0.

bit 1 -7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).

bit 16-... : data DI(...-8). Further data in multiple byte writes.

Figure 20. Multiple byte SPI write protocol (2-byte example)

CS

SPC Obsolete Product(s) - Obsolete Product(s)

SDI

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8

RW

AD6 AD5 AD4 AD3 AD2 AD1 AD0

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Digital interfaces

4.2.3 SPI read in 3-wire mode

LSM6DS1

3-wire mode is entered by setting the

CTRL_REG8 (22h) (SIM) bit equal to ‘1’ (SPI serial

interface mode selection).

CS

SPC

SDI/O

Figure 21. SPI read protocol in 3-wire mode

RW

AD6 AD5 AD4 AD3 AD2 AD1 AD0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

A multiple read command is also available in 3-wire mode.

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LSM6DS1 Register mapping

The table given below provides a list of the 8/16 bit registers embedded in the device and the corresponding addresses.

Name

Table 20. Register mapping

Register address

Type

Hex Binary

Default Note

Reserved

INT_GEN_CFG2_XL

INT_GEN_THS2_XL

INT_GEN_DUR2_XL

ACT_THS

ACT_DUR

INT_GEN_CFG1_XL

INT_GEN_THS1_X_XL

INT_GEN_THS1_Y_XL

INT_GEN_THS1_Z_XL

INT_GEN_DUR1_XL

REFERENCE_G

INT1_CTRL

INT2_CTRL

Reserved

WHO_AM_I

CTRL_REG1_G

CTRL_REG2_G

CTRL_REG3_G

ORIENT_CFG_G r/w r/w

-r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w

0C

0D

0E

0F

08

09

0A

0B

10

11

12

13

04

05

06

07

00

01

02

03

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

00001000

00001001

00001010

00001011

00001100

00001101

--

00001111

00010000

00010001

00010010

00010011

--

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

--

01101000

00000000

00000000

00000000

00000000

Reserved

Reserved

INT_GEN_SRC_G r 14 00010100 output

OUT_TEMP_L

OUT_TEMP_H r r

15

16

00010101

00010110 output output

STATUS_REG r 17 00010111 output

OUT_X_L_G

OUT_X_H_G

OUT_Y_L_G

OUT_Y_H_G

OUT_Z_L_G r r r r r 18

19

1A

1B

1C

00011000

00011001

00011010

00011011

00011100 output output output output output

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Register mapping LSM6DS1

Register address

Name Type Default Note

Hex Binary

OUT_Z_H_G

CTRL_REG4

CTRL_REG5_XL

CTRL_REG6_XL

CTRL_REG7_XL

CTRL_REG8

CTRL_REG9

CTRL_REG10

INT2_GEN_SRC_XL

INT1_GEN_SRC_XL

STATUS_REG

OUT_X_L_XL

OUT_X_H_XL

OUT_Y_L_XL

OUT_Y_H_XL

OUT_Z_L_XL r r r r r r r r r/w r/w r/w r/w r r/w r/w r/w

29

2A

2B

2C

25

26

27

28

21

22

23

24

1D

1E

1F

20

00011101

00011110

00011111

00100000

00100001

00100010

00100011

00100100

00100101

00100110

00100111

00101000

00101001

00101010

00101011

00101100 output output output output output output output output output

00111000

00111000

00000000

00000000

00000100

00000000

00000000

OUT_Z_H_XL

FIFO_CTRL

FIFO_SRC

INT_GEN_CFG_G

INT_GEN_THS_XH_G

INT_GEN_THS_XL_G

INT_GEN_THS_YH_G

INT_GEN_THS_YL_G r/w r/w r/w r/w r r/w r r/w

31

32

33

34

2D

2E

2F

30

00101101

00101110

00101111

00110000

00110001

00110010

00110011

00110100 output

00000000 output

00000000

00000000

00000000

00000000

00000000

INT_GEN_THS_ZH_G

INT_GEN_THS_ZL_G r/w r/w

35

36

00110101

00110110

00000000

00000000

INT_GEN_DUR_G

Reserved r/w

--

37

38-7F

00110111

--

00000000

-Reserved

EXTERNAL_SENSORS_DATA

MASTER_SYNC_REG

MASTER_FSM_REG

Reserved

MASTER_STATUS_REG

Reserved r r/w r/w

-r

--

80-8F

90

91

92-96

97

98-AF

--

10010000

10010001

--

10010111

-output

00000000

01011000

--

00000000

--

Reserved

Reserved

38/80 DocID025605 Rev 3

LSM6DS1 Register mapping

Register address

Name Type Default Note

Hex Binary

SLAVE0_I2C_ADD

SLAVE0_SUB_ADD

Reserved

SLAVE0_DATA_TO_WRITE

SLAVE0_CONFIG

SLAVE0_BYTE_TO_READ

SLAVE1_I2C_ADDD

SLAVE1_SUB_ADD

SLAVE1_DATA_TO_WRITE

SLAVE1_CONFIG

SLAVE1_BYTE_TO_READ

SLAVE2_I2C_ADD

SLAVE2_SUB_ADD

SLAVE2_DATA_TO_WRITE

SLAVE2_CONFIG

SLAVE2_BYTE_TO_READ

MAGNETOMETER_ROUTINES

Reserved

GYRO_OFS_XY_ON_OUT

MAG_CFG

Reserved

PITCH_ANGLE_L

PITCH_ANGLE_H

ROLL_ANGLE_L

ROLL_ANGLE_H

GYRO_OFS_PITCH_DATA_L r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w

-r/w r r

-r r r r/w

-r/w r/w

BE

BF

C0

C1

BA

BB

BC

BD

B0

B1

B2-B4

B5

B6

B7

B8

B9

C2

C3-C8

C9

CA

CB

CC

CD

CE

CF

D0

10110000

10110001

--

10110101

10110110

10110111

10111000

10111001

10111010

10111011

10111100

10111101

10111110

10111111

11000000

11000001

11000010

11000011

11001001

11001010

11001011

11001100

11001101

11001110

11001111

11010000

00000000

00000000

--

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

--

00100010

00000000

-output output output output output

Reserved

Reserved

Reserved

GYRO_OFS_PITCH_DATA_H

GYRO_OFS_ROLL_DATA_L r r

D1

D2

11010001

11010010 output output

GYRO_OFS_ROLL_DATA_H r D3 11010011 output

HEADING_DATA_L r D4 11010100 output

HEADING_DATA_H r D5 11010101 output

Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damages to the device.

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Register mapping LSM6DS1

To guarantee proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored on those registers must not be changed.

The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.

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LSM6DS1 Register description

The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of

7 bits, are used to identify them and to write the data through the serial interface.

Linear acceleration sensor interrupt generator 2 configuration register (r/w).

AOI2_XL

AOI2_XL

6D2

ZHIE2_XL

ZLIE2_XL

YHIE2_XL

YLIE2_XL

XHIE2_XL

6D2

Table 21. INT_GEN_CFG2_XL register

ZHIE2_XL ZLIE2_XL YHIE2_XL YLIE2_XL XHIE2_XL XLIE2_XL

Table 22. INT_GEN_CFG2_XL register description

And/Or combination of accelerometer’s interrupt 2 events. Default value: 0

(0: OR combination; 1: AND combination)

6-direction detection function for interrupt 2. Default value: 0

(0: disabled; 1: enabled)

Enable interrupt 2 generation on accelerometer’s Z-axis high event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request)

Enable interrupt 2 generation on accelerometer’s Z-axis low event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request)

Enable interrupt 2 generation on accelerometer’s Y-axis high event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request)

Enable interrupt 2 generation on accelerometer’s Y-axis low event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request)

Enable interrupt 2 generation on accelerometer’s X-axis high event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request)

Enable interrupt 2 generation on accelerometer’s X-axis low event or on direction recognition. Default value: 0

(0: disable interrupt request; 1: enable interrupt request)

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Register description LSM6DS1

Linear acceleration sensor interrupt 2 threshold register (r/w).

Table 23. INT_GEN_THS2_XL register

THS2_XL7 THS2_XL6 THS2_XL5 THS2_XL4 THS2_XL3 THS2_XL2 THS2_XL1 THS2_XL0

THS2_XL [7:0]

Table 24. INT_GEN_THS2_XL register description

Interrupt 2 thresholds . Default value: 0000 0000

Linear acceleration sensor interrupt 2 duration register (r/w).

Table 25. INT_GEN_DUR2_XL register

WAIT2_XL DUR2_XL6 DUR2_XL5 DUR2_XL4 DUR2_XL3 DUR2_XL2 DUR2_XL1 DUR2_XL0

WAIT2_XL

DUR2_XL [6:0]

Table 26. INT_GEN_DUR2_XL register description

Wait function enable on duration counter. Default value: 0

(0: wait function off; 1: wait for DUR2_XL [6:0] samples before exiting from interrupt 2)

Enter/exit interrupt 2 duration value. Default value: 000 0000

Activity threshold register.

SLEEP_ON_

INACT_EN

Table 27. ACT_THS register

ACT_THS6 ACT_THS5 ACT_THS4 ACT_THS3 ACT_THS2 ACT_THS1 ACT_THS0

SLEEP_ON_

INACT_EN

ACT_THS [6:0]

Table 28. ACT_THS register description

Gyroscope operating mode during inactivity. Default value: 0

(0: Gyroscope in power-down; 1: Gyroscope in sleep mode)

Inactivity threshold. Default value: 000 0000

Obsolete Product(s) - Obsolete Product(s)

Inactivity duration register.

Table 29. ACT_DUR register

ACT_DUR7 ACT_DUR6 ACT_DUR5 ACT_DUR4 ACT_DUR3 ACT_DUR2 ACT_DUR1 ACT_DUR0

Table 30. ACT_DUR register description

Inactivity duration. Default value: 0000 0000 ACT_DUR [7:0]

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LSM6DS1 Register description

Linear acceleration sensor interrupt 1 generator configuration register.

AOI_XL

AOI_XL

6D1

ZHIE_XL

ZLIE_XL

YHIE_XL

YLIE_XL

XHIE_XL

XLIE_XL

6D

Table 31. INT_GEN_CFG1_XL register

ZHIE_XL ZLIE_XL YHIE_XL YLIE_XL XHIE_XL XLIE_XL

Table 32. INT_GEN_CFG1_XL register description

AND/OR combination of accelerometer’s interrupt 1 events. Default value: 0

(0: OR combination; 1: AND combination)

6-direction detection function for interrupt 1. Default value: 0

(0: disabled; 1: enabled)

Enable interrupt 1 generation on accelerometer’s Z-axis high event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold)

Enable interrupt 1 generation on accelerometer’s Z-axis low event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold)

Enable interrupt 1 generation on accelerometer’s Y-axis high event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold)

Enable interrupt 1 generation on accelerometer’s Y-axis low event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold)

Enable interrupt 1 generation on accelerometer’s X-axis high event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold)

Enable interrupt 1 generation on accelerometer’s X-axis low event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold)

Linear acceleration sensor interrupt 1 threshold register.

Obsolete Product(s) - Obsolete Product(s)

Table 33. INT_GEN_THS1_X_XL register

THS1_XL_

X7

THS1_XL_

X6

THS1_XL_

X5

THS1_XL_

X4

THS1_XL_

X3

THS1_XL_

X2

THS1_XL_

X1

THS1_XL_

X0

Table 34. INT_GEN_THS1_X_XL register description

THS1_XL_X [7:0] X-axis interrupt threshold. Default value: 0000 0000

DocID025605 Rev 3 43/80

80

Register description LSM6DS1

Linear acceleration sensor interrupt 1 threshold register.

THS1_XL_

Y7

THS1_XL_

Y6

Table 35. INT_GEN_THS1_Y_XL register

THS1_XL_

Y5

THS1_XL_

Y4

THS1_XL_

Y3

THS1_XL_

Y2

THS1_XL_

Y1

THS1_XL_

Y0

Table 36. INT_GEN_THS1_Y_XL register description

THS1_XL_Y [7:0] Y-axis interrupt threshold.

Default value: 0000 0000

Linear acceleration sensor interrupt 1 threshold register.

THS1_XL_

Z7

THS1_XL_

Z6

Table 37. INT_GEN_THS1_Z_XL register

THS1_XL_

Z5

THS1_XL_

Z4

THS1_XL_

Z3

THS1_XL_

Z2

THS1_XL_

Z1

THS1_XL_

Z0

Table 38. INT_GEN_THS1_Z_XL register description

THS1_XL_Z [7:0] Z-axis interrupt threshold.

Default value: 0000 0000

Linear acceleration sensor interrupt 1 duration register.

WAIT_XL

DUR1_XL

6

Table 39. INT_GEN_DUR1_XL register

DUR1_XL

5

DUR1_XL

4

DUR1_XL

3

DUR1_XL

2

DUR1_XL

1

DUR1_XL

0

WAIT_XL

DUR1_XL [6:0]

Table 40. INT_GEN_DUR1_XL register description

Wait function enabled on duration counter. Default value: 0

(0: wait function off; 1: wait for DUR_XL [6:0] samples before exiting interrupt)

Enter/exit interrupt duration value. Default value: 000 0000

44/80

Table 41. REFERENCE_G register

REF7_G REF6_G REF5_G REF4_G REF3_G REF2_G REF1_G REF0_G

REF_G [7:0]

Table 42. REFERENCE_G register description

Reference value for gyroscope’s digital high-pass filter (r/w).

Default value: 0000 0000

DocID025605 Rev 3

LSM6DS1 Register description

INT1 pin control register.

INT1_IG

_G

INT1_IG_

XL

INT1_

FSS5

Table 43. INT1_CTRL register

INT1_OVR INT1_FTH INT1_ Boot

INT1_

DRDY_G

INT1_

DRDY_XL

INT1_IG_G

INT1_ IG_XL

INT1_ FSS5

INT1_OVR

Table 44. INT1_CTRL register description

Gyroscope interrupt enable on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

Accelerometer interrupt generator on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

FSS5 interrupt enable on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

Overrun interrupt on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_FTH

INT1_ Boot

FIFO threshold interrupt on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

Boot status available on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT1_DRDY_G

INT1_DRDY_XL

Gyroscope data ready on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

Accelerometer data ready on INT1 pin. Default value: 0

(0: disabled; 1: enabled)

INT2 pin control register.

INT2_IN

ACT

INT2_IG2

_XL

INT2_

FSS5

Table 45. INT2_CTRL register

INT2_OVR INT2_FTH

INT2_DRD

Y_TEMP

INT2_

DRDY_G

INT2_

DRDY_XL

Obsolete Product(s) - Obsolete Product(s)

DocID025605 Rev 3 45/80

80

Register description

INT2_INACT

INT2_ IG2_XL

INT2_ FSS5

INT2_OVR

Table 46. INT2_CTRL register description

Gyroscope interrupt enable on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

Accelerometer interrupt 2 generator on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

FSS5 interrupt enable on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

Overrun interrupt on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_FTH

FIFO threshold interrupt on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_DRDY_TE

MP

Temperature sensor data ready on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

INT2_DRDY_G

INT2_DRDY_XL

Gyroscope data ready on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

Accelerometer data ready on INT2 pin. Default value: 0

(0: disabled; 1: enabled)

LSM6DS1

Who_AM_I register.

0 1 1

Table 47. WHO_AM_I register

0 1 0 0 0

46/80

Angular rate sensor control register 1.

Table 48. CTRL_REG1_G register

ODR_G2 ODR_G1 ODR_G0 FS_G1 FS_G0 0

(1)

1. This bit must be set to ‘0’ for the correct operation of the device

BW_G1 BW_G0

ODR_G [2:0]

FS_G [1:0]

BW_G [1:0]

Gyroscope output data rate selection . Default value: 000

(Refer to

Table 50 and

Table 51 )

Gyroscope full-scale selection. Default value: 00

(00: 245 dps; 01: 500 dps; 11: 2000 dps)

Gyroscope bandwidth selection. Default value: 00

ODR_G [2:0] are used to set ODR selection when both the accelerometer and gyroscope are activated. BW_G [1:0] are used to set the bandwidth selection of the gyroscope.

DocID025605 Rev 3

LSM6DS1 Register description

The following table summarizes all frequencies available for each combination of the

ODR_G / BW_G bits after LPF1 (see Table 50

) and LPF2 (see

Table 51 ) when both the

accelerometer and gyroscope are activated. For more details regarding signal processing scheme please refer to

Figure 22 .

ODR_G2

Table 50. ODR and BW configuration setting (after LPF1)

ODR_G1 ODR_G0 ODR [Hz] Cutoff [Hz]

(1)

1

1

1

1

0

0

0

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Power-down

59.5

952 n.a.

n.a.

14.9 5

19

119 38

238 76

476 100

100 n.a.

1. Values in the table are indicative and can vary proportionally with the specific ODR value.

Obsolete Product(s) - Obsolete Product(s)

DocID025605 Rev 3 47/80

80

Register description LSM6DS1

Table 51. ODR and BW configuration setting (after LPF2)

ODR_G [2:0] BW_G [1:0] ODR [Hz] Cutoff [Hz]

(1)

011

011

011

011

010

010

010

010

001

001

001

001

000

000

000

000

101

101

101

101

100

100

100

100

110

110

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

00

01

476

476

476

476

238

238

238

238

952

952

119

119

119

119

59.5

59.5

59.5

59.5

14.9

14.9

14.9

14.9

Power-down

Power-down

Power-down

Power-down

14

31

31

31

16

16

16

16 n.a.

n.a.

n.a.

n.a.

n.a.

n.a.

n.a.

n.a.

21

28

57

100

14

29

63

78

33

40

110

110

10

11

952

952

58

100

111 00 n.a.

n.a.

111 01 n.a.

n.a.

111

111

10

11 n.a.

n.a.

n.a.

n.a.

1. Values in the table are indicative and can vary proportionally with the specific ODR value.

48/80 DocID025605 Rev 3

LSM6DS1 Register description

Angular rate sensor control register 2.

0

(1)

0

(1)

Table 52. CTRL_REG2_G register

0

(1)

0

(1)

INT_SEL1 INT_SEL0 OUT_SEL1 OUT_SEL0

1. These bits must be set to ‘0’ for the correct operation of the device

INT_SEL [1:0]

OUT_SEL [1:0]

Table 53. CTRL_REG2_G register description

INT selection configuration. Default value: 00

(Refer to

Figure 22 )

Out selection configuration. Default value: 00

(Refer to

Figure 22 )

Figure 22. INT_SEL and OUT_SEL configuration gyroscope block diagram

DataReg

FIFO

LPF2

ADC LPF1 HPF

Interrupt generator

Angular rate sensor control register 3.

LP_mode HP_EN

Table 54. CTRL_REG3_G register

0

(1)

0

(1)

HPCF3_G HPCF2_G HPCF1_G HPCF0_G

1. These bits must be set to ‘0’ for the correct operation of the device Obsolete Product(s) - Obsolete Product(s)

Table 55. CTRL_REG3_G register description

LP_mode

Low-power mode enable. Default value: 0

(0: Low-power disable; 1:Low power enable)

HP_EN

HPCF_G [3:0]

High-pass filter enable. Default value: 0

(0: HPF disabled; 1: HPF enabled, refer to

Figure 22 )

Gyroscope high-pass filter cutoff frequency selection. Default value: 0000

Refer to

Table 56 .

DocID025605 Rev 3 49/80

80

Register description LSM6DS1

Table 56. Gyroscope high-pass filter cutoff frequency configuration [Hz] (1)

HPCF_G [3:0] ODR = 14.9 Hz ODR = 59.5 Hz ODR = 119 Hz ODR = 238 Hz ODR = 476 Hz ODR = 952 Hz

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

0.002

0.001

4

2

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

8

4

2

1

0.5

0.2

0.1

0.05

0.02

0.01

15

8

4

2

1

0.5

0.2

0.1

0.05

0.02

1. Values in the table are indicative and can vary proportionally with the specific ODR value

2

1

0.5

0.2

8

4

30

15

0.1

0.05

4

2

1

0.5

57

30

15

8

0.2

0.1

Angular rate sensor sign and orientation register.

0

(1)

0

(1)

Table 57. ORIENT_CFG_G register

SignX_G SignY_G SignZ_G Orient_2 Orient_1 Orient_0

1. These bits must be set to ‘0’ for the correct operation of the device

SignX_G

SignY_G

SignZ_G

Orient [2:0]

Table 58. ORIENT_CFG_G register description

Pitch axis (X) angular rate sign. Default value: 0

(0: positive sign; 1: negative sign)

Roll axis (Y) angular rate sign. Default value: 0

(0: positive sign; 1: negative sign)

Yaw axis (Z) angular rate sign. Default value: 0

(0: positive sign; 1: negative sign)

Directional user-orientation selection. Default value: 000

Obsolete Product(s) - Obsolete Product(s)

Angular rate sensor interrupt source register.

Table 59. INT_GEN_SRC_G register

ZH_G ZL_G YH_G YL_G 0 IA_G XH_G XL_G

50/80 DocID025605 Rev 3

LSM6DS1 Register description

IA_G

ZH_G

ZL_G

YH_G

YL_G

XH_G

XL_G

Table 60. INT_GEN_SRC_G register description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Yaw (Z) high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Yaw (Z) low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Roll (Y) high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Roll (Y) low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

Pitch (X) high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

Pitch (X) low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

6.20 OUT_TEMP_L (15h), OUT_TEMP_H (16h)

Temperature data output register. L and H registers together express a 16-bit word in two’s complement right-justified.

Temp7 Temp6 Temp5

Table 61. OUT_TEMP_L register

Temp4 Temp3 Temp2 Temp1 Temp0

Temp11

Temp [11:0]

Table 62. OUT_TEMP_H register

Temp11 Temp11 Temp11 Temp11 Temp10 Temp9 Temp8

Table 63. OUT_TEMP register description

Temperature sensor output data.

The value is expressed as two’s complement sign extended on the MSB.

Status register.

Obsolete Product(s) - Obsolete Product(s)

Table 64. STATUS_REG register

0 IG_XL IG_G INACT

BOOT_

STATUS

TDA GDA XLDA

DocID025605 Rev 3 51/80

80

Register description LSM6DS1

IG_XL

IG_G

INACT

BOOT_

STATUS

TDA

GDA

XLDA

Table 65. STATUS_REG register description

Accelerometer interrupt output signal. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupt events have been generated)

Gyroscope interrupt output signal. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupt events have been generated)

Inactivity interrupt output signal. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupt events have been generated)

Boot running flag signal. Default value: 0

(0: no boot running; 1: boot running)

Temperature sensor new data available. Default value: 0

(0: a new data is not yet available; 1: a new data is available)

Gyroscope new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

Accelerometer new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

6.22 OUT_X_G (18h - 19h)

Angular rate sensor pitch axis (X) angular rate output register. The value is expressed as a

16-bit word in two’s complement.

6.23 OUT_Y_G (1Ah - 1Bh)

Angular rate sensor roll axis (Y) angular rate output register. The value is expressed as a

16-bit word in two’s complement.

6.24 OUT_Z_G (1Ch - 1Dh)

Angular rate sensor yaw axis (Z) angular rate output register. The value is expressed as a

16-bit word in two’s complement.

Control register 4.

Obsolete Product(s) - Obsolete Product(s)

0

(1)

0

(1)

Zen_G Yen_G Xen_G 0

(1)

LIR_XL1 4D_XL1

1. These bits must be set to ‘0’ for the correct operation of the device

52/80 DocID025605 Rev 3

LSM6DS1

Zen_G

Yen_G

Xen_G

LIR_XL1

4D_XL1

Register description

Table 67. CTRL_REG4 register description

Gyroscope’s yaw axis (Z) output enable. Default value: 1

(0: Z-axis output disabled; 1: Z-axis output enabled)

Gyroscope’s roll axis (Y) output enable. Default value: 1

(0: Y-axis output disabled; 1: Y-axis output enabled)

Gyroscope’s pitch axis (X) output enable. Default value: 1

(0: X-axis output disabled; 1: X-axis output enabled)

Latched interrupt. Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

4D option enabled on interrupt. Default value: 0

(0: interrupt generator uses 6D for position recognition; 1: interrupt generator uses

4D for position recognition)

Linear acceleration sensor control register 5.

DEC_1 DEC_0

Table 68. CTRL_REG5_XL register

Zen_XL Yen_XL Xen_XL

1. These bits must be set to ‘0’ for the correct operation of the device

0 (1)

DEC_ [0:1]

Zen_XL

Yen_XL

Xen_XL

0 (1)

Table 69. CTRL_REG5_XL register description

Decimation of acceleration data on OUT REG and FIFO. Default value: 00

(00: no decimation;

01: update every 2 samples;

10: update every 4 samples;

11: update every 8 samples)

Accelerometer’s Z-axis output enable. Default value: 1

(0: Z-axis output disabled; 1: Z-axis output enabled)

Accelerometer’s Y-axis output enable. Default value: 1

(0: Y-axis output disabled; 1: Y-axis output enabled)

Accelerometer’s X-axis output enable. Default value: 1

(0: X-axis output disabled; 1: X-axis output enabled)

0 (1)

Obsolete Product(s) - Obsolete Product(s)

Linear acceleration sensor control register 6.

Table 70. CTRL_REG6_XL register

ODR_XL2 ODR_XL1 ODR_XL0 FS1_XL FS0_XL

BW_SCAL

_ODR

BW_XL1 BW_XL0

DocID025605 Rev 3 53/80

80

Register description LSM6DS1

ODR_XL [2:0]

FS_XL [1:0]

BW_SCAL_ODR

BW_XL [1:0]

Table 71. CTRL_REG6_XL register description

Output data rate and Power Mode selection .

Default value: 000 (see Table 72 ).

Accelerometer full-scale selection. Default value: 00

(00: ±2 g ; 10: ±4 g ; 11: ±8 g )

Bandwidth selection. Default value: 0

(0: bandwidth determined by ODR selection:

- BW = 408 Hz when ODR = 952 Hz, 50 Hz, 10 Hz;

- BW = 211 Hz when ODR = 476 Hz;

- BW = 105 Hz when ODR = 238 Hz;

- BW = 50 Hz when ODR = 119 Hz;

1: bandwidth selected according to BW_XL [2:1] selection)

Anti-aliasing filter bandwidth selection. Default value: 00

(00: 408 Hz; 01: 211 Hz; 10: 105 Hz; 11: 50 Hz)

ODR_XL [2:0] is used to set power mode and ODR selection. Table 72

summarizes all available frequencies when only the accelerometer is activated.

1

1

0

1

1

0

0

0

ODR_XL2

Table 72. ODR register setting (accelerometer only mode)

ODR_XL1 ODR_XL0 ODR selection [Hz]

0

1

1

0

1

0

0

1

1

0

1

0

1

0

1

0

Power-down

10 Hz

50 Hz

119 Hz

238 Hz

476 Hz

952 Hz n.a.

Linear acceleration sensor control register 7.

DCF1

Table 73. CTRL_REG7_XL register

DCF0 0

(1)

1. These bits must be set to ‘0’ for the correct operation of the device

FDS 0

(1)

HPIS1

54/80 DocID025605 Rev 3

LSM6DS1 Register description

1

1

1

1

HR

DCF[1:0]

FDS

HPIS1

Table 74. CTRL_REG7_XL register description

High resolution mode for accelerometer enable. Default value: 0

(0: disabled; 1: enabled). Refer to

Table 75

Accelerometer digital filter (high-pass and low-pass) cutoff frequency selection: the bandwidth of the high-pass filter depends on the selected ODR. Refer to

Table 75

Filtered data selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO)

High-pass filter enabled for acceleration sensor interrupt function on Interrupt. Default value: 0

(0: filter bypassed; 1: filter enabled)

Table 75. Low-pass cutoff frequency in high resolution mode (HR = 1)

HR CTRL_REG7 (DCF [1:0]) LP cutoff freq. [Hz]

00

01

10

11

ODR/50

ODR/100

ODR/9

ODR/400

Control register 8.

BOOT BDU

Table 76. CTRL_REG8 register

H_LACTIVE PP_OD SIM IF_ADD_INC BLE SW_RESET

BOOT

BDU

H_LACTIVE

PP_OD

Table 77. CTRL_REG8 register description

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content

(1)

)

Block Data Update. Default value: 0

(0: continuous update; 1: output registers not updated until MSB and LSB read

Interrupt activation level. Default value: 0

(0: interrupt output pins active high; 1: interrupt output pins active low)

Push-pull/open-drain selection on INT1 and INT2 pin. Default value: 0. (0: pushpull mode; 1: open-drain mode)

SIM SPI serial interface mode selection. Default value: 0

IF_ADD_INC

(0: 4-wire interface; 1: 3-wire interface) Obsolete Product(s) - Obsolete Product(s) serial interface (I

2

C or SPI). Default value: 1

(0: disabled; 1: enabled)

BLE Big/Little Endian data selection. Default value 0

(0: data LSB @ lower address; 1: data MSB @ lower address)

SW_RESET Software reset. Default value: 0

(0: normal mode; 1: reset device)

1. Boot request is executed as soon as the internal oscillator is turned on. It is possible to set the bit while in power-down mode, in this case it will be served at the next normal mode or sleep mode.

DocID025605 Rev 3 55/80

80

Register description LSM6DS1

Control register 9.

0

(1)

SLEEP_G

Table 78. CTRL_REG9 register

0

(1)

FIFO_

TEMP_EN

DRDY_ mask_bit

I2C_disable FIFO_EN

STOP_ON

_FTH

1. These bits must be set to ‘0’ for the correct operation of the device

SLEEP_G

Table 79. CTRL_REG9 register description

Gyroscope sleep mode enable. Default value: 0

(0: disabled; 1: enabled)

FIFO_TEMP_EN Temperature data storing in FIFO enable. Default value: 0

(0: temperature data not stored in FIFO; 1: temperature data stored in FIFO)

DRDY_mask_bit Data available enable bit. Default value: 0

(0: DA timer disabled; 1: DA timer enabled)

I2C_disable Disable I

2

(0: both I

2

C interface. Default value: 0

C and SPI enabled; 1: I

2

C disabled, SPI only)

FIFO_EN FIFO memory enable. Default value: 0

(0: disabled; 1: enabled)

STOP_ON_FTH Enable FIFO threshold level use. Default value: 0

(0: FIFO depth is not limited; 1: FIFO depth is limited to threshold level)

Control register 10.

0

(1)

0

(1)

0

(1)

Table 80. CTRL_REG10 register

0

(1)

0

(1)

ST_G

1. These bits must be set to ‘0’ for the correct operation of the device

0

(1)

ST_XL

ST_G

Table 81. CTRL_REG10 register description

Angular rate sensor self-test enable. Default value: 0

(0: Self-test disabled; 1: Self-test enabled;)

ST_XL Linear acceleration sensor self-test enable. Default value: 0

(0: Self-test disabled; 1: Self-test enabled;)

Obsolete Product(s) - Obsolete Product(s)

56/80 DocID025605 Rev 3

LSM6DS1 Register description

0

IA2_XL

ZH2_XL

ZL2_XL

YH2_XL

YL2_XL

XH2_XL

XL2_XL

Linear acceleration sensor interrupt 2 source register.

IA2_XL

Table 82. INT2_GEN_SRC_XL register

ZH2_XL ZL2_XL YH2_XL YL2_XL XH2_XL XL2_XL

Table 83. INT2_GEN_SRC_XL register description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Accelerometer’s Z high event. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Accelerometer’s Z low event. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Accelerometer’s Y high event. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Accelerometer’s Y low event. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

Accelerometer’s X high event. Default value: 0

(0: no interrupt, 1: X high event has occurred)

Accelerometer’s X low. event. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Linear acceleration sensor interrupt 1 source register.

IA1_XL

Table 84. INT1_GEN_SRC_XL register

ZH1_XL ZL1_XL YH1_XL YL1_XL 0 XH1_XL XL1_XL

IA1_XL

ZH1_XL

Table 85. INT1_GEN_SRC_XL register description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Accelerometer’s Z high event. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Accelerometer’s Z low event. Default value: 0

ZL1_XL

YH1_XL

(0: no interrupt; 1: Z low event has occurred)

Obsolete Product(s) - Obsolete Product(s)

(0: no interrupt, 1: Y high event has occurred)

YL1_XL

XH1_XL

XL1_XL

Accelerometer’s Y low event. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

Accelerometer’s X high event. Default value: 0

(0: no interrupt, 1: X high event has occurred)

Accelerometer’s X low. event. Default value: 0

(0: no interrupt, 1: X low event has occurred)

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80

Register description LSM6DS1

0

Status register.

IG_XL IG_G

Table 86. STATUS_REG register

INACT

BOOT_

STATUS

TDA GDA XLDA

IG_XL

IG_G

INACT

BOOT_

STATUS

TDA

GDA

XLDA

Table 87. STATUS_REG register description

Accelerometer interrupt output signal. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupt events have been generated)

Gyroscope interrupt output signal. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupt events have been generated)

Inactivity interrupt output signal. Default value: 0.

(0: no interrupt has been generated; 1: one or more interrupt events have been generated)

Boot running flag signal. Default value: 0

(0: no boot running; 1: boot running)

Temperature sensor new data available. Default value: 0

(0: new data is not yet available; 1: new data is available)

Gyroscope new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

Accelerometer new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

6.35 OUT_X_XL (28h - 29h)

Linear acceleration sensor X-axis output register. The value is expressed as a 16-bit word in two’s complement.

6.36 OUT_Y_XL (2Ah - 2Bh)

Linear acceleration sensor Y-axis output register. The value is expressed as a 16-bit word in two’s complement.

6.37 OUT_Z_XL (2Ch - 2Dh) two’s complement.

58/80

FIFO control register.

Table 88. FIFO_CTRL register

FMODE2 FMODE1 FMODE0 FTH4 FTH3 FTH2 FTH1 FTH0

DocID025605 Rev 3

LSM6DS1 Register description

FMODE [2:0]

FTH [4:0]

Table 89. FIFO_CTRL register description

FIFO mode selection bits. Default value: 000

For further details refer to

Table 90 .

FIFO threshold level setting. Default value: 0 0000

0

0

0

0

FMODE2 FMODE1

0

0

1

1

1

1

0

1

0

1

0

1

0

0

Table 90. FIFO mode selection

FMODE0 Mode

Bypass mode. FIFO turned off

FIFO mode. Stop collecting data when FIFO is full.

Reserved

Continuous mode until trigger is deasserted, then FIFO mode.

Bypass mode until trigger is deasserted, then Continuous mode.

Continuous mode. If the FIFO is full, the new sample overwrites the older sample.

Obsolete Product(s) - Obsolete Product(s)

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Register description LSM6DS1

FIFO status control register.

FTH OVRN FSS5

Table 91. FIFO_SRC register

FSS4 FSS3 FSS2

FTH

OVRN

FSS [5:0]

FSS1 FSS0

Table 92. FIFO_SRC register description

FIFO threshold status.

(0: FIFO filling is lower than threshold level; 1: FIFO filling is equal or higher than the threshold level

FIFO overrun status.

(0: FIFO is not completely filled; 1: FIFO is completely filled and at least one sample has been overwritten)

For further details refer to

Table 93

.

Number of unread samples stored into FIFO.

(000000: FIFO empty; 100000: FIFO full, 32 unread samples)

For further details refer to

Table 93

.

Table 93. FIFO_SRC example: OVR/FSS details

FTH OVRN FSS5 FSS4 FSS3 FSS2 FSS1 FSS0 Description

0

--

(1)

...

--

(1)

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

FIFO empty

1 unread sample

0

1

1

1

0

0

0

0

0

0

0

0

0

0

32 unread sample

At least one sample has been overwritten

1. When the number of unread samples in FIFO is greater than the threshold level set in register

FIFO_CTRL

(2Eh)

, the FTH value is ‘1’.

Angular rate sensor interrupt generator configuration register.

Table 94. INT_GEN_CFG_G register

AOI_G LIR_G ZHIE_G ZLIE_G YHIE_G YLIE_G XHIE_G XLIE_G Obsolete Product(s) - Obsolete Product(s)

60/80 DocID025605 Rev 3

LSM6DS1

AOI_G

LIR_G

ZHIE_G

ZLIE_G

YHIE_G

YLIE_G

XHIE_G

XLIE_G

Register description

Table 95. INT_GEN_CFG_G register description

AND/OR combination of gyroscope’s interrupt events. Default value: 0

(0: OR combination; 1: AND combination)

Latch gyroscope interrupt request. Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

Enable interrupt generation on gyroscope’s yaw (Z) axis high event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold)

Enable interrupt generation on gyroscope’s yaw (Z) axis low event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold)

Enable interrupt generation on gyroscope’s roll (y) axis high event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold)

Enable interrupt generation on gyroscope’s roll (y) axis low event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold)

Enable interrupt generation on gyroscope’s pitch (X) axis high event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold)

Enable interrupt generation on gyroscope’s pitch (X) axis low event. Default value: 0

(0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold)

6.41 INT_GEN_THS_X_G (31h - 32h)

Angular rate sensor interrupt generator threshold registers. The value is expressed as a 15bit word in two’s complement.

DCRM_G

THS_G_

X14

Table 96. INT_GEN_THS_XH_G register

THS_G_

X13

THS_G_

X12

THS_G_

X11

THS_G_

X10

THS_G_

X9

THS_G_

X8

THS_G_

X7

THS_G_

X6

THS_G_

X5

THS_G_

X4

THS_G_

X3

THS_G_

X2

THS_G_

X1

THS_G_

X0

DCRM_G

THS_G_X [14:0]

Table 98. INT_GEN_THS_X_G register description

Decrement or reset counter mode selection. Default value: 0

(0: reset; 1: decrement, as per Counter behavior in Figure 23

and Figure 24

)

Angular rate sensor interrupt threshold on pitch (X) axis.

Default value: 0000000 00000000

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Register description LSM6DS1

6.42 INT_GEN_THS_Y_G (33h - 34h)

Angular rate sensor interrupt generator threshold registers. The value is expressed as a 15bit word in two’s complement.

0

(1)

THS_G_

Y14

Table 99. INT_GEN_THS_YH_G register

THS_G_

Y13

THS_G_

Y12

THS_G_

Y11

1. This bit must be set to ‘0’ for the correct operation of the device

THS_G_

Y10

THS_G_

Y9

THS_G_

Y8

THS_G_

Y7

THS_G_

Y6

Table 100. INT_GEN_THS_YL_G register

THS_G_

Y5

THS_G_

Y4

THS_G_

Y3

THS_G_

Y2

THS_G_

Y1

THS_G_

Y0

THS_G_Y [14:0]

Table 101. INT_GEN_THS_Y_G register description

Angular rate sensor interrupt threshold on roll (Y) axis.

Default value: 0000000 00000000

6.43 INT_GEN_THS_Z_G (35h - 36h)

Angular rate sensor interrupt generator threshold registers. The value is expressed as a 15bit word in two’s complement.

0

(1)

THS_G_

Z14

Table 102. INT_GEN_THS_ZH_G register

THS_G_

Z13

THS_G_

Z12

THS_G_

Z11

1. This bit must be set to ‘0’ for the correct operation of the device

THS_G_

Z10

THS_G_

Z9

THS_G_

Z8

THS_G_

Z7

THS_G_

Z6

Table 103. INT_GEN_THS_ZL_G register

THS_G_

Z5

THS_G_

Z4

THS_G_

Z3

THS_G_

Z2

THS_G_

Z1

THS_G_

Z0

Table 104. INT_GEN_THS_Z_G register description

Angular rate sensor interrupt thresholds on yaw (Z) axis.

THS_G_Z [14:0]

Default value: 0000000 00000000

Obsolete Product(s) - Obsolete Product(s)

Angular rate sensor interrupt generator duration register.

Table 105. INT_GEN_DUR_G register

WAIT_G DUR_G6 DUR_G5 DUR_G4 DUR_G3 DUR_G2 DUR_G1 DUR_G0

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LSM6DS1 Register description

WAIT_G

DUR_G [6:0]

Table 106. INT_GEN_DUR_G register description

Exit interrupt wait function enable. Default value: 0

(0: wait function off; 1: wait for DUR_G [6:0] samples before exiting interrupt)

Enter/exit interrupt duration value. Default value: 000 0000

The DUR_G [6:0] bits set the minimum duration of the interrupt event to be recognized. The duration steps and maximum values depend on the ODR chosen. the WAIT_G bit has the following meaning:

 ‘0’: the interrupt falls immediately if the signal crosses the selected threshold

 ‘1’: if the signal crosses the selected threshold, the interrupt falls after a number of samples equal to the value of the duration counter register.

For further details refer to

Figure 23 and

Figure 24

.

Figure 23. Wait bit disabled

• Wait bit = ‘0’ Interrupt disabled as soon as condition is no longer valid (ex: Rate value below threshold)

Rate

(dps)

0

Counter t(n)

Rate

Threshold

Interrupt t(n) t(n)

Duration

Value

“Wait”

Disabled

Obsolete Product(s) - Obsolete Product(s)

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Register description

Figure 24. Wait bit enabled

• Wait bit = ‘1’ Interrupt disabled after duration sample (sort of hysteresis)

LSM6DS1

Rate

(dps)

0

Rate

Threshold t(n)

Counter

Interrupt t(n)

Duration

Value

“Wait”

Enabled t(n)

Duration value is the same used to validate interrupt

These registers (16 bytes) are used to store data read from the slave devices.

Data7 Data6

Table 107. EXTERNAL_SENSORS_DATA register

Data5 Data4 Data3 Data2 Data1

Data [7:0]

Table 108. EXTERNAL_SENSORS_DATA register description

Data read from the slave device.

Data0

Synchronization of I

2

C master register.

INT1_MST

_DRDY

Table 109. MASTER_SYNC_REG register

FREE_

RUNNING

MST_trig1 MST_trig0 write_ slave_sel1 write_ slave_sel0

AUX_pull_ up

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LSM6DS1 Register description

FIFO_write_trig

INT1_MST_DRDY

Table 110. MASTER_SYNC_REG register description

When FIFO is enabled, this bit selects the synchronization strategy used to write data in FIFO. Default: 0

(0: synchronous with XL/GYRO;

1: synchronous with master)

When high data-ready signal of master is sent to INT1 pin. Default: 0

(0: disable; 1: enable)

This setting works properly if the

INT1_CTRL (0Ch) is set to 00h.

FREE_RUNNING Master operates in continuous mode. Default: 0

(0: trigger is needed to start the operation specified in FSM_cmd[2:0] in the

MASTER_FSM_REG (91h) register;

1: free running mode enable)

MST_trig[1:0] Master trigger mode selection. Default: 0

This setting works properly if the FREE_RUNNING bit is set to ‘0’.

(Refer to

Table 111 )

write_slave_sel[1:0] Selected bits to apply write operation on desired slave. Default: 0

(Refer to

Table 112 )

AUX_pull_up

Auxiliary master-to-slave line pull-up enable. Default: 0

(0: internal pull-up disable; 1: internal pull-up enable)

00

01

10

11

MST_trig[1:0]

Table 111. Master trigger mode configuration

Description

Master is off and state machine (FSM) is steady

State machine (FSM) of the master is synchronous with the data-ready signal of XL/GYRO.

State machine (FSM) is synchronous with an external signal coming from

TRIG_M pin.

Not used

Table 112. Slave address writing mode selection

Obsolete Product(s) - Obsolete Product(s)

00 Write operation is done on slave address

SLAVE0_I2C_ADD (B0h)

01

10

11

Write operation is done on slave address

SLAVE1_I2C_ADD (B8h)

Write operation is done on slave address

SLAVE2_I2C_ADD (BDh)

Not used

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Register description LSM6DS1

Master FSM register.

MASTER_

ON

1

(1)

PASS_

THROUGH

Table 113. MASTER_FSM_REG register

1

(1)

1. These bits must be set to ‘1’ for a proper functionality of the device.

1

(1)

FSM_cmd2 FSM_cmd1 FSM_cmd0

MASTER_ON

PASS_THROUGH

FSM_cmd[2:0]

Table 114. MASTER_FSM_REG register description

Enable master in sensor hub. Default: 0

(0: master disable; 1: master enable)

Enable pass-through mode. Default: 0

(0: pass-through mode disable; 1: pass-through mode enable: used to bypass the master of the sensor hub, connecting directly the main bus to the auxiliary bus.)

Select type of operation to be performed by master state machine (FSM). Refer to

Table 115

FSM_cmd [2:0]

000

010

011

100

Table 115. Master state machine type of operation

Description

Idle

Write

Read

Stop

Master status register.

Table 116. MASTER _STATUS_REG register

DATA_ DATA_

DATA_

ACK_ ARB_ BYTE_

0

(1) READY_ I2C_BUS

READY_G READY_XL STATUS LOST TRANSMISSION

MASTER

Obsolete Product(s) - Obsolete Product(s)

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LSM6DS1 Register description

DATA_READY_G

DATA_READY_XL

ACK_STATUS

I2C_BUS

ARB_LOST

BYTE_TRANSMISSION

Table 117. MASTER _STATUS_REG register description

DATA_READY_MASTER

Data-ready signal of gyroscope. Default: 0

(0: data is not ready to be transmitted; 1: a new set of data is ready to be transmitted)

Data-ready signal of accelerometer. Default: 0

(0: data is not ready to be transmitted; 1: a new set of data is ready to be transmitted)

Last read completed flag. Default: 0

(0: read is not complete; 1: read is complete)

Acknowledge signal during current transmission. Default: 0

(0: acknowledge found; 1: acknowledge not found)

I

2

C auxiliary bus status. Default: 0

(0: I

2

C stop sequence has been detected; 1: I

2

C start sequence has been detected)

Arbitration status of auxiliary bus. Default: 0

(0: master is communicating on the bus; 1: arbitration is lost)

Transmission status. Default: 0

(0: transmission is running; 1: transmission of an entire byte is complete)

I 2 C slave address of Slave 0 register.

Slave0_

I2C_add6

Slave0_

I2C_add5

Slave0_

I2C_add4

Table 118. SLAVE0_I2C_ADD register

Slave0_

I2C_add3

Slave0_

I2C_add2

1. These bits must be set to ‘0’ for a proper functionality of the device.

Slave0_

I2C_add1

Slave0_

I2C_add0

Slave0_I2C_add[6:0]

Table 119. SLAVE0_I2C_ADD register description

I

2

C slave address of Slave 0.

0

(1)

Sub slave address of Slave 0 register.

Obsolete Product(s) - Obsolete Product(s)

Slave0_ sub_add7

Slave0_ sub_add6

Slave0_ sub_add5

Slave0_ sub_add4

Slave0_ sub_add3

Slave0_ sub_add2

Slave0_ sub_add1

Slave0_ sub_add0

Slave0_sub_add[7:0]

Table 121. SLAVE0_SUB_ADD register description

Register address for Slave 0 device.

Register address of the first location to be read or written by the master (select proper operation with FSM_cmd[2:0] bits in the

MASTER_FSM_REG (91h) register.

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Register description LSM6DS1

Slave0_

DataW7

Slave 0 data to write register.

Slave0_

DataW6

Table 122. SLAVE0_DATA_TO_WRITE register

Slave0_

DataW5

Slave0_

DataW4

Slave0_

DataW3

Slave0_

DataW2

Slave0_

DataW1

Slave0_

DataW0

Table 123. SLAVE0_DATA_TO_WRITE register description

Slave0_DataW[7:0] Data byte to be written into Slave 0 at address specified in SLAVE0_SUB_ADD (B1h) .

Slave 0 configuration register.

Slave0_ polling_read

Swap_even

_odd

Start_restart

Table 124. SLAVE0_CONFIG register

Slave0_ rate4

Slave0_ rate3

Slave0_ rate2

Slave0_ rate1

Slave0_ rate0

Table 125. SLAVE0_CONFIG register description

Slave0_polling_read Start of polling routine for Slave 0 device. Default: 0

Read continuously Slave0, polling the register addressed by the bits specified in the

SLAVE0_SUB_ADD (B1h) register. If the content is different from 00h, it starts a burst read

from the next address and performs a number of reads equal to the value specified in the

Slave0_numop[3:0] bits in the

SLAVE0_BYTE_TO_READ (B7h) register.

(0: disable polling routine; 1: enable polling routine)

Swap_even_odd Exchange storage order of two bytes. Default: 0

(0: disable swap; 1: enable swap)

Start_restart Transition during a read operation between slaves. Default: 0

(0: I

2

C stop and start operation, the bus is free during the transition; 1: I

2

C restart operation, the bus is always busy).

Slave0_rate[4:0] Decimation of data storage frequency.

If the values are different from ‘0000’, the master uses the first trigger (XL/GYRO data-ready or the signal from TRIG_M) to perform the read operation and then jumps the number of triggers specified in these bits before the next read operation.

Obsolete Product(s) - Obsolete Product(s)

68/80 DocID025605 Rev 3

LSM6DS1 Register description

Slave 0 bytes to read register.

Slave0_on 0

(1)

Table 126. SLAVE0_BYTE_TO_READ register

0

(1)

0

(1)

Slave0_nu mop3

Slave0_ numop2

Slave0_ numop1

1. These bits must be set to ‘0’ for a proper functionality of the device.

Slave0_ numop0

Slave0_on

Table 127. SLAVE0_BYTE_TO_READ register description

Enable Slave 0 auxiliary communication channel. Default: 0

Use the Slave0_numop[3:0] bits in order to correctly map the slave device registers.

(0: Slave 0 not used; 1: Slave 0 used)

Slave0_numop[3:0] Number of bytes read during the read sequence.

Reads are performed on Slave 0 starting from the address specified in the

SLAVE0_SUB_ADD (B1h) register.

I 2 C slave address of slave 1 register.

Slave1_

I2C_add6

Slave1_I

2C_add5

Table 128. SLAVE1_I2C_ADD register

Slave1_

I2C_add4

Slave1_

I2C_add3

Slave1_

I2C_add2

1. These bits must be set to ‘0’ for proper functionality of the device.

Slave1_

I2C_add1

Slave1_

I2C_add0

Slave1_I2C_add[6:0]

Table 129. SLAVE1_I2C_ADD register description

I

2

C slave address of Slave 1.

0

(1)

Sub-slave address of Slave 1 register.

Table 130. SLAVE1_SUB_ADD register

Slave1_ Slave1_ Slave1_ Slave1_ Slave1_ Slave1_ Slave1_ Slave1_ sub_add7 sub_add6 sub_add5 sub_add4 sub_add3 sub_add2 sub_add1 Obsolete Product(s) - Obsolete Product(s)

Table 131. SLAVE1_SUB_ADD register description sub_add0

Slave1_sub_add[7:0] Register address for Slave 1 device.

Register address of the first location to be read or written by the master

(select proper operation with FSM_cmd[2:0] bits in the MASTER_FSM_REG

(91h) register.

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Register description LSM6DS1

Slave 1 data to write register.

Slave1_

DataW7

Slave1_

DataW6

Table 132. SLAVE1_DATA_TO_WRITE register

Slave1_

DataW5

Slave1_

DataW4

Slave1_

DataW3

Slave1_

DataW2

Slave1_

DataW1

Slave1_

DataW0

Table 133. SLAVE1_DATA_TO_WRITE register description

Slave1_DataW[7:0] Data byte to be written into Slave 1 at address specified in the

SLAVE1_SUB-

_ADD (B9h) register.

Slave 1 configuration register.

Slave1_ polling_read

Swap_ even_odd

Table 134. SLAVE1_CONFIG register

0

Slave1_ rate4

Slave1_ rate3

Slave1_ rate2

Slave1_ rate1

Slave1_ rate0

Slave1_polling_read

Table 135. SLAVE1_CONFIG register description

Start of polling routine for Slave 1 device. Default: 0

Read continuously Slave1 polling the register addressed by the bits specified in the

SLAVE1_SUB_ADD (B9h) register. If the content is different

from 00h, it starts a burst read from the next address and performs a number of reads equal to the value specified in the Slave1_numop[3:0] bits in the

SLAVE1_BYTE_TO_READ (BCh) register.

(0: disable polling routine; 1: enable polling routine)

Swap_even_odd

Exchange storage order of two bytes. Default: 0

(0: disable swap; 1: enable swap)

Slave1_rate[4:0] Decimation of data storage frequency.

If values are different from ‘0000’, the master uses the first trigger

(XL/GYRO data-ready or the signal from TRIG_M) to perform the read operation and then jumps the number of triggers specified in these bits before the next read operation.

Obsolete Product(s) - Obsolete Product(s)

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LSM6DS1 Register description

Slave 1 bytes to read register.

Slave1_on 0

(1)

Table 136. SLAVE1_BYTE_TO_READ register

0

(1)

0

(1)

Slave1_ numop3

Slave1_ numop2

Slave1_ numop1

1. These bits must be set to ‘0’ for a proper functionality of the device.

Slave1_ numop0

Slave1_on

Table 137. SLAVE1_BYTE_TO_READ register description

Enable Slave 1 auxiliary communication channel. Default: 0

Use the Slave1_numop[3:0] bits in order to correctly map the slave device registers.

(0: Salve 1 not used; 1: Slave 1 used)

Slave1_numop[3:0] Number of bytes read during the read sequence.

Reads are performed on slave 1 starting from the address specified in the

SLAVE1_SUB_ADD (B9h) register.

I 2 C slave address of slave 2 register.

Slave2_

I2C_add6

Slave2_

I2C_add5

Table 138. SLAVE2_I2C_ADD register

Slave2_

I2C_add4

Slave2_

I2C_add3

Slave2_

I2C_add2

1. These bits must be set to ‘0’ for proper functionality of the device.

Slave2_

I2C_add1

Slave2_

I2C_add0

Slave2_I2C_add[6:0]

Table 139. SLAVE2_I2C_ADD register description

I

2

C slave address of slave 2.

0

(1)

Sub-slave address of slave 2 register.

Table 140. SLAVE2_SUB_ADD register

Slave2_ Slave2_ Slave2_ Slave2_ Slave2_ Slave2_ Slave2_ Slave2_ sub_add7 sub_add6 sub_add5 sub_add4 sub_add3 sub_add2 sub_add1 Obsolete Product(s) - Obsolete Product(s)

Table 141. SLAVE2_SUB_ADD register description sub_add0

Slave2_sub_add[7:0] Register address for slave 2 device.

Register address of the first location to be read or written by the master

(select proper operation with FSM_cmd[2:0] bits in the

MASTER_FSM_REG

(91h)

register.

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Register description LSM6DS1

Slave 2 data to write register.

Slave2_

DataW7

Slave2_

DataW6

Table 142. SLAVE2_DATA_TO_WRITE register

Slave2_

DataW5

Slave2_

DataW4

Slave2_

DataW3

Slave2_

DataW2

Slave2_

DataW1

Table 143. SLAVE2_DATA_TO_WRITE register description

Slave2_DataW[7:0] Data byte to be written into Slave 2 at address specified in the

SLAVE2_SUB_ADD (BEh)

register.

Slave2_

DataW0

Slave 2 configuration register.

Slave2_ polling_read

Swap_ even_odd

Table 144. SLAVE2_CONFIG register

0

Slave2_ rate4

Slave2_ rate3

Slave2_ rate2

Slave2_ rate1

Slave2_ rate0

Slave2_polling_read

Table 145. SLAVE2_CONFIG register description

Start of polling routine for slave 2 device. Default: 0

Read continuously Slave2 polling the register addressed by the bits specified in the

SLAVE2_SUB_ADD (BEh) register. If the content is different

from 00h, it starts a burst read from the next address and performs a number of reads equal to the value specified in the Slave2_numop[3:0] bits in the

SLAVE2_BYTE_TO_READ (C1h) register.

(0: disable polling routine; 1: enable polling routine)

Swap_even_odd

Exchange storage order of two bytes. Default: 0

(0: disable swap; 1: enable swap)

Slave2_rate[4:0]

Decimation of data storage frequency.

If values are different from ‘0000’, the master uses the first trigger

(XL/GYRO data-ready or the signal from TRIG_M) to perform the read operation and then jumps the number of triggers specified in these bits before the next read operation.

Obsolete Product(s) - Obsolete Product(s)

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LSM6DS1 Register description

Slave 2 bytes to read register.

Slave2_on 0

(1)

Table 146. SLAVE2_BYTE_TO_READ register

0

(1)

0

(1)

Slave2_ numop3

Slave2_ numop2

Slave2_ numop1

1. These bits must be set to ‘0’ for a proper functionality of the device.

Slave2_ numop0

Slave2_on

Table 147. SLAVE2_BYTE_TO_READ register description

Enable Slave 2 auxiliary communication channel. Default: 0

Use the Slave2_numop[3:0] bits in order to correctly map the slave device registers.

(0: Slave 2 not used; 1: Slave 2 used)

Slave2_numop[3:0] Number of bytes read during the read sequence.

Reads are performed on Slave 2 starting from the address specified in the

SLAVE2_SUB_ADD (BEh)

register.

Routines for magnetometer register.

LIS3MD_

ODR

Table 148. MAGNETOMETER_ROUTINES register

LIS3MD_ wakeup

LIS3MDL_

ODR

LIS3MDL_ wakeup

0

(1)

1. These bits must be set to ‘0’ for proper functionality of the device.

0

(1)

0

(1)

0

(1)

Table 149. MAGNETOMETER_ROUTINES register description

LIS3MD_ODR Enables automatic routine for ST’s LIS3MD device. Default: 0

This routine activates the device in continuous mode at 100 Hz, the master’s read of the output registers is synchronous with the data-ready signal from the device.

(0: disable routine; 1: enable routine)

LIS3MD_wakeup Enable automatic routine for ST’s LIS3MD device. Default: 0

This routine is composed of a write synchronous with the XL/GYRO data-ready and by a read operation synchronous with the signal from TRIG_M (data-ready

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Register description LSM6DS1

LIS3MDL_ODR

LIS3MDL_wakeup

Enable automatic routine for ST’s LIS3MDL device. Default: 0

This routine activates the device in continuous mode at 80 Hz, the master’s read of the output registers is synchronous with the data-ready signal from the device.

(0: disable routine; 1: enable routine)

Enable automatic routine for ST’s LIS3MDL device. Default: 0

This routine is composed of a write synchronous with the XL/GYRO data-ready and by a read operation synchronous with the signal from TRIG_M (data-ready of the device)

(0: disable routine; 1: enable routine)

0

(1)

Offset_

Enable

Table 150. GYRO_OFS_XY_ON_OUT register

1

(2)

0

(1)

0

(1)

0

(1)

1. These bits must be set to ‘0’ for proper functionality of the device.

2. These bits must be set to ‘1’ for proper functionality of the device.

1

(2)

0

(1)

Offset_Enable

Table 151. GYRO_OFS_XY_ON_OUT register description

Define the values of the gyroscope to be stored in the pitch output registers

GYRO_OFS_PITCH_DATA_L/GYRO_OFS_PITCH_DATA_H (D0h, D1h) and

roll output registers

GYRO_OFS_ROLL_DATA_L/GYRO_OFS_ROLL_-

DATA_H (D2h, D3h) . Default: 0

(Refer to

Table 152 )

Table 152. Offset_Enable description

Description Offset_Enable

0

GYRO_OFS_PITCH_DATA_L/GYRO_OFS_PITCH_DATA_H (D0h, D1h) registers contain the gyro output data for the pitch axis; GYRO_OFS_ROLL_-

DATA_L/GYRO_OFS_ROLL_DATA_H (D2h, D3h) registers contain the gyro

output data for the roll axis

1

GYRO_OFS_PITCH_DATA_L/GYRO_OFS_PITCH_DATA_H (D0h, D1h) reg-

Obsolete Product(s) - Obsolete Product(s) ter and used to correct the gyro output data (

OUT_X_G (18h - 19h) registers);

GYRO_OFS_ROLL_DATA_L/GYRO_OFS_ROLL_DATA_H (D2h, D3h) regis-

ters contain the offset value for the roll axis calculated with the Kalmann filter and used to correct the gyro output data (

OUT_Y_G (1Ah - 1Bh) )

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LSM6DS1 Register description

Magnetometer configuration axes register.

FUNCTIONS_

EN

0

(1)

Table 153. MAG_CFG register

Mag_

SwapXY

MagX_ sign

MagY_ sign

1. These bits must be set to ‘0’ for proper functionality of the device.

MagZ_sig n

FUNCTIONS_EN

Mag_SwapXY

MagX_sign

MagY_sign

MagZ_sign

PR_sel_out

PR_sel_ out

0

(1)

Table 154. MAG_CFG register description

Enable for pitch/roll/heading computation blocks. Default: 0

(0: disable; 1: enable)

Swap XY magnetic axes for compass/heading computation. Default: 0

(0: disable swap; 1: enable swap)

Inversion of X magnetic axis for compass/heading. The inversion is done after XY swap. Default: 0

(0: disable inversion; 1: enable inversion)

Inversion of Y magnetic axis for compass/heading. The inversion is done after XY swap. Default: 0

(0: disable inversion; 1: enable inversion)

Inversion of Z magnetic axis for compass/heading. Default: 0

(0: disable inversion; 1: enable inversion

Send to registers PITCH_ANGLE_L/PITCH_ANGLE_H (CCh, CDh) and

ROLL_ANGLE_L/ROLL_ANGLE_H (CEh, CFh) the filtered pitch/roll

angles obtained by the Kalmann filter or by XL data. Default: 0

(0: pitch/roll angles from accelerometer; 1: pitch/roll angles filtered from the Kalmann filter)

6.67 PITCH_ANGLE_L/PITCH_ANGLE_H (CCh, CDh)

Output register of pitch angle obtained from tilt computation.

Output values are based on the PR_sel_out bit configuration in

MAG_CFG (CAh) . If

PR_sel_out is set to ‘0’, the value is expressed in 16-bit signed, wraparound. If PR_sel_out is set to ‘1’, the angle value is expressed in a 16-bit word in two’s complement with the same sensitivity of the gyroscope output data.

Obsolete Product(s) - Obsolete Product(s)

6.68 ROLL_ANGLE_L/ROLL_ANGLE_H (CEh, CFh)

Output register of roll angle obtained from tilt computation.

Output values are based on the PR_sel_out bit configuration in

MAG_CFG (CAh) . If

PR_sel_out is set to ‘0’, the value is expressed in 16-bit signed, wraparound. If PR_sel_out is set to ‘1’, the angle value is expressed in a 16-bit word in two’s complement with the same sensitivity of the gyroscope output data.

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Register description LSM6DS1

6.69 GYRO_OFS_PITCH_DATA_L/GYRO_OFS_PITCH_DATA_H

(D0h, D1h)

Output register of offset correction block of pitch angle. The value is expressed as a 16-bit word in two’s complement.

Output values are based on the Offset_Enable bit configuration in

GYRO_OFS_XY_ON_OUT (C9h)

6.70 GYRO_OFS_ROLL_DATA_L/GYRO_OFS_ROLL_DATA_H

(D2h, D3h)

Output register of offset correction block of roll angle. The value is expressed as a 16-bit word in two’s complement.

Output values are based on the Offset_Enable bit configuration in

GYRO_OFS_XY_ON_OUT (C9h)

6.71 HEADING_DATA_L/HEADING_DATA_H (D4h, D5h)

Output register of azimuth obtained from heading calculation block. The value is 10-bit unsigned right-aligned, wraparound.

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LSM6DS1 Soldering information

The LGA package is compliant with the ECOPACK ® , RoHS and “Green” standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com/mems .

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Package information LSM6DS1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

Figure 25. LGA 3x3x0.86 16L package outline and dimensions

ITEM

L e n g t h [ L ]

W i d t h [ W ]

H e i g h t [ H ]

Dimensions are in millimeter unless otherwise specified

General Tolerance is +/-0.1mm unless otherwise specified

OUTER DIMENSIONS

DIMENSION [mm]

3 .

0 0

3 .

0 0

0 .

8 6

TOLERANCE [mm]

± 0 .

1

± 0 .

1

M A X

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LSM6DS1 Revision history

Date

28-Nov-2013

31-Mar-2014

03-Nov-2014

Table 155. Document revision history

Revision Changes

1

2

3

Initial release

Updated Vdd to 2.2 V in

Section 2: Module specifications

Added

Section 6.32: INT2_GEN_SRC_XL (25h)

Updated

Section 6.33: INT1_GEN_SRC_XL (26h) and

Table 20:

Register mapping

Updated

Section 6.57: SLAVE1_CONFIG (BBh) and

Section 6.62: SLAVE2_CONFIG (C0h)

Updated

Table 49: CTRL_REG1_G register description and

Table 71: CTRL_REG6_XL register description

Updated SW_RESET bit in

Table 77: CTRL_REG8 register description

Updated dimensions and revised package presentation in

Section 8:

Package information

Updated footnote 2 of Table 2: Pin description

Obsolete Product(s) - Obsolete Product(s)

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LSM6DS1

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