STMicroelectronics VND5N07-E Datasheet
Advertisement
Advertisement
VND5N07-E
DPAK
TO-252
1
3
IPAK
TO-251
1
2
3
Features
Max. on-state resistance (per ch.) R
DS (on)
Current limitation (typ)
Drain-Source clamp voltage
I
LIMH
V
CLAMP
0.2
Ω
5 A
70V
OMNIFET II
fully autoprotected Power MOSFET
Datasheet
-
production data
Description
The VND5N07-E is a monolithic device designed using STMicroelectronics
®
VIPower
®
M0 technology, intended for replacement of standard
Power MOSFETs from DC to 50 KHz applications. Built-in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments.
Fault feedback can be detected by monitoring the voltage at the input pin.
• Linear current limitation
• Thermal shutdown
• Short circuit protection
• Integrated clamp
• Low current drawn from input pin
• Diagnostic feedback through input pin
• ESD protection
• Direct access to the gate of the power mosfet
(analog driving)
• Compatible with standard Power MOSFET
Table 1. Device summary
Order codes
Package
Tube
DPAK VND5N07-E
IPAK VND5N07-1-E
Tape and reel
VND5N07TR-E
September 2013
This is information on a product in full production.
DocID025077 Rev 2 1/22 www.st.com
Contents
Contents
VND5N07-E
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Overvoltage clamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overtemperature and short circuit protection . . . . . . . . . . . . . . . . . . . . . . 17
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
®
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/22 DocID025077 Rev 2
VND5N07-E
List of tables
List of tables
DocID025077 Rev 2 3/22
3
List of figures
List of figures
VND5N07-E
IN
IN
= 10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4/22 DocID025077 Rev 2
VND5N07-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1. Block diagram
DocID025077 Rev 2 5/22
21
Electrical specifications VND5N07-E
Stressing the device above the rating listed in
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to Absolute maximum rating conditions for extended periods may affect device reliability.
Symbol
V
DSn
V
INn
I
Dn
I
Rn
V
ESD
P tot
T j
T c
T stg
Table 2. Absolute maximum ratings
Parameter Value
Drain-Source voltage (V
INn
= 0 V)
Input voltage
Drain current
Reverse DC output current
Electrostatic discharge (R = 1.5 K Ω , C = 100 pF)
Total dissipation at T c
= 25°C
Operating junction temperature
Case operating temperature
Storage temperature
Internally clamped
18
Internally limited
-7
2000
60
Internally limited
Internally limited
-55 to 150
Unit
V
V
A
A
V
W
°C
°C
°C
Symbol
R thj-case
R thj-amb
Table 3. Thermal data
Parameter
Thermal resistance junction-case
Thermal resistance junction-ambient
Max. value
3.75
100
Unit
°C/W
°C/W
6/22 DocID025077 Rev 2
VND5N07-E Electrical specifications
T case = 25 °C unless otherwise stated.
Symbol Parameter
Table 4. Off
Test conditions Min.
Typ.
Max.
Unit
V
CLAMP
V
V
I
I
CLTH
ISS
INCL
DSS
Drain-Source clamp voltage
Zero input voltage drain current
(V
IN
= 0 V)
V
IN
Drain-Source threshold voltage
Supply current from input pin
V
V
IN
DS
= 0 V; I
D
Input-Source reverse clamp voltage
I
IN
= 1 mA
= 2 mA 55
= 0 V; V
IN
= 10 V 250 500
-1.0
-0.3
V
DS
= 0 V; I
D
= 200 mA 60
= 13 V; V
IN
= 0 V
70 80
50
V
DS
= 25 V; V
IN
= 0 V 200
V
V
µA
V
µA
µA
Table 5. On
(1)
Test conditions Symbol Parameter
R
DS(on)
Static drain-source on resistance
V
IN
=10 V; I
D
= 2.5 A
V
IN
= 5 V; I
D
= 2.5 A
V
IN(th)
Input threshold voltage V
DS
= V in
; I
D
+ I in
1.
Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
= 1 mA
Min.
Typ.
Max.
Unit
0.8
200
280
3 m Ω m Ω
V
Symbol Parameter
Table 6. Dynamic
Test conditions g fs
(1)
Forward transconductance
V
DS
= 13 V; I
D
= 2.5 A
C
OSS
Output capacitance V
DS
= 13 V; f = 1 MHz; V
1.
Pulsed: pulse duration = 300µs, duty cycle 1.5%.
IN
= 0 V
Min.
Typ.
Max.
Unit
3 4
200 300
S pF
Table 7. Switching
(1)
Test conditions Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
DD
V gen
= 15 V; I
D
= 10 V; R
= 2.5 A; gen
= 10 Ω
Min.
Typ.
Max.
Unit
50
60
150
40
100
100
300
80 ns ns ns ns
DocID025077 Rev 2 7/22
21
Electrical specifications
Table 7. Switching
(1)
Test conditions Symbol Parameter t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
V
DD gen
= 15 V; I
D
= 10 V; R
= 2.5 A; gen
= 1 k Ω
(dI/dt)
Q i on
Turn-on current slope
Total input charge
V
DD
V in
= 15 V; I
= 10 V; R
D
= 2.5 A; gen
= 10 Ω
V
DD
V
IN
= 12 V; I
= 10 V
D
= 2.5 A;
1.
Parameters guaranteed by design / characterization.
VND5N07-E
Min.
Typ.
Max.
Unit
150
400
250
600 ns ns
3900 5000 ns
1100 1600 ns
80 A/µS
18 nC
Table 8. Source drain diode
Symbol Parameter Test conditions
V
SD
(1) t
Q rr
(2) rr
(2)
Forward on voltage I
SD
= 2.5 A; V
IN
= 0 V
Reverse recovery time
Reverse recovery charge
I
SD
V
DD
= 2.5 A; dI/dt = 100 A/µs;
= 30 V
I
RRM
(2)
Reverse recovery current
1.
Pulsed: pulse duration = 300µs, duty cycle 1.5%.
2.
Parameters guaranteed by design / characterization.
Min.
Typ.
Max.
Unit
150
1.6
V ns
0.3
µC
5.7
A
Symbol
Table 9. Protections (-40°C < T j
< 150°C, unless otherwise specified)
Parameter Test conditions Min.
Typ.
Max.
Unit t
I lim dlim
(1)
Drain current limit
Step response current limit
V
IN
= 10 V; V
DS
= 13 V 3.5
V
IN
= 5 V; V
V
IN
= 10 V
V
IN
= 5 V
DS
= 13 V 3.5
T jsh
(1)
Overtemperature shutdown
T jrs
(1) reset
150
135
E
I gf
(1) as
(1)
Fault sink current
Single pulse avalanche energy
V
IN
= 10 V; V
DS
= 13 V
V
IN
= 5 V; V
DS
= 13 V
Starting T
V
IN j
= 25°C; V
DD
= 10 V; R gen
= 20 V;
= 1 k Ω ;
L = 10 mH
0.2
1.
Parameters guaranteed by design / characterization.
5
5
15
40
50
20
7
7
20
60
°C
°C mA mA
J
A
A
µS
µS
8/22 DocID025077 Rev 2
VND5N07-E Electrical specifications
Figure 2. Switching time test circuit for resistive load
Figure 3. Test circuit for diode recovery times
330 Ω
D
I
OMNIFET
S
B
A
FAST
DIODE
R gen
A
B
I
OMNIFET
D
L=100uH
V
DD
V gen
S
8.5
Ω
DocID025077 Rev 2 9/22
21
Electrical specifications
Figure 4. Unclamped inductive load test circuits
VND5N07-E
10/22
Figure 5. Input charge test circuit
V
IN
GEN
ND8003
DocID025077 Rev 2
VND5N07-E Electrical specifications
Figure 6. Unclamped inductive waveforms
Figure 7. Switching waveforms
DocID025077 Rev 2 11/22
21
Electrical specifications
Figure 8. Thermal impedance for DPAK / IPAK
VND5N07-E
12/22 DocID025077 Rev 2
VND5N07-E Electrical specifications
Figure 9. Source-drain diode forward characteristics
Figure 10. Static drain-source on resistance
Figure 11. Derating curve Figure 12. Static drain-source on resistance vs. input voltage
Figure 13. Normalized on resistance Vs temperature
Figure 14. Transconductance
DocID025077 Rev 2 13/22
21
Electrical specifications
Figure 15. Static drain-source on resistance Vs. Id
VND5N07-E
Figure 16. Switching time resistive load
Figure 17. Turn-on current slope
(V
IN
= 10 V)
Figure 18. Turn-on current slope
(V
IN
= 5 V)
Figure 19. Input voltage vs. input charge Figure 20. Turn-off drain source voltage slope
14/22 DocID025077 Rev 2
VND5N07-E
Figure 21. Turn-off drain-source voltage slope
Electrical specifications
Figure 22. Capacitance variations
Figure 23. Switching time resistive load Figure 24. Step response current limit
Figure 25. Output characteristics Figure 26. Normalized on resistance vs. temperature
DocID025077 Rev 2 15/22
21
Electrical specifications VND5N07-E
Figure 27. Normalized input threshold voltage vs. temperature
Figure 28. Normalized current limit vs. junction temperature
16/22 DocID025077 Rev 2
VND5N07-E Protection features
During normal operation, the INPUT pin is electrically connected to the gate of the internal
Power MOSFET.
The device then behaves like a standard Power MOSFET and can be used as a switch from
DC to 50KHz. The only difference from the user’s standpoint is that a small DC current I
ISS flows into the INPUT pin in order to supply the internal circuitry.
The device integrates:
3.2
3.3
Internally set at 70 V, along with the rugged avalanche characteristics of the Power
MOSFET stage give this device unrivaled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.
Linear current limiter circuit
Limits the drain current I
D
to I lim
whatever the INPUT pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T jsh
.
Overtemperature and short circuit protection
These are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 150 °C. The device is automatically restarted when the chip temperature falls below 135 °C.
In case of an overtemperature fault condition, a Status Feedback is provided through the
Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100
Ω
. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential.
Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in R
DS(on)
).
DocID025077 Rev 2 17/22
21
Package and packing information
4 Package and packing information
VND5N07-E
4.1 ECOPACK
®
packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
4.2 DPAK mechanical data
Figure 29. DPAK package dimensions
P032P
18/22 DocID025077 Rev 2
VND5N07-E
Dim.
D1
E
E1 e
G
H
L2
L4
R
V2
Package weight
B
B2
C
C2
D
A
A1
A2
Package and packing information
Table 10. DPAK mechanical data mm
Typ.
Min.
2.20
0.90
0.03
0.64
5.20
0.45
0.48
6.00
5.1
6.40
4.7
2.28
4.40
9.35
0.8
0.60
0°
0.2
8°
Gr. 0.29
Max.
2.40
1.10
0.23
0.90
5.40
0.60
0.60
6.20
6.60
4.60
10.10
1.00
DocID025077 Rev 2 19/22
21
Package and packing information
Figure 30. IPAK mechanical data and package outline
VND5N07-E
20/22
Symbol
B3
B5
B6
C
C2
D
A
A1
A3
B
B2
E
G
H
L
L1
L2
0.45
0.48
6
6.4
4.4
15.9
9
0.8
Table 11. IPAK mechanical data mm
Typ.
Min.
2.2
0.9
0.7
0.64
5.2
0.3
0.8
DocID025077 Rev 2
Max.
2.4
1.1
1.3
0.9
5.4
0.85
6.6
4.6
16.3
9.4
1.2
1
0.95
0.6
0.6
6.2
VND5N07-E
Date
01-Aug-2013
16-Sep-2013
Revision
Table 12. Document revision history
Changes
1
2
Initial release.
Updated disclaimer.
Revision history
DocID025077 Rev 2 21/22
21
VND5N07-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
22/22 DocID025077 Rev 2
Download
Public link updated
The public link to your chat has been updated. You may view and manage your chat links after registration here.
Document public link
Advertisement