STMicroelectronics L9952GXP Datasheet

L9952GXP

Power management system IC

Features

■

■

■

■

■

■

■

■

■

■

■

■

■

■

Two 5V low-drop voltage regulators (250mA,

100mA continuous mode

Low stand-by current: V

BAT stby, 7µA;

,

V

1 stby,

45µA, (75µA in cycl. sense)

Window watchdog and fail-safe output

Interrupt output

Wake-up logic with cyclic contact monitoring

LIN 2.1 compliant (SAEJ2602 compatible) transceiver

24 bit SPI interface for mode control and diagnostic

Output drivers

4 High side drivers for e.g. LED or HALL

(R

DSon,typ

= 7 Ω )

1 High side driver Out_HS ( R

DSon,typ

= 1 Ω )

2 Relay drivers ( R

DSon,typ

= 2 Ω )

Outputs are short circuit protected

2 Op amp's for current sensing in GND return lines

Temperature warning and thermal shutdown

Table 1.

Device summary

Package

PowerSSO-36

P o w e r S S O - 3 6

Applications

■ Automotive ECU’ s such as door zone and body control modules.

Description

The L9952GXP is a power management system

IC containing two low drop regulators with advanced contact monitoring and additional peripheral functions.

The integrated standard serial peripheral interface

(SPI) controls all L9952GXP operation modes and provides driver diagnostic functions.

Order codes

Tube

L9952GXP

Tape and reel

L9952GXPTR

September 2013 Doc ID 13518 Rev 6 1/68 www.st.com

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Contents

Contents

L9952GXP

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.1.1

2.1.2

Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2

Power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1

2.2.2

2.2.3

2.2.4

Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

V1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3

Wake up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4

Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5

Wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6

Hall sensor ports: WU3,4, Dig_Out 3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.7

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8

Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.9

Window – watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.10

Fail safe output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.11

Reset – generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.12

V1, V2 fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.13

Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.14

PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.15

Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.16

LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.17

Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.17.1

Dominant TxD time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.17.2

Short to battery time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.17.3

Short to ground mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.18

Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.18.1

Normal wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.18.2

Wake up from short to GND condition . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/68 Doc ID 13518 Rev 6

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L9952GXP

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Contents

2.18.3

RxD pin in V1 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.19

LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20.1

Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.20.2

Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.20.3

Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.20.4

Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.20.5

Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1

Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.1

3.1.2

Over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25

3.3

SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4

High side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.5

Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 30

6.3

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1

Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.2

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.3

Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.4

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.5

Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.6

Reset generator (V1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.7

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 13518 Rev 6 3/68

Contents

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9

10

L9952GXP

7.8

High side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.8.1

7.8.2

Output (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.9

Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.10

Wake up inputs ( WU1..WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.11

Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.12

LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.13

Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.14

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.14.1

Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.14.2

Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.14.3

Input PWM 2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.14.4

DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.14.5

DO, FSO, Dig_Out3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.14.6

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.14.7

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

SPI control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.1

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.1

ECOPACK

®

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.2

PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.3

PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4/68 Doc ID 13518 Rev 6

L9952GXP

List of tables

List of tables

Table 1.

Table 2.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pins definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10.

Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11.

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 12.

Power-on Reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 13.

Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 14.

Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 15.

Reset generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 16.

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 17.

High side outputs (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 18.

High side outputs (OUT 1..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 19.

Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 20.

Wake up inputs(WU1...WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 21.

Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 22.

LIN receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 23.

LIN DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 24.

LIN transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 25.

LIN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 26.

LIN DC values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 27.

Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28.

SPI (Input CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 29.

Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30.

Input PWM2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 31.

DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 32.

DO, FSO, Digout3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 33.

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 34.

CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 35.

SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 36.

Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 37.

Configuration bit HSxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 38.

Configuration bit OUT_HSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 39.

Configuration bit RELx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 40.

Configuration bit On_V2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 41.

Configuration bit TRIG, GO_VBAT, GO_V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 42.

Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 43.

Configuration bit Wx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 44.

Configuration bit Ux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 45.

Configuration bit Lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 46.

Configuration bit Txx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 47.

Configuration bit INT_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 48.

Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 49.

Configuration bit OLT_HSx, VSLOCK Out, O_HS_REC, LINPU and TXD_TOUT. . . . . . . 59

Doc ID 13518 Rev 6 5/68

List of tables L9952GXP

Table 50.

Configuration bit LEVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 51.

Configuration bit ICxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 52.

Configuration bit LIN slope, LS_ovuv and ICMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 53.

Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 54.

Configuration bit HSx_OL, HSx_OC and Relx_OC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 55.

Configuration bit SHT5V2, WUx, INH, LIN and Cold Start . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 56.

Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 57.

Configuration bit OV, UV, TW, TSDx and Vx Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 58.

Configuration bit STx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 59.

Configuration bit Rx, WDx, TRIG, SHT_GND, SHT_BAT and DOM_TXD . . . . . . . . . . . . . 63

Table 60.

PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 61.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6/68 Doc ID 13518 Rev 6

L9952GXP

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2.

Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 3.

Operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4.

Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5.

FSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6.

NReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 7.

Lin master pull up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8.

Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 9.

PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10.

PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area (V1 ON) . . . . . 32

Figure 11.

PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON) . . . . . . . . . . . . 32

Figure 12.

PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 13.

Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14.

Watchdog, closed and open window tolerances and save trigger area . . . . . . . . . . . . . . . 39

Figure 15.

LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16.

SPI - Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17.

SPI - Edges timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 18.

SPI - CSN low to high transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19.

SPI - High to low transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 20.

PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 21.

PowerSSO-36

tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 22.

PowerSSO-36

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Doc ID 13518 Rev 6 7/68

Pin definitions and functions

1 Pin definitions and functions

L9952GXP

Figure 1.

Block diagram

220nF

V2

V s

Voltage

Regulator 2

CAN

LIN

For detailed information see

EMC test report from

IBEE Zwickau

CAN

Microcontroller

ESDLIN1524BJ

Fail-safe Logic

CSN

CLK

DI

DO

Dig_Out3

Dig_Out4 /

Interrupt

TxD

RxD

LINPU

LIN

INH

220nF

V1

Wake Up IN

Voltage

Regulator 1

V s

Voltage

Monitor

PWM1

PWM2

NReset

Window

Watchdog

SPI

LIN 2.1 1)

SAEJ2602

WU3

1) LIN 2.1 certified

Wake Up IN

WU4

Wake Up IN

FSO

V

Bat

LOGIC

V s

GND

V

S

V

Bat

Temp Prewarning

& Shutdown

Undervoltage -

Overvoltage -

Shutdown

Low Side

Output Clamp

Low Side

Output Clamp

Rel1

R

Rel2

C

R

C

High Side

-

+

-

+

OP1+

OP1-

OP1out

OP2+

OP2-

OP2out

OUT_HS

µC (ADC)

M e. g. Bulb,

LED, Hall

Sensor

High Side

High Side

High Side

Out1

Out2

Out3 e. g. LED,

Hall Sensor

High Side

Wake Up IN

Wake Up IN

Out4

WU1

WU2

Cyclic Contact

Monitoring

Table 2.

Pin name

GND

Pins definitions and functions

PowerSS0-36

1

V2

V1

NReset

INH

RxD

2

3

4

5

6

Function

Ground

Voltage regulator 2 output : 5 V supply for external loads e.g. IR receiver, potentiometer

Voltage regulator 1 output : 5 V supply e.g. micro controller, Can transceiver

NReset output to micro controller - Internal pull-up of typ. 100K Ω

( reset state = low )

Wake-up input e.g. from CAN transceiver

Receiver output of the LIN 2.1 transceiver

8/68 Doc ID 13518 Rev 6

L9952GXP Pin definitions and functions

Table 2.

Pin name

Pins definitions and functions (continued)

TxD

OP2+

OP2-

OP2

OUT

DI

DO

CLK

CSN

PWM1

PWM2

Dig_Out3

Dig_Out4/INT

Wu

4..1

OP1

OUT

OP1-

OP1+

Out

4..1

Out_HS

Vs

LINPU

LIN

Rel1

Rel2

FSO

PowerSS0-36

31

32

33

34

35

23

24

25

9

10

11

7

8

12

13

14

15

16

17

18

19 to 22

26 to 29

30

36

Function

Transmitter input of the LIN 2.1 transceiver

Non inverting input of operational sense amplifier

Inverting input of operational sense amplifier

Output of operational sense amplifier

SPI : serial data input

SPI : serial data output

SPI : serial clock input

SPI : chip select not input

Pulse width modulation input

Pulse width modulation input

Digital output

Digital output (configurable as Interrupt Output)

Wake-up input: input pins for static or cyclic monitoring of external contacts

Output of operational sense amplifier

Inverting input of operational sense amplifier

Non inverting input of operational sense amplifier

High side driver (7 Ω, typ.) - to supply e.g. LED’ s, HALL sensors or external contacts

High side drivers (1 Ω, typ.) - to supply e.g. LED’ s, Bulbs, HALL sensors or external contacts

Power supply voltage

LIN master pull up

LIN bus line

Low side driver (2

Ω, typ.) - e.g. relay

Low side driver (2 Ω, typ.) - e.g. relay

Fail safe output - used to supervise or control applications in case of watchdog and/or V1 under-voltage failure (e.g. to activate emergency lights)

Doc ID 13518 Rev 6 9/68

Pin definitions and functions

Figure 2.

Pins configuration

GND 1

V 2 2

V1 3

NRESET 4

INH 5

RxD 6

TxD 7

OP2+ 8

OP2 9

OPOUT 2 10

DI 11

DO 12

CLK 13

CSN 14

PWM 1 15

PWM 2 16

Dig_Out 3 17

_ INT 18

PowerSSO - 36

L9952 GXP

TAB = GND

L9952GXP

36 FSO

35 REL 2

34 REL 1

33 LIN

32 LINPU

27

26

25

31 Vs

30

29

28

OUT _ HS

OUT

OUT

OUT

OUT

OP 1 +

24

23

OP 1 -

22

21

20

19

WU 1

WU 2

WU 3

WU 4

10/68 Doc ID 13518 Rev 6

L9952GXP

2 Description

Description

2.1.1

2.1.2

The L9952GXP contains 2 independent and fully protected low drop voltage regulators, which are designed for very fast transient response.

The output voltage is stable with loads capacitors > 220nF.

Voltage regulator: V1

The voltage regulator V1 provides 5V supply voltage and up to 250mA continuous load current for the external digital logic (micro controller, CAN transceiver ...). In addition the regulator V1 drives the L9952GXP internal 5V loads. The voltage regulator is protected against overload and over-temperature. An external reverse current protection has to be provided by the application circuitry to prevent the output capacitor from being discharged by negative transients or low input voltage. The output voltage precision is better than +/-2%

(incl. temperature drift and line-/load regulation) for operating mode; respectively +/-3% during low current mode. Current limitation of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load capacitors > 220nF.

If device Temperature exceeds TSD1 threshold, all outputs (Hsx, Lsx, V2, LIN) will be deactivated except V1. Hence the micro controller has the possibility for interaction or error logging. In case of exceeding TSD2 threshold (TSD2>TSD1), also V1 will be deactivated

(see state chart Fig. 3.1: “Protection and diagnosis”). A timer is started and the voltage regulator is deactivated for t

TSD

= 1sec. During this time, all other wakeup sources (CAN,

LIN, and WU1...4) are disabled. After 1 sec, the voltage regulator will try to restart automatically. If TSD2 occurs within one minute and for 8 consecutive times, the L9952GXP enters the V

BAT

- standby mode.

In case of short to GND at “V1” after initial turn on (V1 < 2V for at least 4ms) the L9952GXP enters the V

BAT

- standby mode. Reactivation (wake-up) of the device can be achieved with signals from CAN, LIN, WU1..4, SPI.

Voltage regulator: V2

The voltage regulator V2 supplies additional 5V loads (e.g. Logic components, external sensors, external potentiometers). The continuous load current is 50mA. The regulator provides accuracy better than + 3% @ 50mA (4% @ 100mA) load current.

In case of short to GND at “V2” after initial turn on (V2 < 2V for at least 4ms) the V2 regulator is switched off. Micro processor has to send a clear command to reactivate the V2 regulator.

V2 is protected against:

● Overload

●

●

●

Over temperature

Short circuit (short to ground and battery supply voltage)

Reverse biasing

Doc ID 13518 Rev 6 11/68

Description

2.2 Power control in operating modes

The L9952GXP can be operated in 4 different operating modes:

●

●

●

●

Active

Flash

V

1

- standby

V

BAT

- standby

A cyclic monitoring of wake-up inputs is available in stand-by modes.

L9952GXP

All functions are available.

Note:

To disable the watchdog feature a FLASH program mode is available.

The mode can be entered by V

PWM2

≥

9V

In this case all other functions are the same as in active mode

Watchdog can be disabled as well as soon as L9952GXP enters the V1 standby mode (see section 2.9 for details)

“High” level for flash mode selection is V

PWM2

≥

9V. For all other operation modes, standard

5V logic signals are required. For proper operation PWM 1 must not be set to a voltage level above standard 5V logic.

2.2.3 V

1 standby mode

Outputs and internal loads are switched off. To supply the micro controller in a low power mode, the voltage regulator1 (V1) remains active. The intention of the V1 standby mode is to preserve the RAM contents. A cyclic contact supply and wake-up input sense feature (for cyclic monitoring of external contacts) can be activated by SPI.

2.2.4 V

BAT standby mode

To achieve minimum current consumption during V

BAT standby mode, all L9952GXP functions (except the ones for wake up functionality) are switched off.

In V

BAT

- standby mode the current consumption of the L9952GXP is reduced to 7µA, typical

(without cyclic sense feature selected).

The transitions from active mode to either V

1

-standby or V

BAT

- standby are controlled by

SPI.

V

BAT

- standby mode is dominant; i.e. if both bits, V

1

- standby and V

BAT

- standby are set to

“1”, the L9952GXP will enter V

BAT

- standby mode.

12/68 Doc ID 13518 Rev 6

L9952GXP

2.3

Description

Wake up events

A wake-up from standby mode will switch the device to active mode. This can be initiated by one or more of the following sources:

●

●

●

Change of the LIN state at LIN bus interfaces

A current at the INH pin (I

≥

200uA) controlled by the CAN-transceiver (the CAN transceiver is not a part of the IC).

Positive/negative edge at wake up pins WU1...WU4 -> change of level after going into stand-by

●

●

Change of open-load state at OUT1 to 4

SPI access in V1-standby mode (CSN is low and first rising edge on CLK)

Table 3.

Wake up events

Wake up source Description

LIN

INH

WU1...4

Open Load at HS outputs

SPI Access

High level at PWM2 input

Always active

Always active

Can be individually disabled via SPI

Can be individually disabled via SPI

Always active

(except in V

BAT

- standby mode)

VPWM2 > 9V

(1)

1.

Only if internal oscillator is running (e. g. in cyclic sense configuration or after wake-up request).

All wake-up events (except wake-up by LIN, INH or SPI from V1standby mode) generate a

Reset pulse (NReset low for 2ms).

Wake-up events from V1standby by LIN, INH or SPI do not cause a Reset and the Reset generation is blocked for 2ms, i. e. a watchdog failure during this timeframe will not cause a reset.

Doc ID 13518 Rev 6 13/68

Description

2.4

L9952GXP

Functional overview (truth table)

Table 4.

Functional overview (truth table)

Operating modes

2.3.1

2.3.2

2.3.3

2.3.4

2.3.5

Function

Voltage-regulator, V1 VOUT= 5V

Voltage-regulator, V2 VOUT= 5V

Reset-generator

Window watchdog

Wake up

Comments

V

1

monitor

Active mode

On

On / Off

On

On

Off

(3)

(2)

V

1

-standby static mode

(cyclic sense)

On

(1)

On

(2)

/ Off

On

Off if

(I_V1 < I

CMP and I

CMP

=0) or I

CMP

= 1

Active

(4)

V

BAT

-standby static mode

(cyclic sense)

Off

On

(2)

/ Off

Off

Off

Active

(4)

2.3.6

HS-cyclic supply

Oscillator timebase

On / Off On

(2)

/ Off On

(2)

/ Off

2.3.7

2.3.11

Relay driver

2.3.8

Operational amplifiers

2.3.9

LIN line driver

2.3.10

LIN line receiver

FSO

LIN 2.1

Fail-safe output

On

On

On

On

Off

Off

Off

On

Off

Off

Off

On

Hi – no error

Lo – WD or V1 fail

On

Hi – no error

Lo – WD or V1 fail

(5)

(6)

On

(7)

Lo -> because

V1= off

(6)

(7)

2.3.12

2.3.13

Oscillator

Vs-Monitor

1.

Supply the processor in low current mode

2.

Only active when selected via SPI

3.

Input Status can be read by SPI (Status Register 0); Inputs should be configured for static sense (Control

Register 2)

4.

Unless disabled by SPI

5.

Watchdog is active in V1 standby mode, until I(V1) is below I

CMP

current threshold

6.

Activation = ON if cyclic sense is selected

7.

Cyclic activation = pulsed ON during cyclic sense

14/68 Doc ID 13518 Rev 6

L9952GXP

Figure 3.

Operating modes, main states

Description

Vbat startup

All registers cleared to ‚0',

Cold start bit (D19, SR0) set to ‚1'

Vs > Vpor

Vpwm2>9V

Flash Mode

Watchdog: OFF

Vpwm2<7V

Vpwm2>9V

Note 1

SPI command: ‚Go Vbat’ (D20 CR0)

OR

Thermal Shutdown

OR

V1 fail (V1 < 2,5V for 4ms after POR)

=> short to GND

Or

15 x WD Failure

Vpwm2>9V

Note 1

Wake-up

Event

Active

Mode

V1: on

Reset Generator: active

Watchdog: active

Fail Safe Out: active

Wake-up

Event

SPI command: ‚Go Vcc’

(D21 CR0)

Vbat Standby

Mode

V1: off

V2: according to SPI settings

Reset Generator: off (Nreset=low)

Watchdog: off

Fail Safe Out: low

HSD, LSD: Off

Thermal Shutdown TSD2

OR IV1 > 1mA AND ICMP = 0 AND 15 x WD fail

V1 Standby

Mode

V1: on

Reset Generator: active

Watchdog:

OFF (if Iv1<I cmp

or ICMP = 1)

Fail Safe Out: active

Note 1: only if internal oscillator is running

Doc ID 13518 Rev 6 15/68

Description

2.5

L9952GXP

Wake up inputs

The de-bounced digital inputs WU1...WU4 can be used to wake up the L9952GXP from standby modes. These inputs are sensitive to any level transition (positive and negative edge)

For static contact monitoring, a filter time of 64 µs is implemented at WU1-4. The filter is started when the input voltage passes the specified threshold. At Vin > 1V and Vin < (Vs –

2V), a Wake-up request is processed. During Wake-up request, the internal oscillator and other circuit blocks are activated in order to allow more accurate monitoring of the inputs.

In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a cyclic wake up feature is implemented. This feature allows periodical activation of the wakeup inputs to read the status of the external contacts. The periodical activation can be linked to Timer 1 (0.5sec to 4.0sec in 0.5sec steps) or Timer 2 (50ms). The input signal is filtered with a filter time of 16us after a programmable delay (80us or 800us). A Wake-up will be processed if the status has changed versus the previous cycle.

The Outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the timing according to the cyclic monitoring of the wake-up inputs.

If the wake-up inputs are configured for cyclic sense mode (Icxx in control register 2), the same input filter timing (Timer1 or Timer2) and the corresponding input filter delay (control register 2) must be used for the HS Outputs (Hsxx in control register 0) which supply the external contact switches.

In Standby mode, the inputs WU1-4 are SPI configurable for pull-up or pull-down current source configuration according to the setup of the external contacts (pull-up for active low contacts, pull-down for active high contacts). In active mode the inputs have a pull down resistor of 100 kOhm (typ).

In Active mode, the input status can be read by SPI (Status Register 0). Static sense should be configured (Control Register 2) before the read operation is started (In cyclic sense configuration, the input status is updated according to the cyclic sense timing; Therefore, reading the input status in this mode may not reflect the actual status).

2.6 Hall sensor ports: WU3,4, Dig_Out 3,4

Applications like Hall sensor outputs need high processing speed. The 12V signals connected to the wakeup inputs WU3 and WU4 can be looped through to the digital outputs

Dig_Out 3 and Dig_Out 4 (5V) in order to avoid read out of the input state by SPI.

The setup is programmable by SPI.

The open load states of the High Side Drivers OUT1 and OUT2 can be looped through the digital outputs Dig_Out3 and Dig_Out4 without delay. In addition, the status of OUT1 and

OUT2 can be accessed through the SPI interface. This feature is intended for 2-pin HALL sensors. Open Load information is only valid during ON state.

The Open Load threshold at pins OUT1...4 can be switched from I

OLD1

= 2mA to

I

OLD2

= 8 mA via SPI .

16/68 Doc ID 13518 Rev 6

L9952GXP Description

2.7 Interrupt

Dig_Out4 can be configured via SPI as Interrupt output (INT) by setting Bit 20 /

CR1:INT_enable=’1’.

This configuration will enable the following behaviour:

●

●

●

INT pin is pulled high for 2ms in case of any wake-up from V1 standby mode (WU inputs, LIN, INH, SPI, open load HS, Iv1 > I

CMP

_ris)

Wake-up events from V1 standby do not generate a reset (i.e. NRESET is not pulled low)

The Dig_Out4 settings in CR1 (Bits 12..14) will be ignored

2.8

Note:

2.9

Cyclic contact supply

In V1 and V

BAT - standby mode, any high side driver output (OUT1..4, OUTHS) can be used to periodically supply external contacts.

The timing is selectable by SPI

Timer 1: period is X sec, the on-time is 10ms resp. 20ms

With X

∈

{0.5, 1.0, 1.5, ... 4 }

Timer 2: period is 50ms, the on- time is 100us resp. 1ms:

Cyclic sense setup: if cyclic sense feature is used for wake-up inputs (Icxx in control register

2), same input filter timing (Timer1 or Timer2) must be used for HS Outputs (Hsxx in control register 0).

Window – watchdog

During normal operation the watchdog monitors the micro controller within a nominal trigger cycle of 10ms.

In V

BAT

-standby

,

V1-standby and Flash program modes, the watchdog circuit is automatically disabled. However, the watchdog will remain enabled in V1-standby mode until the current at V1 decreases below I

CMP

_fall. The V1 current monitoring can be disabled, if the I

CMP

bit (CR2, D20) is set to '1'.

After ‘power-on’, ‘standby mode’ or reset, the window watchdog starts with a long open window (65ms). The long open window allows the micro controller to run its own setup and then to trigger the watchdog via the SPI. The trigger is finally accepted when the CSN input becomes HIGH after the transmission of the SPI word.

A correct watchdog trigger will start the window watchdog with a closed window (< 6ms) followed by an open window (< 10ms), see timing diagrams. Subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit (CR0, D19). The

“negative” or “positive” edge has to meet the open window time. A correct watchdog trigger signal will immediately start the next closed window.

After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. In case of

7 further watchdog failures, the V1 regulator is completely turned off and the device goes into V

BAT standby mode until a wakeup occurs. (e.g. via LIN, CAN/INH).

Doc ID 13518 Rev 6 17/68

Description

Note:

L9952GXP

The watchdog is triggered by toggling the trigger bit (CR0, D19).

The active trigger window will be reset after each correct trigger write operation.

In case of reset (NReset low for 2ms) the trigger bit is set to “0”.

In case of a WD failure, the outputs (Lsx, Hsx, V2) are switched off and NReset is pulled low for 2ms.

Writing to control register 0 without inverting the WD trigger bit is possible at any time.

Figure 4.

Watchdog

Watchdog Failure

Reset

Wake up event t=200ms

V1 off for 200 ms

Vbatstdby

Mode

8+7

WD Failures

8x WD Failure

(Nreset =low for 2ms)

LSD: Off (control bits set to ‚0')

HSD: Off (control bits remain unchanged)

Toggle WD Trigger Bit

Within nominal window

Watchdog active

With

Normal window

(10ms)

HSD, LSD : according to

CR0

Watchdog Failure (‚long open window’ passed without TRIG=1

2ms

Set WD Trigger Bit = ‚1' or toggle trigger bit if wake-up from V1standby

Power-on

Reset

Wake-up event or exit Flash Mode

Go to standby mode or

Flash Mode (PWM2>9V)

Watchdog active with

‚long open window’

(65ms nom )

HS and LS outputs are off

Go to standby mode or Flash Mode (PWM2>9V)

Set

WD Trigger Bit = ‚0' or write non-inverting value to trigger bit after wake-up from

V1standby mode

INH, LIN, SPI

I(V1)>1mA and ICMP=0

Watchdog

Inactive

(standby modes,

Flash Mode)

18/68 Doc ID 13518 Rev 6

L9952GXP Description

After power-on (Vs > V

POR

) or wakeup from V

BAT

-standby mode, the output FSO is set to

“HIGH”, if V1 is above the V1 threshold. FSO is set to “LOW” in case of V1 under voltage or watchdog failure.

During V1-standby mode, FSO is HIGH unless a V1 under-voltage or watchdog reset occurs. WD remains enabled in V1 standby mode until I

V1

drops below 150uA. In V

BAT

standby mode, FSO is low. At exit from V

BAT

- standby mode, it goes to high as soon as V1 is stable.

At wakeup FSO remains high, provided that the watchdog is triggered successfully. It is set low if the watchdog is not served during the long open window of if a V1 under-voltage occurs.

Figure 5.

FSO

V1 undervoltage

TSD2

Watchdog Failure

Vbatstdby Mode

FSO = 0

2.11 Reset – generator

IF V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output

“NRESET” is switched to “HIGH” after a 2ms reset delay time. This is necessary for a defined start of the micro controller when the application is switched on.

As soon as an under voltage condition of the output voltage (V1 < VRT) for more than 8us appears, the reset output is switched low again.

Figure 6.

NReset

Wake-up Event 1)

V1 Undervoltage

Vpwm2 < 9V

(Exit Flash Mode)

Watchdog

Failure

NReset = 0

1) Only if

(INT_en = 0) and (wake-up by WU-input or High Side Open Load)

Doc ID 13518 Rev 6 19/68

Description L9952GXP

2.12 V1, V2 fail

The V

1, and V

2

regulator output voltages are monitored.

In case of a drop below the V

1,

V

2

– fail thresholds (V

1,2

< 2V,typ for t > 2us), the V

1,2

- fail bits are latched. The fail bits are cleared by a dedicated SPI command.

If 4ms after turn on of the regulator the V

1,2 voltage is below the V

1,2

fail thresholds,

(independent for V1,2 ), the L9952GXP will identify a short circuit condition at the related regulator output and the regulator will be switched off.

In case of a V1 failure the device enters V

BAT

- standby mode automatically.

In case of a V2 failure the SHT5V2 bit (SR0 Bit12) is set.

2.13 Low side driver outputs Rel1, Rel2

The outputs Rel1, Rel2 (R

DSon

= 2 Ω typ. @25 ° C) are specially designed to drive relay loads.

Typical relays used have the following characteristics:

Relay type 1:

– closed armature: R = 160

Ω

+10%, L= 300mH

– open armature: R = 160 Ω +10%, L= 240mH

Relay type 2:

– closed armature: R= 220

Ω

+10%, L= 420mH

– open armature: R= 220 Ω +10%, L= 330mH

The outputs provide an active output zener clamping (40V) feature for the demagnetisation of the relay coil, even though a load dump condition exists. In case of watchdog failure the relay drivers will be switched off and the low side driver control bits are cleared.

Note: 1 Due to relays bouncing, high dV/dt and/or dI/dt transients may occur on the low side driver outputs. In case high currents are switched (for example window lift motor), due to parasitic capacitive inductive coupling from load side of relays to the relays coils, the Absolute

Maximum Ratings of the Low Side driver outputs may be exceeded. In order to avoid this, it is recommended to place a 10nF capacitor at the Rel1, Rel2 outputs to GND.

2 If a hard short circuit to V

BAT required with T

RC is possible at the "Low Side Driver" outputs, an RC network is

> 1µs, R ≥ 1 Ω (see block diagram, the value is given for an output short circuit of given di/dt = 5A/µs).

The inputs PWM 1,2 can be used to control the output drivers Out1..4 and OUT_HS with a

PWM signal. Each PWM input can be mapped individually to each of the above listed outputs according to the SPI settings.

20/68 Doc ID 13518 Rev 6

L9952GXP Description

The operational amplifiers are especially designed to be used for sensing and amplifying the voltage drop across ground connected shunt resistors. Therefore the input common mode range includes - 0.2 ... 3V.

The operational amplifiers are designed for GND + 3V... GND – 0.2V input voltage swing and rail-to-rail output voltage range. All Pins (positive, negative and outputs ) are available to be able to operate in non-inverting and inverting mode. Both operational amplifiers are on-chip compensated for stability over the whole operating range within the defined load impedance.

Figure 7.

Lin master pull up

Vs

LIN c o n t r o l

T

S W

LIN P U c o n t r o l

3 0 k

LIN

1 k

M a s t e r n o d e p u ll u p

Gn d

A dedicated built-in switch “Tsw” enables the LIN to act as a master. (see chapter 2.18)

General requirements:

● Speed communication up to 20kbit/s

●

●

LIN 2.0 compliant (SAEJ2602 compatible) transceiver

Function range from +40V to -18V DC at LIN Pin

●

●

●

●

GND disconnection fail safe at module level

Off mode: does not disturb network

GND shift operation at system level

Microcontroller Interface with CMOS compatible I/O pins.

●

●

●

Pull up resistor internal.

ESD: immunity against automotive transients per ISO7637 specification (see application note)

Matched output slopes and propagation delay

In order to further reduce the current consumption in standby mode, the integrated LIN bus interface offers an ultra low current consumption.

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22/68

Description L9952GXP

The L9952GXP provides the following 3 error handling features which are not described in the LIN Spec. V2.1, but are realized in different stand alone LIN transceivers / micro controllers to switch the application back to normal operation mode.

2.17.1 Dominant TxD time out

If TXI is in dominant state (low) for more than 12ms (typ) the transmitter will be disabled until

TXI becomes recessive (high). This feature can be disabled via SPI.

2.17.2 Short to battery time out

If TXI changes to dominant (low) state but RXI signal does not follow within 40 µ s, the transmitter will be disabled until TXI becomes recessive (high).

2.17.3 Short to ground mode

A wake up caused by a message on the bus will start the voltage regulator and the micro controller to switch the application back to normal operation mode.

2.18 Wake up (from LIN)

In standby mode the L9952GXP can receive a wake up from LIN bus. For the wake up feature the L9952GXP logic differentiates two different conditions.

Normal wake up can occur when the LIN transceiver was set in standby mode while LIN was in recessive (high) state. A dominant level at LIN for at least 40µs, will switch the

L9952GXP to active mode.

2.18.2 Wake up from short to GND condition

If the LIN transceiver was set in standby mode while LIN was in dominant (low) state, recessive level at LIN for at least 40us, will switch the L9952GXP to active mode.

2.18.3 RxD pin in V1 standby

In V1 standby condition the RxD is a tristate pin.

Doc ID 13518 Rev 6

L9952GXP Description

2.19 LINPU

The LINPU (LIN pull up) signal is set by L9952GXP logic in order to drive the LIN transceiver in master mode. The master mode is realized by an internal high side switch and an external diode in series with an external 1k resistor. In master mode the high side switch is closed causing an external pull up path in parallel to the internal one (diode & 30k resistor).

HS (high side) characteristics:

● HS does not have an over current protection.

●

●

●

The HS remains active in standby mode.

Switch off only in case of over temperature (TSD2 = thermal shutdown #2).

Typical R

DSon

, 10

Ω.

The Linpu is activated by default (LIN master mode) and can be switched off with a SPI command (see register 2) to reduce current in case of LIN shorted to ground.

2.20 Serial Peripheral Interface (SPI)

Note:

A 24 bit SPI command (2 adresses + 22 data bits) is used for bi-directional communication with the micro controller.

During active mode, the SPI:

1) triggers the watchdog

2) controls the modes and status of all L9952GXP modules (incl. input and output drivers)

3) provides driver output diagnostic

4) provide L9952 diagnostic (incl. over temperature warning, L9952GXP operation status)

During stand-by modes, the SPI is generally deactivated.

The SPI can be driven by a micro controller with its SPI peripheral running in following mode:

CPOL=0 and CPHA=0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to micro controller with a build-in SPI. Only three CMOScompatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the global error flag (fault condition) of the device which is a logical -”OR” of all over current, Vsover / under voltage, temperature warning/shutdown and V1 Fail bits. The micro controller can poll the status of the device without the need of a full SPI-communication cycle.

2.20.1 Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal activates the output driver and a serial communication can be started. The state during CSN = 0 is called a communication frame.

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Description L9952GXP

2.20.2 Serial Data In (DI)

Note:

The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.

At the rising edge of the CSN signal the contents of the shift register will be transferred to

Data Input Register. The writing to the selected Data Input Register is only enabled if exactly

24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.

2.20.3 Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag (fault condition).

The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. The SPI can be driven with a CLK frequency up to 1MHz.

The device has 3 Control registers and 2 Status registers. The first two bits (D22+D23) at the DI-Input are used to select one of the Control registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Control register only if a frame of exact 24 bits is detected. If the

Control register 1 is selected for data transfer, the Status register 1 will be transferred to the

DO during the current communication frame. For the selection of Control register 0 or

Control register 2, the Status register 0 is transferred to DO.

Doc ID 13518 Rev 6

L9952GXP

3 Protection and diagnosis

3.1 Power supply fail

Over and under-voltage detection on Vs.

Protection and diagnosis

If the supply voltage Vs reaches the over voltage threshold (V

SOV

)

● The outputs HS1..4, OUT_HS, Rel1,2, and LIN are switched to high impedance state

(load protection)

● The over voltage bit is set and can be cleared with the clear bit (CR1,CLR)

● Automatic recovery after Vs over-voltage; selectable via SPI (CR2, bit4)

3.2

If the supply voltage Vs drops below the under voltage threshold voltage(V

SUV

)

● The outputs HS1..4, OUTHS, Rel1,2, and LIN are switched to high impedance state

(load protection)

● The under voltage bit is set

● Automatic recovery after Vs under-voltage; selectable via SPI (CR2, bit4)

Temperature warning and thermal shutdown

See state chart: “ Protection and diagnosis”.

Digital diagnosis features are provided by SPI:

● V1 reset threshold programmable

●

●

Over temperature including pre warning

Open load separately for each output stage

●

●

●

●

Overload status

Vs-supply over/under voltage

V1 and V2 fail bit

Status of the WU1...4, LIN and INH pin

●

●

●

●

●

Cold start bit

Number of unsuccessful V1 restarts after thermal shutdown

Number of sequential watchdog failures

Status of watchdog trigger bit TRIG: (SR1, Bit 16)

LIN status (short to ground, short to V

BAT

, dominant TxD)

See the following state chart: “Protection and diagnosis”.

Doc ID 13518 Rev 6 25/68

26/68

Protection and diagnosis

Figure 8.

Protection and diagnosis

TSD2

All outputs: off

V1: off for 1 sec

‚TSD2-bit is set (D4 SR1)

8x TSD2

(each TSD2 within 1 min)

Tj > 155°C

T > 1sec

TSD1

All outputs except V 1: off

‚TSD 1'-Bit is set(D3 SR1)

L9952GXP

Tj > 140°C

Vbatstdby

All outputs incl V 2: off

Power-on reset

Wake-up event

SPI command: ‚CLR’

(D21 CR1)

OR

Power-on reset

Temperature

Warning

SPI command: ‚CLR’

(D21 CR1)

OR

Power-on reset

‚Temperature Warning'-

Bit set

(D2 SR1)

Tj > 130°C

Active

Mode

Standby Modes

(during cyclic sense )

Vs Undervoltage

Vs Overvoltage

SPI command: ‚CLR’

(D21 CR1)

OR

Autorestart activated

(D4 CR2)

SPI command: ‚CLR’

(D21 CR1)

OR

Autorestart activated

(D4 CR2)

Vs Lockout

All outputs: high Impedance

OV Bit set (D0 SR1)

Auto-restart if selected by SPI

Vs Lockout

All outputs: off

UV bit set (D1 SR1)

Auto-restart if selected by SPI

8 successive watchdog failures

V1 off for

200ms

7 additional watchdog failures in sequence

Vbatstdby mode

Doc ID 13518 Rev 6

L9952GXP

3.4

Note:

Protection and diagnosis

High side driver outputs

The component provides a total of 4 high side outputs Out1...4, (7

Ω typ. @ 25C) to drive e.g. LED' s or hall sensors and 1 high side output OUT_HS with 1

Ω typ. @ 25 C).

The high side outputs are protected against

● Over- and under voltage

●

●

Overload (short circuit)

Over temperature with pre warning

If the output current exceeds the current shutdown threshold the output transistor is turned off and the corresponding diagnosis bit of the output is set.

The switches are automatically disabled in case of reset condition, Vs-under, Vs-over voltage or thermal shutdown (TSD1&2).

For OUT_HS an auto recovery feature is available in active mode.

If the OUT_HS output current exceeds the current shutdown threshold, the output transistor is turned off and the corresponding diagnosis bit of the output is set.

Via SPI command the auto recovery feature can be enabled in order to restart the driver in case of over current shutdown. This over current recovery feature is intended for loads which have an initial current higher than the over current limit of the output (e.g. Inrush current of cold light bulbs).

The device itself can not distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example, the micro controller can switch on light bulbs by setting the over current recovery bit for the first 50ms.

After clearing the recovery bit, the output will be automatically disabled if the overload condition still exists.

The status of all high side outputs (over-current, open load) can be monitored by SPI interface.

In case of a watchdog failure, the high side drivers are switched off. The control bits are not cleared, i.e. the drivers will go to the previous state once the watchdog failure condition disappears.

ESD structures are configured for nominal currents only. If external loads are connected to different grounds, the current load must be limited to this nominal current.

Loss of ground or ground shift with externally grounded loads.

3.5 Low side driver outputs Rel1, Rel2

The outputs provide an active output zener clamping feature for the demagnetisation of the relay coil, even though a load dump condition exists. For safety reasons the relay drivers are linked with the Watchdog: in case of failure, or missing trigger signal the relay drivers will switch off.

Doc ID 13518 Rev 6 27/68

28/68

Absolute maximum ratings L9952GXP

Note:

Table 5.

Absolute maximum ratings

Symbol Parameter

V

S

V

1

DC supply voltage / “jump start”

Single pulse / t max

< 400 ms

“transient load dump”

Stabilized supply voltage, logic supply

Stabilized supply voltage V

2

V

DI

V

CLK

V

TXD

V

CSN

V

DO

V

RXD

V

NRESET

V

FSO

V

DIGOUT3,4

V

INH

V

PWM1,

V

PWM2,

V

REL1,

V

REL2,

V

OUT1..4,,

V

OUTH

V

WU1...4,

V

OP1+,

V

OP1-,

V

OP2+,

V

OP2-,

V

OPOUT1,

V

OPOUT2

V

LIN,

V

LINPU

I

Input

Logic input / output voltage range

Wake up input voltage range

PWM input voltage range

Low side output voltage range

High side output voltage range

Wake up input voltage range

Opamp1 input voltage range

Opamp2 input voltage range

Analog Output voltage range

LIN bus I/O voltage range

Current injection into Vs related input pins

Value

-0.3 to +28

-0.3 to +40

-0.3 to +5.25

-0.3 to +28

-0.3 to V1+0.3

-0.3 to +40

-0.3 to V

S

+ 0.3

-0.3 to V

S

+ 0.3

-0.3 to V1 + 0.3

-0.3 to V

S

+ 0.3

-20 to +40

5

Unit

V

V

V

V

V

All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit !

V

V

V

V

V

V mA

Doc ID 13518 Rev 6

L9952GXP ESD protection

Table 6.

ESD protection

Parameter

All pins, except LIN

(1)

All output pins

(2)

LIN

(3)

LIN

(4)

Value

+/- 2

+/- 4

+/- 1.5

Unit kV kV kV

+/- 8 kV

All pins (charge device model) +/- 500 V

Corner pins (charge device model)

All pins

(5)

+/- 750

+/- 200

V

V

1.

HBM (human body model, 100pF, 1.5 k

Ω

) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A

2.

HBM with all none zapped pins grounded

3.

Without external components

4.

Acc. DIN EN61000-4-2 (330

Ω, 150 pF), with external components:

- Diode, type ESDLIN1524BJ

- SMD Ferrite bead, type TDKMMZ2012Y202B

- Capacitor C=220pF

For detailed information please see EMC report from IBEE Zwickau (available on request)

5.

Acc. Machine Model: C=220pF; L=0.75µH; R=10

Ω

Doc ID 13518 Rev 6 29/68

Thermal data L9952GXP

6.1

6.2

Operating junction temperature

Table 7.

Item

6.1.1

6.1.2

Operating junction temperature

Symbol Parameter

Tj Operating junction temperature

RthjA Thermal resistance junction- ambient

Value

- 40 to 150

See

Figure 10.

Unit

°C

°C/W

Temperature warning and thermal shutdown

Table 8.

Item

6.2.1

6.2.2

Temperature warning and thermal shutdown

Symbol Parameter

T

W ON

T

SD1 OFF

Thermal over temperature warning threshold

Thermal shutdown junction temperature 1

T j

(1)

T j

(1)

T j

(1)

6.2.3

6.2.4

6.2.5

T

SD2OFF

T

SD2 ON

T

SD12hys

1.

Non-overlapping

Thermal shutdown junction temperature 2

Hysteresis

Min.

120

130

140

Typ.

Max.

Unit

130 140 °C

140 150 °C

155 170 °C

5 °C

30/68 Doc ID 13518 Rev 6

L9952GXP

6.3 Package and PCB thermal data

Figure 9.

PowerSSO-36 PC board

Thermal data

Note: Layout condition of R th

and Z th

measurements ( board finish thickness 1.6 mm +/- 10% board double layer, board dimension 129x60, board Material FR4, Cu thickness 0.070mm

(front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm ).

Doc ID 13518 Rev 6 31/68

Thermal data L9952GXP

Figure 10. PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area

(V1 ON)

RTHj _amb( ° C/ W)

110

90

70

50

30

0 2 4 6

PCB Cu heat sink area ( cm^ 2)

8 10

Figure 11. PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON)

ZTH ( ° C/ W)

1000

100

Footprint

2 cm

2

8 cm

2

10

1

0,1

0,01 0,1 1

Time ( s)

10 100 1000

32/68 Doc ID 13518 Rev 6

L9952GXP

Equation 1: pulse calculation formula

Z

TH δ

= R

TH where

δ

= t

P

/T

⋅ δ

+ Z

THtp

(

1 –

δ )

Figure 12. PowerSSO-36 thermal fitting model (V1 ON)

Thermal data

Table 9.

Thermal parameters

Area/island (cm

2

)

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

Footprint

0,0003

0,35

1,5

5

5

18

29

51

2

1

1,3

15

10

22

29

8

1

1,3

15

10

7,8

21

Doc ID 13518 Rev 6 33/68

Electrical characteristics L9952GXP

7.1 Supply and supply monitoring

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V

S unless otherwise specified.

< 18V; 4.8V < V1 < 5.2V; all outputs open; T j

= -40°C...130°C,

Table 10.

Supply and supply monitoring

Item Symbol Parameter

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

7.1.7

7.1.8

7.1.9

7.1.10

7.1.11

V

S

V

SUV

V hyst_UV

V

SOV

V hyst_OV

I

V(act)

I

V(BAT)

I

V(BAT)CS

I

V(V1)

I

V(BATWU)

I

V(V1WU)

Test condition Min.

Typ.

Max.

Unit

Supply voltage range 6 13.5

18 V

VS UV-threshold voltage

V

S

increasing / decreasing

5.11

5.81

V

Undervoltage hysteresis

VS OV-threshold voltage

Overvoltage hysteresis

Current concumption in active mode

Current consumption in

V

BAT

- standby mode

V

S

increasing / decreasing

Hysteresis

Vs=12V, TxD LIN high, V2 on,

Outputs off

Iv1=Iv2=0A

V

S

=12V, both voltage regulators deactivated, no wake-up request

Current consumption in

V

BAT

- standby mode

Current consumption in

V

1

-standby mode

V

S

=12V, both voltage regulators deactivated, (cyclic sense)

V1=5V, V

S

=12V,

Voltage regulator

V1 active, without cyclic sense, no wake-up request

Current consumption in

V

BAT

-standby mode with a pending wake up request

1.5V<V

WU

<(Vs-3V)

Current consumption in

V

1

- standby mode with a pending wake up request

1.5V<V

WU

<(Vs-3V)

0.04

0.1

0.15

V

18

0.5

1

40

10

1

2.7

7

75

45

220

300

22

1.5

20

10

100

70

320

410

V

V mA

µA

µA

µA

µA

µA

34/68 Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

7.2 Oscillator

6V < V

S

< 18V; all outputs open; T j

= -40°C...130°C, unless otherwise specified.

Table 11.

Oscillator

Item Symbol

7.2.1

F

CLK

Parameter

Oscillation frequency

Test condition

Vs = 6V...18V

Min.

Typ.

Max.

Unit

0.808

1.01

1.35

MHz

7.3 Power-on reset (Vs)

All outputs open; T j

= - 40°C...130 °C, unless otherwise specified.

Table 12.

Power-on Reset (Vs)

Item Symbol Parameter

7.3.1

V

THUP_POR

7.3.2

V

Hys_POR

V

POR

threshold

Hysteresis

Test condition Min.

Typ.

Max.

Unit

2.8

3.45

4.1

200

V mV

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 5.25V < V

S

< 27V; T j

= -40°C...130°C, unless otherwise specified.

Table 13.

Voltage regulator V1

Item Symbol Parameter

7.4.1

Test condition Min.

Typ.

Max.

Unit

7.4.2

7.4.3

7.4.4

7.4.5

7.4.6

7.4.7

V1

V1

Vhc1

VSTB1

Output voltage

Output voltage tolerance

Active mode

I

LOAD

= 1mA...

100mA,

VS = 13.5V

Output voltage tolerance

Active mode, high current

I

LOAD

= 100mA ...

250mA,

VS = 13.5V

Output voltage tolerance in low current mode

I

LOAD

= 250mA

VS = 13.5V,

T j

>80°C

0mA < I

LOAD

< I

CMP

VS = 13.5V

VDP1

ICC1

Drop-out voltage in undervoltage conditions

Output current in active mode

I

LOAD

= 50mA,

V

S

= 4.5V

I

LOAD

= 100mA,

V

S

=4.5V

Max. continuous load current

ICCmax1 Short circuit output current Current limitation

5.0

0.2

0.3

0.4

0.5

V

+/- 2 %

+/- 3 %

+/- 4 %

+/- 4 %

V

V

250 mA

400 600 950 mA

Doc ID 13518 Rev 6 35/68

Electrical characteristics L9952GXP

Table 13.

Voltage regulator V1 (continued)

Item

7.4.8

7.4.9

Symbol

Cload1 tTSD

Parameter

Load capacitor1

V1 deactivation time after thermal shutdown

Test condition

Ceramic

(1)

7.4.10 I

CMP_ris

Current comp. rising threshold

Rising current

7.4.11 I

CMP_fal

Current comp. falling threshold

Falling current

Tj= -40°C...130°C

Tj= 25°C...130°C

7.4.12 I

CMP

_hys Current comp. hysteresis

7.4.13 V1fail V1 fail threshold V1 forced

1.

Placement close to the PAD

Min.

Typ.

Max.

Unit

0.22

µF

1 s

0.9

2.5

0.75

0.85

1.95

1.95

0.5

2

4 mA mA mA

V

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 5.25V < V

S

< 27V; T j

= -40°C...130°C, unless otherwise specified.

Table 14.

Voltage regulator V2

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

V

V

I

V

V

V

2

2 hc1

STB2

DP2

CC2

Output voltage

Output voltage tolerance

Active mode

Output voltage tolerance

Active mode, high current

I

LOAD

= 1mA ...

50mA, V

S

= 13.5V

I

LOAD

= 50mA ...

100mA, V

S

= 13,5V

Output voltage tolerance in low current mode

I

LOAD

= 0uA ...1mA

V

S

= 13,5V

Drop-out voltage

Output current in Active mode

I

LOAD

= 25mA,

V

S

= 5 V

I

LOAD

= 50mA,

V

S

= 5 V

Max. continuous load current

7.5.7

7.5.8

I

CCmax2

C load

7.5.9 V2 fail

Short circuit output current Current limitation

Load capacitor

V2 fail threshold

1.

Placement close to the PAD

Ceramic

(1)

V2 forced

5.0

0,3

0.4

+/- 3

+/- 4

+/- 5

0,4

0.7

100

200 300 500 mA

0.22

µF

2

V

%

%

%

V

V mA

V

36/68 Doc ID 13518 Rev 6

L9952GXP

7.6

Electrical characteristics

Reset generator (V1 supervision)

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 5.25V < V

S

= 18V; T j

= -40 to 130 °C, unless otherwise specified.

Table 15.

Reset generator

Item Symbol Parameter Min.

Typ.

Max.

Unit

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

V

RT1

V

RT2

V

RESET

R

RESET t

RR

Reset threshold voltage1

Reset threshold voltage2

Reset pin low output voltage

Reset pull up int. resistor

Reset reaction time

V1 under-voltage filter time

Test condition

V

S,

V

V1

inc. / decreasing

V

S,

V

V1

inc. / decreasing

V1 > 1V,

I

RESET

= 1mA

@Iload = 1mA

4.5

4.63

4.75

4.25

4.37

4.5

0,2 0,4

V

V

V

60 110 204 k Ω

6 40 µs

16 µs

7.7 Watchdog

6V < V

S

< 18V; 4.8V < V1 < 5.2V; T j

= -40 to 130 °C, unless otherwise specified

Table 16.

Watchdog

(1)

Item Symbol Parameter

7.7.1

7.7.2

7.7.3

7.7.4

t

LW t

CW t

OW t

WDR

1.

See

Figure 13

.

Long open window

Closed window

Open window

Watchdog reset pulse time

Test condition Min.

Typ.

Max.

Unit

48,75

4.5

7.5

1.5

65

6

10

2

81,25

7.5

12.5

2. 5 ms ms ms ms

Doc ID 13518 Rev 6 37/68

38/68

Electrical characteristics

Figure 13.

Watchdog timing

W Dtrigger

N orm al startup operation and tim eout failures

= correct trigger tim ing

= early trigger timing

= m issing trigger

T

C W

+ T

OW

T

C W

+ T

O W

T

LW

T

C W

T

LW

= long w indow < 65m s

T

C W

= closed w indow < 6m s

T

O W

= open w indow < 10m s

T

W DR

= w atchdog reset = 2ms

L9952GXP trigger signal tim e / m s

N R ES-

O ut

T

W D R

T

LW

T

W DR

T

LW early w rite

0 norm al operation m issing trigger

M issing uC trigger signal

W Dtrigger

T

LW

T

LW

T

LW tim e / m s tim e / m s

N RE S-

O ut

T

W DR

T

W DR

T

W D R

0 tim e / m s

Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

Figure 14.

Watchdog, closed and open window tolerances and save trigger area

TWD = nominal trigger time

TCW = closed window

TOW = open window

TWD= 10ms

TCW, max

TCW, min TOW, min

TOW, max watchdog failure save trigger area undefined

4.5

7.5

7.8 High side outputs

12 20 time / ms

The voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6V < V

S

< 18V; 4.8V < V1 < 5.2V; T j

= -40°C...130°C, unless otherwise specified.

Table 17.

High side outputs (Out_HS)

Item Symbol Parameter

7.8.1

7.8.2

7.8.3

R

DSON

OUT_HS td

ONHS td

OFFHS

Static Drain Source

On-resistance to supply

(IOUT_HS=150mA)

Switch on delay time

Switch off delay time

7.8.4

7.8.5

7.8.6

7.8.7

7.8.8

td

SDHS td

ARHS dVout/dt

I

OSDHS

I

OLD

Short circuit filter time

Auto recovery filter time

Slew rate

Short circuit shutdown current

Open load detection current

Test condition

Tj = 25°C

Tj = 125°C

0.2 VS

0.8VS

Tested by scan chain

Tested by scan chain

Min.

Typ.

Max.

Unit

0 1.0

1.5

Ω

0 1.6

3 Ω

10

40

35

95

60

150

µs

µs

64*

T

OSC

400*

T

OSC

0.2

0.5

0.8

V/µs

480 900 1320 mA

40 80 120 mA

Doc ID 13518 Rev 6 39/68

Electrical characteristics L9952GXP

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6V < V

S

< 18V; 4.8V < V1 < 5.2V; T j

= -40°C...130°C, unless otherwise specified.

Table 18.

High side outputs (OUT 1..4)

Item Symbol Parameter Min.

Typ.

Max.

Unit Test condition

I

LOAD

= 60mA @

Tj=+25°C

0 7 12 Ω 7.8.11

R

DSON

On – resistance

7.8.12

7.8.13

7.8.14

7.8.15

7.8.16

7.8.17

I

I

OUT

OLD1

I

OLD2

SR t dONHS t dOFFHS

Short circuit shutdown current

Open load detection current 1

Open load detection current 2

Slew rate

Switch ON delay time

Switch OFF delay time

7.8.18

t

SCF

Short circuit filter time

7.8.19

I

FW

(1)

Loss of GND current

(ESD structure)

1.

Parameter guaranteed by design

8V < Vs < 16V

Selectable via SPI 0.8

0.2 V

S

0.8 V

S

Tested by scan chain

140 235 330 mA

6

2

8

4

13 mA mA

0.2

0.5

0.8

V/µs

10

40

35

64*

T

OSC

60 µs

95 150 µs

100 mA

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6V < V

S

< 18V; 4.8V < V1 < 5.2V; T j

= -40 to 130 °C, unless otherwise specified.

Table 19.

Relay drivers

Item Symbol Parameter

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

R

DSON

I

OUT

V

Z t

ONHL t

OFFLH

Test condition Min.

Typ.

Max.

Unit

DC output resistance

ILOAD = 100mA @

Tj = +25°C

Short circuit shutdown current

Output clamp voltage

(1)

Turn on delay time to 10%

V

OUT

Turn off delay time to 90%

V

OUT

8V < Vs < 16V

I

LOAD

= 100mA

0

250 375 500 mA

40

5

5

2

50

50

3

48

100

100

Ω

V

µs

µs

40/68 Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

Table 19.

Relay drivers (continued)

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

7.9.6

t

SCF

Short circuit filter time

Tested by scan chain

64*

T

OSC

7.9.7

SR Slew Rate 0.2

2

1.

The output is capable to switch off relay coils with the impedance of RL=160

Ω

; L = 300mH

(RL=220

Ω

; L= 420mH); at V

S

= 40V (Load dump condition)

4 V/µs

7.10 Wake up inputs ( WU1..WU4)

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6V < V

S

< 18V; T j

= -40 to 130 °C, unless otherwise specified.

Table 20.

Wake up inputs

(1)

(WU1...WU4)

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

7.10.1

7.10.2

V

V

WUthp

WUthn

Wake-up negative edge threshold voltage

Wake-up positive edge threshold voltage

0.4 Vs

0.5 Vs

0.45 Vs

0.55 Vs

0.5 Vs

0.6 Vs

V

V

7.10.3

7.10.4

V t

HYST

WU

7.10.5

I

WU_stdby

Input current in standby mode

1.5V<V

IN

< (Vs-3V)

7.10.6

R

WU_act

Input resistor to GND in active mode and in standby mode during wake-up request

7.10.7

Nn

Hysteresis

Minimum time for wake-up

Number of samples

During OUT_HS on, cyclic sense mode (100us cyclic HS on time)

7.10.8

7.10.9

V

V wuthl wuthh

Pending wake up request low threshold

Pending wake up request high threshold

0.05 Vs 0.1 Vs 0.15 Vs V

51

10

100

2 (at 80µs and 100µs)

1.0

Vs-3

64

20

275

1.25

Vs-2.2

77

30

450

1.5

Vs-1.4

1.

Defines whether the inputs W1..4 are configured with current source or current sink in standby mode.

µs

µA k Ω

V

V

Doc ID 13518 Rev 6 41/68

Electrical characteristics L9952GXP

7.11 Wake up input (INH)

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. 6V < V

S

< 18V; T j

= -40 to 130 °C, unless otherwise specified.

Table 21.

Wake up input (INH)

Item Symbol Parameter

7.11.1

7.11.2

7.11.3

7.11.4

I

INHth

I

INHUth

I

INHhys t

WU

Wake-up activate threshold current

Wake-up passive threshold current

Wake-up current hysteresis

Minimum time for wake-up

Test condition Min.

Typ.

Max.

Unit

30

30

51

75 120 µA

70 120 µA

10

64

20

77

µA

µs

7.11.5

Nn Number of samples

During OUT_HS on, cyclic sense mode (100µs cyclic

HS on time)

2 (at 80us and

100us)

7.12 LIN

Compatible to Lin 2.1 for Baud rates up to 20 kBit/s

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

6V < V

S

< 18V; 4.8V < V1 < 5.2V; T j

= -40°C...130°C, unless otherwise specified.

Table 22.

LIN receiver

Item

Symbol

LIN

Parameter

LIN receiver

7.12.1

7.12.2

7.12.3

V

TXDLOW

V

TXDHIGH

V

TXDHYS

Input voltage dominant level

Input voltage recessive level

V

TXDHIGH

-

V

TXDLOW

Test condition

Normal mode, V1=5V

Normal mode, V1=5V

Normal mode, V1=5V

Min.

Typ.

Max.

Unit

1

0.5

1.3

2.2

0.8

2.5

V

V

V

7.12.4

7.12.5

7.12.6

I

TXDPU

I

TXDPD

V

RXDLOW

TXD pull up current

TXD pull-down current

Output voltage dominant level

Normal and

V1-standby mode ,

V1=5V

V

BAT

- standby mode,

V

TXDHIGH

V1=5V

Normal mode, V1=5V,

2mA

-5

5

-30

30

0.2

-60 µA

60

1.5

µA

V

42/68 Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

Table 22.

LIN receiver (continued)

Item Parameter

Symbol

LIN LIN receiver

7.12.7

7.12.8

7.12.9

7.12.10

V

RXDHIGH

V

THdom

V

THrec

V

THhys

Test condition

Output voltage recessive level

Receiver threshold voltage recessive to dominant state

Normal mode, V1=5V,

2mA

Receiver threshold voltage dominant to recessive state

Receiver threshold hysteresis

V

THrec

- V

THdom

7.12.11

7.12.12

7.12.13

7.12.14

V

THcnt

V

THwkup

V

THwkdwn

Tbus

Receiver tolerance center value

(V

THrec

+ V

THdom

) / 2

Receiver wakeup threshold voltage

Receiver wakeup threshold voltage

Dominant time for wakeup via bus

Sleep mode edge: rez.- dom.

Min.

Typ.

Max.

Unit

4.5

0.4

V

S

0.5

V

S

0.55

V

S

0.07

V

S

0.475

V

S

0.1

V

S

0.5

V

S

0.6

V

S

0.175

V

S

0.525

V

S

1.0

1.5

2

3.5

Vs

0.45

V

S

2.5

Vs

64

0.5

V

S

1.5

Vs

V

V

V

V

V

V

V

µs

Table 23.

LIN DC parameters

Item Parameter

Symbol

LIN DC parameters

Test condition

7.12.15

7.12.19

I

LINDomSC

7.12.16

I bus_PAS_dom

7.12.17

I bus_PAS_drec

7.12.18

I bus_NO_GND

I bus

Transmitter input current limit in dominant state

Input leakage current at the receiver incl.

Pull-Up resistor

V

V

V

TxD

LIN

TxD

V

LIN

= V

= Vbatmax = 18V

= V

TxDlow

TxDhigh

= 0V

,

V

BAT

Slave mode

=12V,

Transmitter input current in recessive state

V

TxD

= V

TxDhigh

8V<V

LIN,

V

BAT

<18V;

V

LIN

≥ V

BAT

Input current if loss of GND at Device

GND = Vs,

0V<V

LIN

<18V

V

BAT

=12V

Input current if loss of Vbat at device

GND = Vs,

0V<V

LIN

<18V

Min.

Typ.

Max.

Unit

40

-1

-1

100 180 mA

20

1 mA

µA mA

100 µA

Doc ID 13518 Rev 6 43/68

Electrical characteristics

Table 24.

LIN transmitter (continued)

Item Parameter

Symbol

LIN LIN transmitter

7.12.20

7.12.21

7.12.22

V

LINdom

V

LINrec

R

LINup

Test condition

LIN voltage level in dominant state

V

TxD

= V

TxDlow

I

LIN

= 40mA

LIN voltage level in recessive state

V

TxD

= V

TxDhigh

I

LIN

= 10µA

LIN output pull up resistor

V

LIN

= 0V

L9952GXP

Min.

Typ.

Max.

Unit

1.2

V

0.8

Vs

20 40

V

60 k Ω

Table 25.

LIN timing

Item

7.12.24

Symbol t

TXpd_sym

Parameter

Test condition

LIN timing

Symmetry of transmitter propagation delay time (rising vs. falling edge) tTXpd_sym =

= tTXpdr – tTXpdf

Vs=12V,

Rbus Cbus:

1 k Ω , 1 nF tRXpd =

= max (tRXpdr tRXpdf)

Min.

Typ.

Max.

Unit

-2.5

2.5

µs tRXpdf =

=t(0.5RXD)-t(0.45 VLin)

7.12.25

t

RXpd

Receiver propagation delay time tRXpdr =

=t(0.5RXD)-t(0.55 VLin)

Crxd = 20pF

Vs = 12V,

7.12.26

tRXpd_sym

Rbus Cbus:

1 k Ω , 1 nF;

660

Ω,

6.8 nF;

500 Ω ,10 nF

Symmetry of receiver propagation delay time (rising vs. falling edge) tRXpd_sym =

= tRXpdr – tRXpdf

-2 -

6

2

µs

µs

44/68 Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

Table 25.

LIN timing (continued)

Parameter

Item Symbol

LIN timing

7.12.27

7.12.28

7.12.29

7.12.30

D1

D2

D3

D4

Duty cycle 1

Duty cycle 2

Duty cycle 3

Duty cycle 4

Test condition Min.

Typ.

Max.

Unit

THRec(max)=0.744*Vs

THDom(max)=0.581*Vs

Vs= 7...18V, tbit= 50us,

D1=tbus_rec(min)/(2xtbit)

Rbus, Cbus: 1 k Ω , 1 nF;

660 Ω , 6.8 nF;

500 Ω , 10 nF

0.396

THRec(min)=0.284*Vs;

THDom(min)=0.422*Vs,

Vs= 7.6 ...18V, tbit= 50µs,

D1=tbus_rec(max)/(2xtbit)

Rbus, Cbus:

1 k

Ω

, 1 nF;

660 Ω , 6.8 nF;

500

Ω

, 10 nF

THRec(max)=0.778*Vs;

THDom(max)=0.616*V,

Vs= 7...18V tbit= 96µs,

D3 =tbus_rec(min)/(2xtbit)

Rbus, Cbus: 1 k Ω , 1 nF;

660 Ω , 6.8 nF;

500 Ω , 10 nF

0.417

THRec(min)=0.251*Vs;

THDom(min)=0.389*Vs,

Vs= 7.6 ...18V, tbit= 96µs

D1 =tbus_rec(max)/(2xtbit)

Rbus, Cbus:

1 k Ω , 1 nF;

660 Ω , 6.8 nF;

500

Ω

,10 nF

-

-

-

-

0.581

0.59

Table 26.

LIN DC values

Item Parameter

Symbol

LINPU DC values

7.12.31

7.12.32

R

DSon

I leak

ON resistance

Leakage current

Test condition Min.

Typ.

Max.

Unit

10.5

16

1

Ω uA

Doc ID 13518 Rev 6 45/68

Electrical characteristics

Figure 15.

LIN transmit, receive timing t

T X p d f

V

T x D

V

L I N

V

T H r e c

V

T H d o m

V

L IN d o m

8 0 %

V

R x D t

R X p d f

V

L IN r e c t

T X p d r

2 0 % t

R X p d r

L9952GXP t i m e t i m e t i m e

46/68 Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

Note:

The voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6V < V

S

< 18V; T j

= -40...130°C, unless otherwise specified.

Table 27.

Operational amplifier

Item Symbol Parameter

7.13.1

7.13.2

7.13.3

7.13.4

7.13.5

7.13.6

7.13.7

7.13.8

7.13.9

7.13.10

7.13.11

GBW

AVOL

DC

PSRR

V off

V

ICR

V

OH

V

OL

I lim+

I lim-

SR+

SR-

Test condition Min.

Typ.

Max.

Unit

GBW product

DC open loop gain

Power supply rejection

1

80

DC, Vin =150 mV 80

3.5

7.0

MHz dB

Input offset voltage

Common mode input range

-5

-0.2

0

Output voltage range high Iload = 1mA to Gnd

0.2

V

S

Output voltage range low Iload = 1mA to V

S

0

Output current limitation + DC 5 10

Output current limitation DC -5

+5

V

3

S dB mV

V

V

0.2

V

20 mA

-10 -20 mA

Slew rate positive

Slew rate negative

1

-1

4

-4

10 V/µs

-10 V/µs

The operational amplifier is on-chip stabilized for external capacitive loads C

L

< 25pF (all operating conditions)

Doc ID 13518 Rev 6 47/68

Electrical characteristics

7.14 SPI

L9952GXP

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V

S unless otherwise specified.

< 18V; 4.5V < V1 < 5.3V; all outputs open; T j

= -40°C...130°C,

Table 28.

SPI (Input CSN)

Item Symbol Parameter

7.14.1

7.14.2

V

CSNHIGH

7.14.3

7.14.4

7.14.5

V

CSNLOW

V

CSNHYS

I

CSNPU

I

CSNPD

Input voltage low level

Input voltage high level

VCSNHIGH - VCSNLOW

CSN pull up current

CSN pull-down current

Test condition

Active mode,

V1 = 5V

Active mode,

V1=5V

Active mode,

V1=5V

Active mode and

V1 Standby mode,V1=5V

In V bat

- standby mode

Min.

Typ.

Max.

Unit

0.5

1.0

1.6

1

0.5

1.0

1.5

-5

5

1.75

2.5

-30 -60 µA

30 60

V

V

V

µA

7.14.2 Inputs: CLK, DI, PWM 1, PWM 2

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V< V

S

<18V; 4.5V < V1 < 5.3V; all outputs open; T j

= -40°C...130°C, unless otherwise specified.

Table 29.

Inputs: CLK, DI, PWM 1, PWM 2

Item Symbol Parameter Test condition Min.

Typ.

Max.

Unit

7.14.6

7.14.7

7.14.8

7.14.9

7.14.10

7.14.11

7.14.12

V in H

V in Hyst

C f t

V set in L

I

in in

(1)

CLK

Delay time from standby to active mode

Input low level

Switching from standby to active mode. Time until output drivers are enabled after CSN going to high.

V1 = 5 V

Input high level

Input hysteresis

V1 = 5 V

V1 = 5 V

Pull down current at input V in

= 1.5 V

Input capacitance at input

CSN, CLK, DI and

PWM

1,2

0V < V1 < 5.3V

SPI input frequency at

CLK

1.0

160

2.05

10

1.

Value of input capacity is not measured in production test. Parameter guaranteed by design.

300

2.5

1.5

2.8

3.3

0.4

0.75

1.5

5 30 60

15

1

µs pF

MHz

V

V

V

µA

48/68 Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

7.14.3 Input PWM 2 Vth for flash mode

The voltages are referred to ground.

6V < V

S

< 18V; 4.5V < V1 < 5.3V; all outputs open; T j

= -40°C...130°C, unless otherwise specified.

Table 30.

Input PWM2 Vth for flash mode

Item Symbol Parameter

7.14.13

7.14.14

7.14.15

V in L

V in H

V in Hyst

Input low level (Vin rising))

Input high level

(Vin falling)

Input hysteresis

Test condition Min.

Typ.

Max.

Unit

V1 = 5 V 6.1

7.25

8.4

V

V1 = 5 V

V1 = 5 V

7.4

8.4

9.4

0.6 0.8

1.0

V

V

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V

S unless otherwise specified.

< 18V; 4.5V < V1 < 5.3V; all outputs open; T j

= -40°C...130°C,

Table 31.

DI timing

Item Symbol

7.14.16

7.14.17

7.14.18

7.14.19

7.14.20

7.14.21

7.14.22

7.14.23

7.14.24

t

CLK t

CLKH t

CLKL t set CSN t set CLK t set DI t hold DI t r_in t f_in

Parameter

Clock period

Clock high time

Clock low time

CSN setup time, CSN low before rising edge of CLK

CLK setup time, CLK high before rising edge of CSN

DI setup time

DI hold time

Rise time of input signal

DI, CLK, CSN

Fall time of input signal

DI, CLK, CSN

Test condition Min.

Typ.

Max.

Unit

V1 = 5 V

V1 = 5 V

V1 = 5 V

1000 -

400

400 -

ns ns ns

V1 = 5 V

V1 = 5 V

V1 = 5 V

V1 = 5 V

V1 = 5 V

V1 = 5 V

400

400

200

200 -

-

-

-

-

ns ns ns ns

100 ns

100 ns

Doc ID 13518 Rev 6 49/68

Electrical characteristics L9952GXP

7.14.5 DO, FSO, Dig_Out3,4

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V

S unless otherwise specified.

< 18V; 4.5V < V1 < 5.3V; all outputs open; T j

= -40°C...130°C,

Table 32.

DO, FSO, Digout3,4

Item Symbol Parameter

7.14.25

7.14.26

7.14.27

7.14.28

V

DOL

V

DOH

I

DOLK

(1)

C

DO

Test condition Min.

Typ.

Max.

Unit

Output low level

Output high level

Tristate leakage current

Tristate input capacitance

V1 = 5 V, I

D

= -4mA

V = 5 V, I

D

= 4 mA 4.5

V

CSN

= V1,

0 V < V

DO

<´V1

-10

V

CSN

= V1,

0 V < V1 < 5.3 V

10

0.5

10

15

V

V uA pF

1.

Not valid for FSO

50/68

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V

S unless otherwise specified.

< 18V; 4.5V < V1 < 5.3V; all outputs open; T j

= -40°C...130°C,

Table 33.

DO timing

Item Symbol Parameter

7.14.29

7.14.30

7.14.35

t r DO t f DO

7.14.31

t en DO tri L

7.14.32

t dis DO L tri

7.14.33

t en DO tri H

7.14.34

t dis DO H tri t d DO

DO rise time

DO fall time

DO enable time from tristate to low level

DO disable time from low level to tristate

DO enable time from tristate to high level

DO disable time from high level to tristate

DO delay time

Test condition Min.

Typ.

Max.

Unit

C

L

= 100 pF,

I load

= -1 mA

C

L

= 100 pF,

I load

= 1 mA

C

L

= 100 pF,

I load

= 1 mA pull-up load to V1

C

L

= 100 pF,

I load

= 4 mA pull-up load to V1

C

L

= 100 pF,

I load

= -1 mA pull- down load to

GND

C

L

= 100 pF,

I load

= -4 mA pull-down load to

GND

V

DO

< 0.3 V1,

V

DO

> 0.7 V1,

C

L

= 100 pF

-

-

-

-

-

-

50

50

50

50

50

50

50

100

100

250

250

250

250

250 ns ns ns ns ns ns ns

Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V

S unless otherwise specified.

< 18V; 4.5V < V1 < 5.3V; all outputs open; T j

= -40°C...130°C,

Table 34.

CSN timing

Item Symbol Parameter

7.14.36

t

CSN_HI,min

Minimum CSN HI time, active mode

Test condition Min.

Typ. Max.

Unit

Transfer of SPIcommand to input register

6 µs

Figure 16.

SPI - Input timing

CSN t set CSN t

CLKH t se t CLK

0.8 VCC

0.2 VCC

CLK

0.8 VCC

0.2 VCC t set DI t hold DI t

CLKL

DI Valid Valid

0.8 VCC

0.2 VCC

Doc ID 13518 Rev 6 51/68

Electrical characteristics

Figure 17.

SPI - Edges timing

Tf

CLK

CLK

Tr

DO

DO

(low to high

Td

DO

Tf

DO

DO

(high to low

Tf

CSN

CSN

Ten

DO_tri_L

Ten

DO_tri_H

L9952GXP

Tr

CLK

Tr

CSN

Tdis

DO_L_tri

0.8 Vcc

0.5 Vcc

0.2 Vcc

50 %

50 %

Tdis

DO_H_tri

0.8 Vcc

0.5 Vcc

0.2 Vcc

0.8 Vcc

0.2 Vcc

0.8 Vcc

0.2 Vcc

52/68 Doc ID 13518 Rev 6

L9952GXP Electrical characteristics

Figure 18.

SPI - CSN low to high transition

CS N low to high : data from sh ift reg is ter is trans fe rred to output power switches t r in t

CS N_HI,m in t f in

C S N t d OFF output curren t of a driver

O N state OF F state

80 %

50 %

20 %

80 %

50 %

20 % t d ON t

OFF t

ON output curren t of a driver

O FF sta te O N s tate

80 %

50 %

20 %

Figure 19.

SPI - High to low transition

CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO

CSN time

CLK time

DI time

DI: data is not accepted

DO time

DO: status information of data bit 0 (fault condition) will stay as long as CSN is low

Doc ID 13518 Rev 6 53/68

SPI control and status registers

8 SPI control and status registers

L9952GXP

24bit shift register: first 2 bits are address (A1,A0) and 22 bits are data.

During power-on reset, all registers are set to zero.

Table 35.

SPI registers

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

A1 A0

Address

Data

[write] On5V2 On Signals

Control

Register 0

GO

VCC

GO

V

BAT

TRIG

ON

V21

ON

V20

REL

2

REL

1

OUT

HS2

OUT

HS1

OUT

HS0

HS

42

HS

41

HS

40

HS

32

HS

31

HS

30

HS

22

HS

21

HS

20

HS

12

HS

11

HS

10

0 0

[write]

Timer

2

Timer

1

Control

Register 1

CLR INT_en T20 T13 T12 T11 T10 L2

Loop

L1 L0

Address

U3

Pullup / down

U2 U1

Wakeup Sources OL

U0 W7 W6 W5 W4

Wakeup Sources

W3 W2 W1 W0

0

Register 2

1

Control

Err

[write]

1

0

Err

RES I

CMP

LS

OVUV

LIN

Slope

IC

41

IC

40

IC

31

Input config

IC

30

IC

21

IC

20

Address

IC

11

Address

IC

10

Reset level

LIN Openload treshold

LEV

1

LEV

0

TXT

TOU

T

LINPU

O_HS

REC

VLOCK

OUT

OLT

HS4

OLT

HS3

OLT

HS2

OLT

HS1

[read] Reserved Wakeup Wakeup input status Overcurrent Openload

Status

Register 0

RES RES

COLD

STAR

T

L I N I NH WU4 WU3 WU2 WU1

SHT5

V2

Rel2

OC

Rel1

OC

HS

OC

HS4

OC

HS3

OC

HS2

OC

HS1

OC

HS

OL

HS4

OL

HS3

OL

HS2

OL

HS1

OL

Err Err

Status

Register 1

Reserved LIN State Watchdog Reset

RES RES

DOM

TXD

SHT

BAT

SHT

GND

TRIG

WD

3

WD

2

WD

1

WD

0

Address

5V Restarts

R2

State

R1 R0 ST1 ST0

VCC

2

Fail

VCC

1

Fail

TSD

2

TSD

1

TW UV OV

Address

Note: During the shift in of the address bits, (2 clock periods) an internal error bit (Err) is fed to the

DO output.

D23,D22 -> error flags (seen from DO)

The error flag is generated by logic OR combination of following error bits:

VCC_Fail1,2; TSD1,2; TW; OV,UW; OC_HS1..4; OC_OUTHS; OC_REL1..2; OC_V2

54/68 Doc ID 13518 Rev 6

L9952GXP SPI control and status registers

While writing to the control register 0, the status register 0 can be read at the DO-Output of the SPI.

Table 36.

Control register 0

Bit 21 20 19

5V2

18 17 16 15 14 13

Driver ON Signals

12 11 10 9 8 7 6 5 4 3 2 1 0

Access w w w w w w w w w w w w w w w w w w w w w w

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Name

GO

V1

GO

V bat

TRIG

ON

V21

ON

V20

REL

2

REL

1

OUT

HS2

OUT

HS1

OUT

HS0

HS

42

HS

41

HS

40

HS

32

HS

31

HS

30

HS

22

HS

21

HS

20

HS

12

HS

11

HS

10

x

Table 37.

Configuration bit HSxx

Name / state Definition/ function

HSx2 HSx1 HSx0 Defines the output configuration of the High Side Drivers 1-4

Table 38.

Configuration bit OUT_HSx

Name / state Definition/ function

OUT_HS

2

0

0

0

0

1

1

OUT_HS

1

OUT_HS

0

Defines the output configuration of the High Side Driver OUT_HS

0 0 Driver is OFF in all modes

0 1

1

1

0

0

0

1

0

1

Driver is ON in active mode, off in standby mode

Driver is cyclic ON with the timing of Timer 1 in active mode and standby modes

Driver is cyclic ON with the timing of Timer 2 in active mode and standby modes

Driver is controlled by the PWM1 Input

Driver is controlled by the PWM2 Input

Table 39.

Configuration bit RELx

Name / state

RELx

0

1

Definition/ function

Defines the Output configuration of the low side relay drivers 1/2

Driver is OFF in all modes

Driver is ON in active mode (off in standby mode)

Table 40.

Configuration bit On_V2x

Name / state

On_V21

0

Definition/ function

On_V20 Defines in which modes the voltage regulator 2 is on

0 Voltage regulator 2 is OFF in all modes

Doc ID 13518 Rev 6 55/68

SPI control and status registers

Table 40.

Configuration bit On_V2x (continued)

Name / state Definition/ function

0

1

1

1

0

1

Voltage regulator 2 is ON in ACTIVE mode;

OFF in V

1

-standby, V

Bat

-standby

Voltage regulator 2 is ON in ACTIVE mode and V

1

standby;

OFF in V bat

-standby

Voltage regulator 2 is ON in all modes

L9952GXP

Table 41.

Configuration bit TRIG, GO_VBAT, GO_V1

TRIG

Trigger bit for watchdog; inverted for each Trigger event invert this bit for a proper watchdog trigger.

GO_VBAT

GO_V1

”1” enters the V bat

-standby mode. (dominant mode, if both standby modes are selected)

“1” enters the V

1

-standby mode.

While writing to the control register 1, the status register 1 can be read at the DO-Output of the SPI.

Table 42.

Control register 1

Cyclic Timer 1/2

Bit

Access

Reset

Name

Loop

11

Pull up

10 9 5

Wakeup Sources

4 3 2 21 w

20 w

19 w

18 17 16 15 14 13 12 8 w

7 w

6 w

1 w w

0 w

0 w

0 w

0 w

0 w

0 w

0 w

0 w

0 w

0 w

0 w

0 w

0 w

0 0 0 0 0 0 0 0 0

CLR INT_EN T20 T13 T12 T11 T10 L2 L1 L0 U3 U2 U1 U0 W7 W6 W5 W4 W3 W2 W1 W0

0 w

Table 43.

Configuration bit Wx

Name/state Definition/function

W7 W6 W5 W4 W3 W2 W1 W0 Disables the corresponding wake up sources x x x x x x x x x x x x x

1

1 x

Input WU1 is disabled as wake up source

Input WU2 is disabled as wake up source x x x x x x x x x

1 x x x

1 x x x

1 x x x

1 x x x

1 x x x x x x x x x x x x x x

Input WU3 is disabled as wake up source

Input WU4 is disabled as wake up source

Open load Appearance / Disappearance at OUT1 is disabled as wake up source

Open load Appearance / Disappearance at OUT2 is disabled as wake up source

Open load Appearance / Disappearance at OUT3 is disabled as wake up source

56/68 Doc ID 13518 Rev 6

L9952GXP SPI control and status registers

Table 43.

Configuration bit Wx (continued)

1

0 x

0 x

0

Name/state x

0 x

0 x

0 x

0

Definition/function x

Open load Appearance / Disappearance at OUT4 is disabled as wake up source

0 Default: all wake up sources are enabled

Table 44.

Configuration bit Ux

Name/state Definition/function

U3 U2 U1 U0

Defines whether the Inputs WU1..4 are configured with current source or current sink in standby mode. x x x

1

0 x x

1 x

0 x

1 x x

0

1 x x x

0

Input WU1 configured with a current source in standby mode

(R

WU_act

pulldown resistor in active mode - see Table 20.

)

Input WU2 configured with a current source in standby mode

(R

WU_act

pulldown resistor in active mode - see Table 20.

)

Input WU3 configured with a current source in standby mode

(R

WU_act

pulldown resistor in active mode - see Table 20.

)

Input WU4 configured with a current source in standby mode

(R

WU_act

pulldown resistor in active mode - see Table 20.

)

Default: All Inputs configured with a current sink in standby

(R

WU_act

pulldown resistor in active mode - see Table 20.

)

Table 45.

Configuration bit Lx

Name/state

L2 L1

1

1

1

1

0

0

0

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

0

0

L0

Definition/function

Defines which signal is looped to the Dig_Out3 and Dig_Out4

(see note)

Dig_Out3 Dig_Out4

WU3 (default)

HighZ

WU3

WU3

WU4 (default)

WU4

HighZ

Open Load HS2

Open Load HS1

Open Load HS1

Open Load HS1

HighZ

WU4

Open Load HS2

HighZ

Open Load HS2

Doc ID 13518 Rev 6 57/68

58/68

SPI control and status registers L9952GXP

Table 46.

Configuration bit Txx

Name/state

T12 T11

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

T13

0

1

T20

0

1

0

1

0

1

0

1

0

1

T10

Definition/function

Defines the period of the cyclic sense Timer 1 which is selectable for Out

1..4 and Out_HS (see ON signals control register 0)

Period: 0.5 s

Period: 1.0 s

Period: 1.5 s

Period: 2.0 s

Period: 2.5 s

Period: 3.0 s

Period: 3.5 s

Period: 4.0 s

Defines the ON time for the cyclic sense Timer1

ON time 10 ms

ON time 20 ms

Defines the ON time of the cyclic sense Timer 2 which is selectable for Out

1..4 and OUTHS (see ON Signals control register 0)

Period 50 ms / ON time 100 us

Period 50 ms / ON time 1ms

Table 47.

Configuration bit INT_enable

Name/state

INT_enable

0

1

CLR

Definition/function

Interrupt Mode disabled ( see

Section 2.7

)

Interrupt Mode enabled

Clears the contents of status register 0 and 1

Note: In V

BAT standby mode, DigOut 3 and DigOut4 are HighZ.

Doc ID 13518 Rev 6

L9952GXP SPI control and status registers

While writing to the control register 2, the status register 0 can be read at the DO-Output of the SPI.

Table 48.

Control register 2

Input filter configuration

Bit

Access

21

W

20 19

W

18

W

17

W

16 15 14 13 12 11 10

W W W W W W W

9

Reset level

W

8

W

7

W

LIN

6

W

5

W

4

W

Open load threshold

3

W

2

W

1

W

0

W

Reset

Name

0 0 0 0 0

RES I

CMP

LSO

VUV

LIN

Slope

IC

41

0 0 0 0 0 0 0 0 0 0

IC

40

IC

31

IC

30

IC

21

IC

20

IC

11

IC

10

LEV

1

LEV

0

TXDT

Out

0

LINP

U

0 0 0 0 0 0

O_HS

REC

VS

Lock

Out

OLT

HS4

OLT

HS3

OLT

HS2

OLT

HS1

Table 49.

Configuration bit OLT_HSx, VSLOCK Out, O_HS_REC, LINPU and

TXD_TOUT

Name/state Definition/function

OLT_HSx

Open load threshold for the High Side Drivers Out1..4

0: Iopenload = 2mA; 1: Iopenload = 8mA

Automatic recovery after VS Over/Under voltage

“0” (default): Vs lockout is disabled, i.e. outputs will automatically recover (according to output settings in CR0) after Vs over / under - voltage conditions has disappeared

VSLOCK

Out

“1”: Vs lockout is enabled, i.e. outputs will remain Off after Vs over / under voltage recovery conditions has disappeared, until the Vs over / under voltage Status Bits

(SR1, bit s0,1) are cleared by CLR command (CR1, bit 21).

O_HS_REC “1” = Recovery mode for OUT_HS Driver.

LINPU “1” will disable the master pull up LINPU

TXD_TOUT “1” will disable the dominant TxD time-out for the LIN Interface.

Table 50.

Configuration bit LEVx

LEV1

0

0

1

Name/state

LEV0

0

1

X

Definition/function

Controls the reset level

Set the reset threshold to 4.65V, typ.

Set the reset threshold to 4.35V, typ.

Reserved (do not use for operation, set LEV1 to “0”)

Doc ID 13518 Rev 6 59/68

60/68

SPI control and status registers L9952GXP

Table 51.

Configuration bit ICxx

Name/state

IC(1..4)1 IC(1..4)0

Definition/function

Selects the filter configuration for the

Wakeup Inputs WU1 to 4

IC11

IC21

IC31

IC41

0

0

1

1

0

1

0

1

Filter with 64 us Filter time (static sense)

Enable Filter after 80 us with a Filter time of 16 us (cyclic sensing), timer2

Enable Filter after 800 us with a Filter time of 16 us (cyclic sensing), timer2

Enable Filter after 800 us with a Filter time of 16 us (cyclic sensing), timer1

Table 52.

Configuration bit LIN slope, LS_ovuv and ICMP

Name/state Definition/function

LIN slope Change LIN slope

0

1

LS_ovuv

0

1

I

CMP

0

1

RES

High slew rate (default)

Low slew rate

Vs Over / Under voltage shutdown of REL1,2 (low side drivers)

Enable (default): REL1,2 turned Off in case of Vs Over/Undervoltage

Disable : REL1,2 remain On in case of Vs Over/Undervoltage

Current supervision of V1 regulator in V

1

-standby mode.

Enable (default)

Disable

Reserved

Doc ID 13518 Rev 6

L9952GXP SPI control and status registers

The contents of the status register 0 can be read implicitly, while accessing the control register 0 or control register 2.

Table 53.

Status register 0

Bit

Access

Reset

Name

21 r

20 r

19 r

Wakeup Inputs

18 17 16 15 14 13 r r r r r r

10

Over current

9 8 3

Open load

2 1 12 r

11 r

7 r

6 r

5 r

4 r

0 r r r r r r r

0 0

RES RES

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Cold

Start

LIN INH

WU

4

WU

3

WU

2

WU

1

SHT5V2

REL

2OC

REL

1OC

HS

OC

HS

4OC

HS

3OC

HS

2OC

HS

10C

HS

O L

HS

4OL

HS

3OL

HS

2OL

HS

1OL

Table 54.

Configuration bit HSx_OL, HSx_OC and Relx_OC

Name/state Definition/function

HS1..4_OL

Open load status from the High Side Driver OUT1..4.

0

1

HS_OL

0

No open load has been detected.

Open load has been detected.

Open load status from the High Side Driver OUT_HS

No open load has been detected.

1 Open load has been detected.

HS1..4_OC

Over current status from the High Side Driver OUT1..4.

0

1

No over current has been detected.

Over current has been detected.

HS_OC

0

Over current status from the High Side Driver OUT_HS.

No over current has been detected.

1 Over current has been detected.

Rel 1,2_OC Over current status from Relais1,2

0

1

No over current has been detected.

Over current has been detected.

Table 55.

Configuration bit SHT5V2, WUx, INH, LIN and Cold Start

Name/state Definition/function

SHT5V2 V2 short to ground at turn on; condition: V2 < 2V for more than 4ms. “1” = fail

WU4...WU1

Status of the corresponding Inputs WU1..4 (according to filter settings in CR2)

Doc ID 13518 Rev 6 61/68

SPI control and status registers

Note:

L9952GXP

Table 55.

Configuration bit SHT5V2, WUx, INH, LIN and Cold Start (continued)

Name/state Definition/function

INH

LIN

Cold Start

Wakeup initiated through INH source

Wakeup initiated through LIN source

Set to high when the internal Power on Reset occurs.

Will be cleared with the first SPI access.

RES = reserved bits.

The contents of the status register 1 can be read implicitly, while accessing the control register 1.

Table 56.

Status register 1

LIN state

Bit

Access

Reset

Name

WD resets

11

5V restarts

10 9 8

State

7 21 20 19 18 17 r

16 r

15 14 13 12 6 r

5 r

4 r

3 r

2 r

1 r r r r r r r r r r r r r r

0 0 0 0 0 0 0 0 0 0 0

RES RES

DOM

TXD

SHT

BAT

SHT

GND

TRIG

WD

3

WD

2

WD

1

WD

0

R2

0

R1

0 0 0 0 0 0 0 0 0

R0 ST1 ST0

V2

Fail

V1

Fail

TSD

2

TSD

1

TW UV

0

OV

0 r

Table 57.

Configuration bit OV, UV, TW, TSDx and Vx Fail

Name Definition, function

OV

UV

TW

TSD1

TSD2

V1 Fail

V2 Fail

Over voltage failure of Vs.

Under voltage failure of Vs.

Temperature Warning: the chip temperature exceeds 130°C

Thermal shutdown #1: The chip temperature exceeds 140°C

All Outputs, except the voltage regulator 1 are switched off.

Thermal shutdown #2: The chip temperature exceeds 155°C

All Outputs, including the voltage regulator 1 are switched off.

The output of Voltage Regulator 1 failed for at least 2µs. Conditions: (V1<2V for >2µs)

OR (V1<2V at 4ms after turn-on). ‘1’= fail

The output of Voltage Regulator 2 failed for at least 2µs. Conditions: (V2<2V for >2µs)

OR (V2<2V at 4ms after turn-on). ‘1’= fail

Table 58.

Configuration bit STx

Name Mode

ST1 ST0

0 0 Active mode

0 1 V1-standby -> a readout is wake up condition -> active mode -> 00 is read

62/68 Doc ID 13518 Rev 6

L9952GXP SPI control and status registers

Table 58.

Configuration bit STx (continued)

Name Mode

1

1

0 VBat-standby, a readout is not possible, as V1 is off

1 Flash Mode

Table 59.

Configuration bit Rx, WDx, TRIG, SHT_GND, SHT_BAT and DOM_TXD

Name Definition, function

R2 R1 R0 Number of unsuccessfully restarts after thermal shutdown

WD3 WD2 WD1 WD0 Number of Watchdog time-outs

(1)

TRIG

SHT_GND

Status of the Trigger bit from Control Register 0

LIN Short to ground

SHT_BAT

DOM_TXD

LIN Short to battery

Dominant TXT

RES Reserved

1.

Bits are cleared at every valid WD trigger or when forced sleep mode is entered (after 15 WD failures have been detected)

Doc ID 13518 Rev 6 63/68

Package and packing information

9 Package and packing information

L9952GXP

9.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK

®

is an ST trademark.

9.2 PowerSSO-36 package information

Figure 20.

PowerSSO-36 package dimensions

64/68

Table 60.

PowerSSO-36 mechanical data

Symbol

A

A2 a1 b c

Min.

-

2.15

0

0.18

0.23

Millimeters

Typ.

-

-

-

-

-

Doc ID 13518 Rev 6

Max.

2.45

2.35

0.1

0.36

0.32

L9952GXP Package and packing information

Table 60.

PowerSSO-36 mechanical data (continued)

Millimeters

Symbol

Min.

Typ.

k

L

M

N

G

G1

H h e e3

F

D

E

S

T

U

O

Q

X

Y

0°

0.55

-

-

-

-

10.1

-

10.10

7.4

-

-

-

-

-

-

-

-

4.1

6.5

-

-

4.3

-

-

-

-

-

0.5

8.5

2.3

-

-

1.2

0.8

2.9

3.65

1.0

-

-

0.1

0.06

10.5

0.4

8°

0.85

-

10 deg

-

-

-

-

-

4.7

7.1

Max.

10.50

7.6

-

-

-

Doc ID 13518 Rev 6 65/68

Package and packing information

9.3 PowerSSO-36 packing information

Figure 21.

PowerSSO-36 tube shipment (no suffix)

C

B

Base Qty

Bulk Qty

Tube length (±0.5)

A

B

C (±0.1)

All dimensions are in mm.

49

1225

532

3.5

13.8

0.6

A

Figure 22.

PowerSSO-36 tape and reel shipment (suffix “TR”)

L9952GXP

REEL DIMENSIONS

Base Qty

Bulk Qty

A (max)

B (min)

C (±0.2)

F

G (+2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

24.4

100

30.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (±0.1)

D1 (min)

F (±0.1)

K (max)

P1 (±0.1)

24

4

P 12

D (±0.05) 1.55

1.5

11.5

2.85

2

All dimensions are in mm.

End

Top cover tape

No components Components

500mm min 500mm min

Empty components pockets sealed with cover tape.

Start

No components

User direction of feed

66/68 Doc ID 13518 Rev 6

L9952GXP Revision history

Table 61.

Document revision history

Date Revision

24-Aug-2007

07-Sep-2007

21-Sep-2007

11-Apr-2008

08-Jul-2009

22-Sep-2013

1

2

3

4

5

6

Changes

Initial release.

Table 18: High side outputs (OUT 1..4)

: modified openload detection current 1 parameter value (item 7.8.13).

Table 20: Wake up inputs(WU1...WU4) : modified Input current in

standby mode test condition (item 7.10.5).

Table 22: LIN receiver : modified symmetry of transmitter propagation

delay time parameter value (item 7.12.24).

Added Section 9.3: PowerSSO-36 packing information

.

Section 7.2: Oscillator

: changed Vs minimum value from 7 to 6 V.

Table 10: Supply and supply monitoring :

– changed parameter 7.1.10 (I

V(BATWU)

) max value from 300 to 320 µA

– changed parameter 7.1.11 (I

V(BATWU)

) max value from 380 to 410 µA.

Modified

Figure 4.: Watchdog

Modified

Section 2.13: Low side driver outputs Rel1, Rel2

.

Added note to

Section 2.2.2: Flash mode .

Section Table 48.: Control register 2

: changed definition to V

S

Lock Out parameter.

Added Section 6.3: Package and PCB thermal data .

Modified

Section 7.14.3: Input PWM 2 Vth for flash mode .

Table 42: Control register 1

: modified "pull down" settings for the wakeup inputs WU1..4 .

Table 60: PowerSSO-36 mechanical data :

– Deleted A (min) value

– Changed A (max) value from 2.47 to 2.45

– Changed A2 (max) value from 2.40 to 2.35

– Changed a1 (max) value from 0.075 to 0.1

– Added k row

– Changed G (max) value from 0.075 to 0.1

Updated Disclaimer.

Doc ID 13518 Rev 6 67/68

L9952GXP

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68/68 Doc ID 13518 Rev 6