Mechanical and electrical specifications LIS331DLM
2.3.2 I
2
C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Table 6.
I
2
C slave timing values
Symbol Parameter f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
I
2
C standard mode
(1)
Min
0
Max
100
4.7
4.0
250
0.01
3.45
1000 t f(SDA) t f(SCL)
SDA and SCL fall time 300 t h(ST)
START condition hold time 4 t su(SR)
Repeated START condition setup time
4.7
t su(SP)
STOP condition setup time 4 t w(SP:SR)
Bus free time between STOP and START condition
4.7
1.
Data based on standard I
2
C protocol requirement, not tested in production
2.
Cb = total capacitance of one bus line, in pF
I
2
C fast mode
(1)
Min
0
Max
400
1.3
0.6
100
0.01
20 + 0.1C
b
(2)
20 + 0.1C
b
( 2)
0.6
0.9
300
300
0.6
0.6
1.3
Figure 4.
I
2
C Slave timing diagram
(a)
SDA
START
Unit
KHz
µs ns
µs ns
µs t su(SR) t w(SP:SR)
REPEATED
START
START t f(SDA) t r(SDA) t su(SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH) t r(SCL) t f(SCL) a.
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port
12/38 Doc ID 15102 Rev 4
