STMicroelectronics powerSTEP01 Datasheet
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powerSTEP01
System-in-package integrating microstepping controller and
10 A power MOSFETs
Datasheet
-
production data
Applications
High power bipolar stepper motor
– Stage lighting
– Surveillance systems
– Textile and sewing machines
– Pick and place machines
VFQFPN 11x14 mm
Features
Power system-in-package integrating a programmable microstepping controller and 8
N-channel power MOSFETs
Operating voltage: 7.5 V - 85 V
Dual full-bridge with R
DS(on)
= 16 mΩ
10 A
RMS maximum output current
Adjustable output slew rate
Programmable speed profile
Up to 1/128 microstepping
Sensorless stall detection
Integrated voltage regulators
SPI interface
Low quiescent standby currents
Programmable non-dissipative overcurrent protection
Overtemperature protection
Description
The powerSTEP01 is a system-in-package integrating 8 N-channel 16 mΩ MOSFETs for stepper applications up to 85 V with an SPI programmable controller, providing a full digital control of the motion through a speed profile generation and positioning calculations.
It integrates a dual low R
DS(on)
full-bridge with embedded non-dissipative overcurrent protection.
The device can operate with both voltage mode driving and advanced current control fitting different application needs. The digital control core can generate user’s defined motion profiles with acceleration, deceleration, speed or a target position easily programmed through a dedicated register set. All application commands and data registers, including those used to set analog values (i.e. current protection trip point, dead time, PWM frequency, etc.) are sent through a standard 5-Mbit/s SPI. A very rich set of protections (thermal, low bus voltage, overcurrent and motor stall) make the powerSTEP01 “bullet proof”, as required by the most demanding motor control applications.
Table 1. Device summary
Order code Package
POWERSTEP01
POWERSTEP01TR
VFQFPN
11x14x1.0 mm
VFQFPN
11x14x1.0 mm
Packing
Tray
Tape and reel
January 2020
This is information on a product in full production.
DS9836 Rev 7 1/92 www.st.com
Contents
Contents
2/92 powerSTEP01
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Programmable speed profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Motor control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Constant speed commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Positioning commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Motion commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
GoUntil and ReleaseSW commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Internal oscillator and oscillator driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DS9836 Rev 7
powerSTEP01
Contents
VS undervoltage lockout (UVLO_ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 32
Integrated power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Programmable slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Deadtime and blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Integrated analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Supply management and internal voltage regulators . . . . . . . . . . . . . . . . 36
Phase current control: voltage mode . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PWM sinewave generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
BEMF compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Motor supply voltage compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Winding resistance thermal drift compensation . . . . . . . . . . . . . . . . . . . . 42
Phase current control: current mode . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Auto-adjusted decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Auto-adjusted fast decay during the falling steps . . . . . . . . . . . . . . . . . . . 46
Torque regulation (setting the output current) . . . . . . . . . . . . . . . . . . . . . 47
Programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Register and flag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DS9836 Rev 7 3/92
92
Contents powerSTEP01
11.1.10 KVAL_HOLD, KVAL_RUN, KVAL_ACC and KVAL_DEC . . . . . . . . . . . 56
11.1.16 TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC . . . . . . . . . . . . 58
Command management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SetParam (PARAM, VALUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
GetParam (PARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Move (DIR, N_STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
GoTo (ABS_POS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
GoTo_DIR (DIR, ABS_POS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4/92 DS9836 Rev 7
powerSTEP01
Contents
VFQFPN 11x14x10 package information . . . . . . . . . . . . . . . . . . . . . . . . . 83
DS9836 Rev 7 5/92
92
List of tables
List of tables
powerSTEP01
Integrated MOSFETs characteristics at T j
= 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers . 58
ADC_OUT value and motor supply voltage compensation feature . . . . . . . . . . . . . . . . . . 60
6/92 DS9836 Rev 7
powerSTEP01 List of tables
DS9836 Rev 7 7/92
92
List of figures
List of figures
powerSTEP01
Adaptive decay - switch from normal to slow+ fast decay mode and vice versa . . . . . . . . 46
8/92 DS9836 Rev 7
powerSTEP01
1 Block diagram
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DS9836 Rev 7 9/92
92
Electrical data
2 Electrical data
2.1 Absolute maximum ratings
V
SREG
V
CCREG
V
OUT1A
V
OUT2A
V
OUT1B
V
OUT2B
I
I
OUT1A
I
OUT2A
OUT1B
I
OUT2B
SR out
V
ADCIN
Symbol
V
DD
V
REG
V
S
V
CC
V
BOOT
V
BOOT
V out_diff
V in
T
OP
T s
Table 2. Absolute maximum ratings
Parameter Test conditions
Logic interface supply voltage
Logic supply voltage
Motor supply voltage
Low-side gate driver supply voltage
Boot voltage
High-side gate driver supply voltage
(V
BOOT
- V
S
)
Internal V
CC
regulator supply voltage
Internal V
REG
regulator supply voltage
DC
Output voltage
AC
Output current
Full-bridge output slew rate (10% - 90%)
Integrated ADC input voltage range
(ADCIN pin)
Differential voltage between VBOOT, VS,
OUT1A, OUT2A, PGND and VBOOT, VS,
OUT1B, OUT2B, PGND pins
Logic input voltage range
Storage and operating junction temperature
DC powerSTEP01
Value
5.5
3.6
95
18
100
0 to 20
95
18
-5 to V
BOOT
-15 to V
BOOT
Unit
V
V
V
V
V
V
V
V
10
10
-0.3 to 3.6
A
RMS
V/ns
V
100
-0.3 to 5.5
-40 to 150
V
V
°C
10/92 DS9836 Rev 7
powerSTEP01 Electrical data
2.2 Recommended operating conditions
Symbol
Table 3. Recommended operating conditions
Parameter Test conditions Min.
Typ.
Max.
Unit
V
V
V
V
REG
V
S
SREG
CC, ext
V
CCREG
V
DD
ADC
Logic interface supply voltage
3.3 V logic outputs
5 V logic outputs
Logic supply voltage
Motor supply voltage V
SREG
Internal V
CC voltage voltage regulator supply
Integrated ADC input voltage
(ADCIN pin)
V
CC voltage internally generated V
Gate driver supply voltage
Internal V
REG voltage
voltage regulator supply
V
CC
voltage imposed by external source (V
SREG
= V
CC
)
V
REG
voltage internally generated
CC
7.5
6.3
0
+3
3.3
5
3.3
85
V s
15
V
CC
V
REG
V
V
V
V
V
V
V
DS9836 Rev 7 11/92
92
Electrical characteristics
3 Electrical characteristics
powerSTEP01
Symbol
V
S
= 48 V; V
CC
= 7.5 V; V
DD
= 3.3 V; T j
= 25 °C, unless otherwise specified.
Table 4. Electrical characteristics
Parameter Test conditions Min.
Typ.
Max. Unit
General
V
V
V
V
CCthOn
CCthOff
BOOTthOn
BOOTthOff
V
V
CC
CC
UVLO turn-on threshold
UVLO turn-off threshold
V
BOOT
V
BOOT
- V
S
- V
S
UVLO turn-on threshold
UVLO turn-off threshold
UVLO_VAL set high
(1)
UVLO_VAL set low
(1)
UVLO_VAL set high
(1)
UVLO_VAL set low
(1)
UVLO_VAL set high
(1)
UVLO_VAL set low
(1)
UVLO_VAL set high
(1)
UVLO_VAL set low
(1)
(1)
V
V
I
REGthOn
REGthOff
VREGqu
V
REG turn-on threshold
V
REG turn-off threshold
Undervoltage V
REG
quiescent supply current
(1)
V
CCREG
= V
REG
< 2.2 V
(1)
I
VREGq
Quiescent V
REG supply current
I
VSREGq
Quiescent V
Thermal protection
SREG supply current
T j(WRN)Set
T j(WRN)Rec
T j(OFF)Set
T
T
T j(OFF)Rec j(SD)Set j(SD)Rec
Thermal warning temperature
Thermal warning recovery temperature
Thermal bridge shutdown temperature
Thermal bridge shutdown recovery temperature
Thermal device shutdown temperature
Thermal device shutdown recovery temperature
V
CCREG
= V
REG
= 3.3 V internal oscillator selected
(1)
V
CCREG
= V
CC
= 15 V
Charge pump f f
V pump pump,min pump,max
Voltage swing for charge pump oscillator
Minimum charge pump oscillator frequency
(2)
Maximum charge pump oscillator frequency
(2)
5.9
8.6
5.7
8.2
9.9
6.5
9.5
5.3
2.8
2.2
10.4
6.9
10
6.3
9.2
6
8.8
5.5
3
2.4
40
3.8
6.5
135
125
155
145
170
130
V
CC
660
800 mA mA
°C
°C
°C
°C
°C
°C
V kHz kHz
10.9
V
7.3
V
10.5
V
6.7
V
9.94
V
6.35
V
9.65
V
5.9
V
3.18
V
2.5
V
A
12/92 DS9836 Rev 7
powerSTEP01 Electrical characteristics
Symbol
Table 4. Electrical characteristics (continued)
Parameter
R
R pumpHS pumpLS
Charge pump high-side R
DS(on) resistance
Charge pump low-side R
DS(on) resistance
I boot
Power outputs
Average boot current
Test conditions Min.
Typ.
Max. Unit
10
10
2.6
mA
R
DS(on)
SR
OUT
I
DSS
High-side and low-side on resistance
Output slew rate
Leakage current
V
CC
= 15 V at 25 °C
At 125 °C
IGATE = 96 mA
IGATE = 32 mA
OUT = V
S
OUT = GND -0.1
16
23
980
520
21 m
V/ s
0.1
mA mA
Dead time and blanking t
DT t blank
Programmable deadtime
2
Programmable blanking time
2
TDT = '00000'
TDT =’11111’
TBLANK = '000'
TBLANK =’111’
125
4000
125
1000 ns ns
Logic
V
IL
V
IH
I
IH
I
IL
V
OL
V
OH
Low level logic input voltage
High level logic input voltage
High level logic input current
Low level logic input current
Low level logic output voltage
(3)
High level logic output voltage
V
IN
= 5 V, V
DD
= 5 V
V
IN
= 0 V, V
DD
= 5 V
V
DD
= 3.3 V, I
OL
= 4 mA
V
DD
= 5 V, I
OL
= 4 mA
V
DD
= 3.3 V, I
OH
= 4 mA
V
DD
= 5 V, I
OH
= 4 mA
2
-1
2.4
4.7
0.8
1
0.3
0.3
V
V
V
V
μA
μA
R
PUCS
R
PDRST
R
PUSW t high,STCK t low,STCK
CS pull-up resistor
STBY/RESET pull-down resistor
SW pull-up resistor
Step-clock input high time
Step-clock input low time
Internal oscillator and external oscillator driver f f osc,int osc,ext
Internal oscillator frequency
Programmable external oscillator frequency
T j
= 25 °C
300
300
-5%
8
430
450
80
16 k ns ns
+5% MHz
32 MHz
DS9836 Rev 7 13/92
92
Electrical characteristics powerSTEP01
Symbol
Table 4. Electrical characteristics (continued)
Parameter Test conditions
V
V t t
OSCOUTH
OSCOUTL rOSCOUT fOSCOUT t t t high extosc intosc
OSCOUT clock source high level voltage
OSCOUT clock source low level voltage
Internal oscillator
Internal oscillator
OSCOUT clock source rise and fall time
OSCOUT clock source high time
Internal to external oscillator switching delay
External to internal oscillator switching delay
Internal oscillator
Internal oscillator
SPI f
CK,MAX t rCK t fCK t hCK t lCK t setCS t holCS t disCS t setSDI t holSDI t enSDO t disSDO t vSDO t holSDO
Maximum SPI clock frequency
SPI clock rise and fall time
Chip select setup time
(4)
Chip select hold time
(4)
Deselect time
(4)
Data input setup time
(4)
Data input hold time
(4)
Data output enable time
(4)
Data output disable time
(4)
Data output valid time
Data output hold time
(4)
(4)
(4)
SPI clock high and low time
PWM modulators
(4)
(4) f
PWM
Programmable PWM frequency
(2) f osc
= 32 MHz
F_PWM_INT=’11X’
F_PWM_DEC=’000’ f osc
= 32 MHz
F_PWM_INT=’000’
F_PWM_DEC=’111’
N
PWM
PWM resolution
Current control
V
REF, MAX
V
REF, MIN
Maximum reference voltage
Minimum reference voltage
Min.
Typ.
Max. Unit
2.4
5
90
30
30
625
20
30
0
31.25
3
5.6
125
8
1000
7.8
0.3
10
1
95
95
35
V
V ns ns ms
100 μs
MHz
μs ns kHz kHz bit mV mV ns ns ns ns ns ns ns ns ns
14/92 DS9836 Rev 7
powerSTEP01 Electrical characteristics
Symbol
Table 4. Electrical characteristics (continued)
Parameter Test conditions Min.
Typ.
Max. Unit
Overcurrent protection
V
OCD
Programmable overcurrent detection voltage V
DS threshold t
OCD,Comp t
OCD,Flag t
OCD,SD
Stall detection
OCD comparator delay
OCD to flag signal delay time
OCD to shutdown delay time I
OCD_TH = ‘00000’
OCD_TH = ‘01001’
OCD_TH = ‘10011’
OCD_TH = '11111' gate
= 4 mA, t
CC
= maximum
V
STALL
Programmable stall detection V voltage threshold
DS
STALL_TH = '11111'
STALL_TH = '00000'
Standby t
I
I
STBY,reg
STBY,min t logicwu t
STBY cpwu
Standby mode supply current (VSREG pin)
V
CC
V
= V
CCREG
SREG
= 48 V
= 7.5 V
V
CC
V
= V
CCREG
SREG
= 18 V
= 7.5 V
Standby mode supply current (VREG pin)
Minimum standby time
Logic power-on and wake-up time
Charge pump power-on and wake-up time
Power bridges disabled,
C p
V
= 10 nF, C boot
CC
= 15 V
= 220 nF,
Internal voltage regulators
27 31 35 mV
270 312.5
344 mV
500 625 688 mV
800 1000 1100 mV
100 200 ns
230 530 ns
4200 6000 ns
1000
31
42
37.5
6
0.5
500
1 mV
μA
μA ms
μs ms
V
CCOUT
Internal V voltage
CC voltage regulator output
V
V
V
CCREG, drop
I
SREG, drop
P
CC
REGOUT
REGOUT
V
SREG to
V
CC dropout voltage
Internal V
CC dissipation voltage regulator power
Internal V
REG voltage voltage regulator output
V
CCREG to V
REG dropout voltage
Internal V
REG current voltage regulator output
Low (default), I
CC
= 10 mA
High, I
CC
= 10 mA
I
CC
= 50 mA
I
REG
= 10 mA
I
REG
= 50 mA
7.3
14
3.13
5
7.5
15
3.3
125
3
2.5
3
V
V
W
V
V mA
DS9836 Rev 7 15/92
92
Electrical characteristics powerSTEP01
Symbol
Table 4. Electrical characteristics (continued)
Parameter
I
REGOUT,STBY
Internal V
REG voltage regulator output standby current
P
REG
Internal V
REG dissipation voltage regulator power
Test conditions Min.
Typ.
Max. Unit
55 mA
0.5
W
Integrated analog-to-digital converter
N
ADC
Analog-to-digital converter resolution 5
V
ADC,ref
Analog-to-digital converter reference voltage
3.3
f
S
Analog-to-digital converter sampling frequency
Voltage mode
(2)
Current mode
(2)
V
ADC,UVLO
ADCIN UVLO threshold
1. Guaranteed in the temperature range -25 to 125 ° C .
2. The value accuracy is dependent on oscillator frequency accuracy ( Section 7.8 on page 29 ).
3. FLAG and BUSY open-drain outputs included.
.
f
PWM f
OSC
/512
1.05
1.16
bit
V kHz kHz
1.35
V
16/92 DS9836 Rev 7
powerSTEP01
4 Pin connection
Figure 2. Pin connection (top view)
Pin connection
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Note: All VS pins and pads must be connected together.
Pins 34, 35, 36, EPAD10 (SENSEA2_P) must be connected to pins 39, 40, 41, EPAD11
(SENSEA1_P)
Pins 77, 78, 79, EPAD12 (SENSEB1_P) must be connected to pins 82, 83, 84, EPAD13
(SENSEB2_P)
DS9836 Rev 7 17/92
92
Pin list
5 Pin list
powerSTEP01
No.
Name
Table 5. Pin description
Type Function
1, 2, 3, 4, 5, 6, 23, 24,
25, 26, 27, 28, 29, 30,
31, 32, 43, 44, 45, 46,
47, 48, 49, 50, 51, 52,
66, 67, 68, 69, 70, 71,
72, 73, 74, 75, 86, 87,
88, 89, EPAD1,
EPAD2, EPAD5,
EPAD6
38, 42, 53, EPAD4
22, 33, 37, EPAD3
65, 76, 80, EPAD7
7, 81, 85, EPAD8
8, 21, 59, EPAD9
34, 35, 36, EPAD10
39, 40, 41, EPAD11
VS
OUTA1
OUTA2
OUTB1
OUTB2
GND
SENSEA2_P
SENSEA1_P
Supply Motor supply voltage (drain of the high-side MOSFETs)
Power output Half-bridge A1 output
Power output Half-bridge A2 output
Power output Half-bridge B1 output
Power output Half-bridge B2 output
Ground Ground
Sense
(power)
Sense
(power)
Tail of half-bridge A2 (source of the respective low-side
MOSFET)
(2)
Tail of half-bridge A1 (source of the respective low-side
(1)
20
77, 78, 79, EPAD12
SENSEA_S Analog input Current control comparator input
SENSEB1_P
Sense
(power)
Tail of half-bridge B1 (source of the respective low-side
MOSFET)
(3)
82, 83, 84, EPAD13
9
SENSEB2_P
Sense
(power)
Tail of half-bridge B2 (source of the respective low-side
SENSEB_S Analog input Current control comparator input
60
62
13
61
58
63
64
VCCREG
VREG
VDDIO
VSREG
VCC
OSCIN
OSCOUT
Power supply Internal V
REG
voltage regulator supply voltage
Power supply Logic supply voltage
Power supply
Power supply Internal V
CC
voltage regulator supply voltage
Power supply Gate driver supply voltage
Analog input
Analog output
Logic interface supply voltage
Oscillator pin 1. To connect an external oscillator or clock source
Oscillator pin 2. To connect an external oscillator. When the internal oscillator is used this pin can supply a 2/4/8/16
MHz clock
57
56
54
CP
VBOOT
ADCIN
Output
Power supply
Charge pump oscillator output
Bootstrap voltage needed for driving the high-side power
DMOS of both bridges (A and B)
Analog input Internal analog-to-digital converter input
18/92 DS9836 Rev 7
powerSTEP01 Pin list
No.
Name
Table 5. Pin description (continued)
Type Function
55
18
14
12
11
10
15
16
19
VS
SW
SDO
SDI
CK
CS
BUSY
/SYNC
FLAG
STBY
/RESET
Power supply Motor supply voltage
Logical input External switch input pin
Logic output Data output pin for serial interface
Logic input Data input pin for serial interface
Logic input Serial interface clock
Logic input Chip select input pin for serial interface
Open-drain output
Open-drain output
By default BUSY/SYNC pin is forced low when the device is performing a command.
The pin can be programmed in order to generate a synchronization signal
Status flag pin. An internal open-drain transistor can pull the pin to GND when a programmed alarm condition occurs (step loss, OCD, thermal pre-warning or shutdown,
UVLO, wrong command, non performable command)
Logic input
Standby and reset pin. Low logic level puts the device in standby mode and reset logic.
If not used, should be connected to V
REG
Logic input Step clock input 17 STCK
1. All VS pins and pads must be connected together
2. Pins 34, 35, 36, EPAD10 (SENSEA2_P) must be connected to pins 39, 40, 41, EPAD11 (SENSEA1_P)
3. Pins 77, 78, 79, EPAD12 (SENSEB1_P) must be connected to pins 82, 83, 84, EPAD13 (SENSEB2_P)
DS9836 Rev 7 19/92
92
Typical applications
6 Typical applications
Name
C
VSPOL
C
VS
C
BOOT
C
FLY
C
VSREG
C
VCC
C
VCCREG
C
VREG
C
VREGPOL
C
VDD
D1
R
PU
R
A
R
B
R
SENSEA
R
SENSEB
Table 6. Typical application values
Value
220 μF
220 nF
470 nF
47 nF
100 nF
470 nF
100 nF
100 nF
22 μF
100 nF
Charge pump diodes
39 kΩ
1.8 kΩ (V
S
= 85 V)
91 kΩ (V
S
= 85 V)
0.1 Ω (maximum I peak
= 10 A)
0.1 Ω (maximum I peak
= 10 A) powerSTEP01
20/92 DS9836 Rev 7
powerSTEP01
3
16
)045
Typical applications
3
16
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Figure 3. Typical application schematic - voltage mode
7
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0R U RU
+267
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38
Figure 4. Typical application schematic - current mode
5
38
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DS9836 Rev 7 21/92
92
Functional description
7 Functional description
7.1
powerSTEP01
Device power-up
During power-up, the device is under reset (all logic IOs disabled and power bridges in high impedance state) until the following conditions are satisfied:
V
REG
is greater than V
REGthOn
Internal oscillator is operative
STBY/RESET input is forced high.
After power-up, the device state is the following:
Parameters are set to default
Internal logic is driven by internal oscillator and a 2-MHz clock is provided by the
OSCOUT pin
Bridges are disabled (high impedance).
FLAG output is forced low (UVLO failure indication).
After power-up, a period of t logicwu oscillator and logic startup.
must pass before applying a command to allow proper
Any movement command makes the device exit from High Z state (HardStop and SoftStop included).
7.2
7.3
Logic I/O
Pins CS, CK, SDI, STCK, SW and STBY/RESET are TTL/CMOS 3.3 V to 5 V compatible logic inputs.
Pin SDO is a TTL/CMOS compatible logic output. VDD pin voltage imposes logical output voltage range.
Pins FLAG and BUSY/SYNC are open-drain outputs.
SW and CS inputs are internally pulled up to V
DD down to ground.
and STBY/RESET input is internally pulled
Charge pump
To ensure the correct driving of the high-side integrated MOSFETs, a voltage higher than the motor power supply voltage needs to be applied to the VBOOT pin. The high-side gate driver supply voltage V
BOOT
is obtained through an oscillator and a few external components realizing a charge pump (see
22/92 DS9836 Rev 7
powerSTEP01
9
6
9
&3
9
'
9
'
WRKLJKVLGH
JDWHGULYHUV
Figure 5. Charge pump circuitry
9
6
9
&3
9
'
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9
6
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)/<
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9
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9
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Functional description
$0Y
7.4 Microstepping
The driver is able to divide the single step into up to 128 microsteps. Stepping mode can be
programmed by the STEP_SEL parameter in the STEP_MODE register ( Table 27 on page 61
). In current mode driving the maximum microstepping resolution is 1/16 th of the step.
Step mode can only be changed when bridges are disabled. Every time the step mode is changed, the electrical position (i. e. the point of microstepping sinewave that is generated)
is reset to zero and the absolute position counter value ( Section 7.5
) becomes meaningless.
Figure 6. Normal mode and microstepping (128 microsteps)
Reset position
Normal driving
PHASE A current
PHASE B current
Reset position
Microstepping
PHASE A current
PHASE B current microsteps step 1 step 2 step 3 step 4 step 1 step 1 step 2 step 3 step 4 step 1
128
μsteps
128
μsteps
128
μsteps
128
μsteps
AM12828v1
DS9836 Rev 7 23/92
92
Functional description powerSTEP01
Automatic full-step and boost modes
When motor speed is greater than a programmable full-step speed threshold, the device switches automatically to Full-step mode; the driving mode returns to microstepping when motor speed decreases below the full-step speed threshold.
The switching between the microstepping and Full-step mode and vice-versa is always performed at an electrical position multiple of /4 (
Full-step speed threshold is set through the related parameter in the FS_SPD register
).
When the BOOST_MODE bit of the FS_SPD register is low (default), the amplitude of the voltage squarewave in Full-step mode is equal to the peak of the voltage sinewave multiplied by sine( /4) (
Figure 7 ). This avoids the current drop between the two driving
modes.
When the BOOST_MODE bit of the FS_SPD register is high, the amplitude of the voltage squarewave in Full-step mode is equal to the peak of the voltage sinewave (
improves the output current increasing the maximum motor torque.
Figure 7. Automatic full-step switching in normal mode
V peak
Phase A
)x V peak
Phase B
Microstepping
(2N+1) x π /4
Full-step
(2N+1) x π /4
Microstepping
AM12829v1
24/92 DS9836 Rev 7
powerSTEP01
V peak
Phase A
Functional description
Figure 8. Automatic full-step switching in boost mode
V peak
Phase B
7.5
7.6
Microstepping
(2N+1) x π /4
Full-step
(2N+1) x π/4
Microstepping
AM12850v1
Absolute position counter
An internal 22-bit register (ABS_POS) records all the motor motions according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). The position range is from -2 21 to +2 21 -1 steps (see
Programmable speed profiles
The user can easily program a customized speed profile defining independently acceleration, deceleration, maximum and minimum speed values by ACC, DEC,
MAX_SPEED and MIN_SPEED registers respectively (see
11.1.6 on page 54 , 11.1.7 on page 54
and
).
When a command is sent to the device, the integrated logic generates the microstep frequency profile that performs a motor motion compliant to speed profile boundaries.
All acceleration parameters are expressed in step/tick
2
and all speed parameters are expressed in step/tick; the unit of measurement does not depend on the selected step mode. Acceleration and deceleration parameters range from 2
-40
to (2
12
-2)
·
2
-40
step/tick
(equivalent to 14.55 to 59590 step/s
2
).
2
Minimum speed parameter ranges from 0 to (2
12 step/s).
-
1
)
·
2
-24
step/tick (equivalent to 0 to 976.3
Maximum speed parameter ranges from 2
-18
15610 step/s).
to (2
10
-1)
·
2
-18
step/tick (equivalent to 15.25 to
DS9836 Rev 7 25/92
92
Functional description
7.7
7.7.1
7.7.2
Motor control commands
The powerSTEP01 can accept different types of commands:
constant speed commands (Run, GoUntil, ReleaseSW)
absolute positioning commands (GoTo, GoTo_DIR, GoHome, GoMark)
motion commands (Move)
stop commands (SoftStop, HardStop, SoftHiz, HardHiz).
For detailed command descriptions refer to
powerSTEP01
Constant speed commands
A constant speed command produces a motion in order to reach and maintain a userdefined target speed starting from the programmed minimum speed (set in the MIN_SPEED register) and with the programmed acceleration/deceleration value (set in the ACC and DEC registers). A new constant speed command can be requested anytime.
Figure 9. Constant speed command examples
Speed
(step frequency)
SPD3
SPD1
SPD2
Minimum speed
Minimum speed
SPD4
Run(SPD2,FW)
Run(SPD1,FW)
Run(SPD3,FW)
Run(SPD4,BW) time
AM12856v1
Positioning commands
An absolute positioning command produces a motion in order to reach a user-defined position that is sent to the device together with the command. The position can be reached performing the minimum path (minimum physical distance) or forcing a direction (see
).
Performed motor motion is compliant to programmed speed profile boundaries
(acceleration, deceleration, minimum and maximum speed).
Note that with some speed profiles or positioning commands, the deceleration phase can start before the maximum speed is reached.
26/92 DS9836 Rev 7
powerSTEP01 Functional description
Figure 10. Positioning command examples
0
Forward direction
0
7.7.3
7.7.4
Present position
Present position
-2 21 +2 21 -1
GoTo(Target pos)
Target position
-2 21 +2 21 -1
GoTo_DIR(Target pos,FW)
Target position
AM12857v1
Motion commands
Motion commands produce a motion in order to perform a user-defined number of microsteps in a user-defined direction that are sent to the device together with the command
Performed motor motion is compliant to programmed speed profile boundaries
(acceleration, deceleration, minimum and maximum speed).
Note that with some speed profiles or motion commands, the deceleration phase can start before the maximum speed is reached.
Figure 11. Motion command examples
SPEED programmed maximum speed programmed number of microsteps programmed minimum speed programmed
ACCELERATION programmed
DECELERATION
SPEED programmed maximum speed programmed
ACCELERATION programmed number of microsteps
Note: with some acceleration/decelaration profiles the programmed maximum speed
is never reached programmed
DECELERATION programmed minimum speed time
AM15163v1 time
Stop commands
A stop command forces the motor to stop. Stop commands can be sent anytime.
The SoftStop command causes the motor to decelerate with a programmed deceleration value until MIN_SPEED value is reached and then stops the motor keeping the rotor position (a holding torque is applied).
DS9836 Rev 7 27/92
92
Functional description
7.7.5
7.7.6 powerSTEP01
The HardStop command stops the motor instantly, ignoring deceleration constraints and keeping the rotor position (a holding torque is applied).
The SoftHiZ command causes the motor to decelerate with a programmed deceleration value until the MIN_SPEED value is reached and then forces the bridges into high impedance state (no holding torque is present).
The HardHiZ command instantly forces the bridges into high impedance state (no holding torque is present).
Step-clock mode
In Step-clock mode the motor motion is defined by the step-clock signal applied to the STCK pin. At each step-clock rising edge, the motor is moved one microstep in the programmed direction and absolute position is consequently updated.
When the system is in Step-clock mode the SCK_MOD flag in the STATUS register is raised, the SPEED register is set to zero and motor status is considered stopped regardless of the STCK signal frequency (the MOT_STATUS parameter in the STATUS register equal to “00”).
GoUntil and ReleaseSW commands
In most applications the power-up position of the stepper motor is undefined, so an initialization algorithm driving the motor to a known position is necessary.
The GoUntil and ReleaseSW commands can be used in combination with external switch input (see
Section 7.14 on page 33 ) to easily initialize the motor position.
The GoUntil command makes the motor run at target constant speed until the SW input is forced low (falling edge). When this event occurs, one of the following actions can be performed:
ABS_POS register is set to zero (home position) and the motor decelerates to zero speed (as a SoftStop command)
ABS_POS register value is stored in the MARK register and the motor decelerates to zero speed (as a SoftStop command).
If the SW_MODE bit of the CONFIG register is set to ‘0’, the motor does not decelerate but it immediately stops (as a HardStop command).
The ReleaseSW command makes the motor run at a programmed minimum speed until the
SW input is forced high (rising edge). When this event occurs, one of the following actions can be performed:
ABS_POS register is set to zero (home position) and the motor immediately stops (as a HardStop command)
ABS_POS register value is stored in the MARK register and the motor immediately stops (as a HardStop command).
If the programmed minimum speed is less than 5 step/s, the motor is driven at 5 step/s.
28/92 DS9836 Rev 7
powerSTEP01
7.8
Functional description
Internal oscillator and oscillator driver
The control logic clock can be supplied by the internal 16-MHz oscillator, an external oscillator (crystal or ceramic resonator) or a direct clock signal.
These working modes can be selected by EXT_CLK and OSC_SEL parameters in the
CONFIG register (see Table 41 on page 66 ).
At power-up the device starts using the internal oscillator and provides a 2-MHz clock signal on the OSCOUT pin.
Attention: In any case, before changing clock source configuration, a hardware reset is mandatory. Switching to different clock configurations during operation may cause unexpected behavior.
7.8.1
7.8.2
Internal oscillator
In this mode the internal oscillator is activated and OSCIN is unused. If the OSCOUT clock source is enabled, the OSCOUT pin provides a 2, 4, 8 or 16-MHz clock signal (according to
OSC_SEL value); otherwise it is unused (see
External clock source
Two types of external clock source can be selected: crystal/ceramic resonator or direct clock source. Four programmable clock frequencies are available for each external clock source:
8, 16, 24 and 32-MHz.
When an external crystal/resonator is selected, the OSCIN and OSCOUT pins are used to
drive the crystal/resonator (see Figure 12
). The crystal/resonator and load capacitors (C
L
) must be placed as close as possible to the pins. Refer to
Table 7 for the choice of the load
capacitor value according to the external oscillator frequency.
Table 7. CL values according to external oscillator frequency
Crystal/resonator freq.
(1) C
L
(2)
8 MHz
16 MHz
24 MHz
32 MHz
25 pF (ESR max
= 80 )
18 pF (ESR max
= 50 )
15 pF (ESR max
= 40 )
10 pF (ESR max
= 40 )
1. First harmonic resonance frequency.
2. Lower ESR value allows driving greater load capacitors.
If a direct clock source is used, it must be connected to the OSCIN pin and the OSCOUT pin
supplies the inverted OSCIN signal (see Figure 12
).
The powerSTEP01 integrates a clock detection system that resets the device in case of the failure of the external clock source (direct or crystal/resonator). The monitoring of the clock source is disabled by default, it can be enabled setting high the WD_EN bit in the
DS9836 Rev 7 29/92
92
Functional description powerSTEP01
GATECFG1 register ( Section 11.1.25 on page 63 ). When the external clock source is
selected, the device continues to work with the integrated oscillator for t extosc and then the clock management system switches to the OSCIN input.
milliseconds
Figure 12. OSCIN and OSCOUT pin configuration
EXT_CLK = "0" EXT_CLK = "1"
8/16/24/32 MHz
C
L
8/16/24/32 MHz
C
L
OSC_SEL = "1xx"
OSCIN OSCOUT
External oscillator configuration
OSCIN OSCOUT
External clock source configuration
2/4/8/16 MHz
Note:
7.9
OSC_SEL = "0xx"
UNUSED UNUSED
OSCIN OSCOUT
Internal oscillator configuration without clock source
UNUSED
OSCIN OSCOUT
Internal oscillator configuration with clock generation
AM12830v1
When OSCIN is UNUSED, it should be left floating.
When OSCOUT is UNUSED, it should be left floating.
Overcurrent detection
The powerSTEP01 measures the load current of each half-bridge sensing the V
DS of the integrated MOSFET (
Figure 13 ). When any of the V
DS
voltage
voltages rise over the programmed threshold, the OCD flag in the STATUS register is forced low until the event expires and a GetStatus command is sent to the device (
and
Section 11.2.20 on page 82 ). The overcurrent event expires when all the MOSFET V
DS voltages fall below the programmed threshold.
The overcurrent threshold can be programmed by the OCD_TH register in one of 32 available values listed in
.
30/92 DS9836 Rev 7
powerSTEP01 Functional description
Figure 13. Overcurrent detection - principle scheme
VS
LOGIC CORE
OCD_HSxx
-
+
Voltage
Comparator
BLANKING
OUTxx
OC
THRESHOLD
CURRENT
DAC
OCD_LSxx
Voltage
Comparator
+
-
GND
GND
AM16762v1
The overcurrent detection comparators are disabled, in order to avoid wrong voltage measurements, in following cases:
The respective half-bridge is in high impedance state (both MOSFETs forced off)
The respective half-bridge is commutating
The respective half-bridge is commutated and the programmed blanking time is not elapsed yet
The respective gate is turned off
It is possible to set if an overcurrent event causes the bridges turn-off or not through the
OC_SD bit in CONFIG register.
When the power bridges are turned off by an overcurrent event, they cannot be turned on until the OCD flag is released by a GetStatus command.
7.10 Undervoltage lockout (UVLO)
The powerSTEP01 provides a programmable gate driver supply voltage UVLO protection.
When one of the supply voltages of the gate driver (V
CC
for the low-sides and V
BOOT
- V
S for the high-sides) falls below the respective turn-off threshold, an undervoltage event occurs. In this case, all MOSFETs are immediately turned off and the UVLO flag in the
STATUS register is forced low.
The UVLO flag is forced low and the MOSFETs are kept off until the gate driver supply voltages return to above the respective turn-on threshold; in this case the undervoltage event expires and the UVLO flag can be released through a GetStatus command.
The UVLO thresholds can be selected between two sets according to the UVLOVAL bit value in the CONFIG register.
DS9836 Rev 7 31/92
92
Functional description powerSTEP01
Table 8. UVLO thresholds
Description
Low-side gate driver supply turn-off threshold (V
CCthOff
)
Low-side gate driver supply turn-on threshold (V
CCthOn
)
High-side gate driver supply turn-off threshold ( V
BOOTthOff
)
High-side gate driver supply turn-on threshold ( V
BOOTthOn
)
0
6.3 V
6.9 V
5.5 V
6 V
UVLOVAL
1
10 V
10.4 V
8.8 V
9.2 V
7.11 V
S
undervoltage lockout (UVLO_ADC)
The device provides an undervoltage signal of the integrated ADC input voltage (the
UVLO_ADC flag in the STATUS register). When V
ADCIN falls below the V
ADC,UVLO
value the
UVLO_ADC flag is forced low and it is kept in this state until the ADCIN voltage is greater than V
ADC,UVLO and a GetStatus command is sent to the device.
The ADCIN undervoltage event doesn’t turn-off the power bridges.
The motor supply voltage undervoltage detection can be performed by means of this feature, connecting the ADCIN pin to V
S
through a voltage divider as described in
7.12 Thermal warning and thermal shutdown
An integrated sensor allows detection of the internal temperature and implementation of a 3-level protection.
When the T j(WRN)Set
threshold is reached, a warning signal is generated. This is the thermal warning condition and it expires when the temperature falls below the T j(WRN)Rel
threshold.
When the T j(OFF)Set
threshold is reached, all the MOSFETs are turned off and the gate driving circuitry is disabled (Miller clamps are still operative). This condition expires when the temperature falls below the T j(OFF)Rel
threshold.
When the T j(SD)OFF clamps, the internal V
CC internal V
REG
threshold is reached, all the MOSFETs are turned off using Miller
voltage regulator is disabled and the current capability of the
voltage regulator is reduced (thermal shutdown). In this condition logic is still active (if supplied). The thermal shutdown condition only expires when the temperature goes below T j(SD)ON
.
The thermal condition of the device is shown by TH_STATUS bits in the STATUS register
32/92 DS9836 Rev 7
powerSTEP01 Functional description
State
Normal
Warning
Bridge shutdown
Device shutdown
Table 9. Thermal protection summarizing table
Set condition Release condition
T j > Tj(WRN)Set
T j > Tj(OFF)Set
T j > Tj(SD)Set
T j< Tj(WRN)Rel
T j < Tj(OFF)Rel
T j < Tj(SD)Rel
Description
Normal operation state
Temperature warning: operation is not limited
High temperature protection: the
MOSFETs are turned of and the gate drivers are disabled
Overtemperature protection: the
MOSFETs are turned off, the gate drivers are disabled, the internal V
CC voltage regulator is disabled, the current capability of the internal V
REG
voltage regulator is limited, and the charge pump is disabled
TH_STATUS
00
01
10
11
7.13 Reset and standby
The device can be reset and put into Standby mode through the STBY/RESET pin. When it is forced low, all the MOSFETs are turned off (High Z state), the charge pump is stopped, the SPI interface and control logic are disabled and the internal V
REG
voltage regulator maximum output current is limited; as a result, the powerSTEP01 heavily reduces the power consumption. At the same time the register values are reset to their default and all the protection functions are disabled. The STBY/RESET input must be forced low at least for t
STBY,min
in order to ensure the complete switch to Standby mode.
On exiting Standby mode, as well as for IC power-up, a delay must be given before applying a new command to allow proper oscillator and charge pump startup. Actual delay could vary according to the values of the charge pump external components.
On exiting Standby mode all the MOSFETs are off and the HiZ flag is high.
The registers can be reset to the default values without putting the device into Standby mode through the ResetDevice command (
).
7.14 External switch (SW pin)
The SW input is internally pulled up to V
DD
).
and detects if the pin is open or connected to
The SW_F bit of the STATUS register indicates if the switch is open (‘0’) or closed (‘1’)
( Section 11.1.28 on page 71 ); the bit value is refreshed at every system clock cycle
(125 ns). The SW_EVN flag of the STATUS register is raised when a switch turn-on event
(SW input falling edge) is detected ( Section 11.1.28
). A GetStatus command releases the
SW_EVN flag (
By default, a switch turn-on event causes a HardStop interrupt (SW_MODE bit of CONFIG register set to ‘0’). Otherwise (SW_MODE bit of CONFIG register set to ‘1’), switch input events do not cause interrupts and the switch status information is at the user’s disposal
).
DS9836 Rev 7 33/92
92
Functional description powerSTEP01
The switch input can be used by GoUntil and ReleaseSW commands as described in
Section 11.2.10 on page 78 and
If the SW input is not used, it should be connected to V
DD
.
Figure 14. External switch connection
V
DD
External switch
SW
AM12833v1
7.15 Integrated power MOSFETs
The typical characteristics of the 8 N-channel MOSFETs integrated into the system-inpackage are listed in
.
Symbol
V
GS(th)
Q g
V
SD
Table 10. Integrated MOSFETs characteristics at T j
= 25 °C
Parameter Typical value
Gate threshold voltage
Total gate charge at V gs
= 10 V
Source-drain diode forward on voltage at I
SD
= 10 A
3
25
0.8
Unit
V nC
V
7.16 Programmable slew rate
The powerSTEP01 integrates eight programmable gate drivers which allow the output slew rate to be fixed in a wide range of values.
The following parameters can be adjusted:
– Gate sink/source current (I
GATE
)
– controlled current time (t
CC
)
– Turn-off over-boost time (t
OB
)
During the turn-on, the gate driver charges the gate forcing an I
GATE
current for all the controlled current time period. At the end of the controlled current phase the gate of the integrated MOSFET should be completely charged.
During the turn-off the gate driver discharges the gate sinking an I
GATE
current for all the controlled current time period. At the beginning of the turn-off an overboost phase can be added: in this case the gate driver sinks an I
OB
current for the programmed t
OB
period in order to rapidly reach the plateau region. At the end of the controlled current time the gate of the integrated MOSFET should be completely discharged.
34/92 DS9836 Rev 7
powerSTEP01 Functional description
The gate current can be set to one of following values: 4, 8, 16, 24, 32, 64 and 96 mA through the I
GATE
parameter in the GATECFG1 register.
Controlled current time can be programmed within range from 125 ns to 3.75 μs with a resolution 125 ns (TCC parameter in GATECFG1 register).
Turn-off overboost time can be set to one of following values: 0, 62.5, 125, 250 ns (TBOOST parameter in GATECFG1 register). The 62.5 ns value is only available when clock frequency is 16 MHz or 32 MHz; when clock frequency is 8 MHz it is changed to 125 ns and when a 24 MHz clock is used it is changed to 83.3 ns.
Table 11. Output slew rate
Slew rate
(V
S
= 48 V)
I gate
980 V/μs 96 mA
790 V/μs 64 mA
520 V/μs 32 mA
400 V/μs 24 mA
220 V/μs 16 mA
114 V/μs 8 mA
t
CC
375 ns
500 ns
875 ns
1000 ns
1600 ns
3125 ns
t
DT
125 ns
125 ns
125 ns
125 ns
125 ns
125 ns
t blank
500 ns
375 ns
250 ns
250 ns
250 ns
250 ns
t boost
0 ns
0 ns
0 ns
0 ns
0 ns
0 ns
7.17 Deadtime and blanking time
During the bridge commutation, a deadtime is added in order to avoid cross conductions.
The deadtime can be programmed within a range from 125 ns to 4 s with a resolution of
125 ns (TDT parameter in the GATECFG2 register) (see
At the end of each commutation the overcurrent and stall detection comparators are disabled (blanking) in order to avoid the respective systems detecting body diodes turn-off current peaks.
The duration of blanking time is programmable through the TBLANK parameter in the
GATECFG2 register at one of the following values: 125, 250, 375, 500, 625, 750, 875, 1000 ns (see
).
7.18 Integrated analog-to-digital converter
The powerSTEP01 integrates an N
ADC reference voltage equal to V
REG
bit ramp-compare analog to digital converter with a
. The analog to digital converter input is available through the ADCIN pin and the conversion result is available in the ADC_OUT register
( Section 11.1.20 on page 60 ).
The ADC_OUT value can be used for motor supply voltage compensation or can be at the user’s disposal.
DS9836 Rev 7 35/92
92
Functional description powerSTEP01
7.19 Supply management and internal voltage regulators
The powerSTEP01 integrates two linear voltage regulators: the first one can be used to obtain gate driver supply starting from a higher voltage (e.g.: the motor supply one). Its output voltage can be set to 7.5 V or 15 V according to the VCCVAL bit value (CONFIG register). The second linear voltage regulator can be used to obtain the 3.3 V logic supply voltage.
The regulator is designed to supply the internal circuitry of the IC and should not be used to supply external components.
The input and output voltages of both regulators are connected to external pins and the regulators are totally independent: in this way a very flexible supply management can be performed using external components or external supply voltages (
Figure 15. Device supply pin management
All voltages are internally generated
VBOOT
CP
VBUS
VS
7V5 - 15V
3V3
VSREG
V CC
VCCREG
VREG
All voltages are externally supplied
VBOOT
CP
V S
VBUS
7V5 - 15V
Using external components
(zener diodes, resistors, ...) it is possible to reduce internal power dissipation constrains.
VSREG
V CC
3V3
VCCREG
VREG
3.3 V
VCC
AM12834v1
If V
CC
is externally supplied, the VSREG and VCC pins must be shorted (V
SREG compliant with V
CC
range).
must be
If V
REG
3.3 V.
is externally supplied, the VCCREG and VREG pins must be shorted and equal to
V
SREG
must be always less than V
BOOT
in order to avoid related ESD protection diode turnon. The device can be protected from this event by adding an external low drop diode between the VSREG and VS pins, charge pump diodes should be low drop too.
V
CCREG
must be always less than V
CC
in order to avoid ESD protection diode turn-on. The device can be protected from this event by adding an external low drop diode between the
VCCREG and VSREG pins.
Both regulators provide a short circuit protection limiting the load current within the respective maximum ratings.
36/92 DS9836 Rev 7
powerSTEP01 Functional description
7.20 BUSY/SYNC pin
This pin is an open-drain output which can be used as busy flag or synchronization signal
according to the SYNC_EN bit value (STEP_MODE register) (see Section 11.1.23 on page
7.21 FLAG pin
By default, an internal open-drain transistor pulls the FLAG pin to ground when at least one of the following conditions occurs:
Power-up or standby/reset exit
Stall detection on bridge A
Stall detection on bridge B
Overcurrent detection
Thermal warning
Thermal shutdown
UVLO
UVLO on ADC input
Switch turn-on event
Command error
It is possible to mask one or more alarm conditions by programming the ALARM_EN
register (see Table 32 on page 63 ). If the corresponding bit of the ALARM_EN register is
low, the alarm condition is masked and it does not cause a FLAG pin transition; all other actions imposed by alarm conditions are performed anyway. In case of daisy chain configuration, FLAG pins of different ICs can be or-wired to save host controller GPIOs.
DS9836 Rev 7 37/92
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Phase current control: voltage mode
8 Phase current control: voltage mode
powerSTEP01
When the voltage mode driving is selected (CM_VM bit in STEP_MODE register is set to 0), the powerSTEP01 controls the phase current applying a sinusoidal voltage to motor windings. Phase current amplitude is not directly controlled but depends on phase voltage amplitude, load torque, motor electrical characteristics and rotation speed. Sinewave amplitude is proportional to the motor supply voltage multiplied by a coefficient (K
VAL
). K
VAL ranges from 0 to 100% and the sinewave amplitude can be obtained through the following formula:
Equation 1
V
OUT
= V
S
K
VAL
Different K
VAL
values can be programmed for acceleration, deceleration and constant speed phases and when the motor is stopped (HOLD phase) through KVAL_ACC, KVAL_DEC,
KVAL_RUN and KVAL_HOLD registers (
Section 11.1.10 on page 56 ). KVAL value is
calculated according to the following formula:
Equation 2
K
VAL
= K
VAL_X
+ BEMF_COMP microst ep where K
VAL_X
is the starting K
VAL value programmed for the present motion phase
(KVAL_ACC, KVAL_DEC, KVAL_RUN or KVAL_HOLD), BEMF_COMP is the BEMF compensation curve value, VSCOMP and K_THERM are the motor supply voltage and winding resistance compensation factors and microstep is the current microstep value
(fraction of target peak current).
The powerSTEP01 offers various methods to guarantee a stable current value, allowing the compensation of:
Low speed distortion (
Back electromotive force (
Motor supply voltage variation ( Section 8.5
)
Winding resistance variation ( Section 8.6 on page 42 )
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powerSTEP01
8.1
Phase current control: voltage mode
PWM sinewave generators
The two voltage sinewaves applied to the stepper motor phases are generated by two PWM modulators.
The PWM frequency (f
PWM
) is proportional to the oscillator frequency (f
OSC
) and can be obtained through the following formula:
Equation 3 f
PWM
= f
OSC
512 N
m
' N ' is the integer division factor and ' m ' is the multiplication factor. 'N' and 'm' values can be programmed by F_PWM_INT and F_PWM_DEC parameters in the CONFIG register (see
and
Available PWM frequencies are listed in Section 11.1.27 on page 66 from
to
.
8.2 Sensorless stall detection
The powerSTEP01 is able to detect a motor stall caused by an excessive load torque. When the motor is driven using the voltage mode approach, a stall condition corresponds to an unexpected increase of the phase current. Imposing a current threshold slightly above the operative current, it is possible to detect the stall condition without speed or position sensors.
The powerSTEP01 measures the load current of each phase sensing the V
DS low-side power MOSFETs. When any of the V
DS
voltage of the
voltages rise over the programmed threshold, the STEP_LOSS_X flag in the STATUS register of the respective bridge
(STEP_LOSS_A or STEP_LOSS_B) is forced low. The failure flag is kept low until the V
DS voltages fall below the programmed threshold and a GetStatus command is sent to the device (
and Section 11.2.20 on page 82 ).
The stall detection threshold can be programmed in one of 32 available values ranging from
31.25 mV to 1 V with steps of 31.25 mV (see
).
Stall detection comparators are disabled, in order to avoid wrong voltage measurements, in the following cases:
The respective half-bridge is in high impedance state (both MOSFETs forced off)
The respective half-bridge is commutating
The respective half-bridge is commutated and the programmed blanking time has not yet elapsed
The respective low-side gate is turned off
8.3 Low speed optimization
When the motor is driven at a very low speed using a small driving voltage, the resulting phase current can be distorted. As a consequence, the motor position is different from the ideal one (see
The device implements a low speed optimization in order to remove this effect.
DS9836 Rev 7 39/92
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Phase current control: voltage mode
Figure 16. Current distortion and compensation
Without low speed optimizazion
I phase powerSTEP01
W ith low speed optimizazion
I phase
Current distortion is heavily reduced
8.4
AM12851v1
The optimization can be enabled setting high the LSPD_OPT bit in the MIN_SPEED register
) and is active in a speed range from zero to MIN_SPEED. When low speed optimization is enabled, speed profile minimum speed is forced to zero.
BEMF compensation
Using the speed information, a compensation curve is added to the amplitude of the voltage waveform applied to the motor winding in order to compensate the BEMF variations during acceleration and deceleration (see
The compensation curve is approximated by a stacked line with a starting slope (ST_SLP) when speed is lower than a programmable threshold speed (INT_SPEED) and a fine slope
(FN_SLP_ACC and FN_SLP_DEC) when speed is greater than the threshold speed (see
,
and
40/92 DS9836 Rev 7
powerSTEP01
8.5
Phase current control: voltage mode
Figure 17. BEMF compensation curve
Compensation value
FN_SLP_ACC
FN_SLP_DEC
ST_SLP
INT_SPEED Speed
AM12835v1
To obtain different current values during acceleration and deceleration phase, two different final slope values, and consequently two different compensation curves, can be programmed.
Acceleration compensation curve is applied when the motor runs. No BEMF compensation is applied when the motor is stopped.
Motor supply voltage compensation
The sinewave amplitude generated by the PWM modulators is directly proportional to the motor supply voltage (V
S
). When the motor supply voltage is different from its nominal value, the motor phases are driven with an incorrect voltage. The powerSTEP01 can compensate motor supply voltage variations in order to avoid this effect.
The motor supply voltage should be connected to the integrated ADC input through a resistor divider in order to obtain V
REG nominal value (see
/2 voltage at the ADCIN pin when V
S
is at its
The ADC input is sampled at f
S
frequency, which is equal to PWM frequency.
Figure 18. Motor supply voltage compensation circuit
V
S
V
REG
R
A
ADCIN
5
V
ADCIN
= V
S
x R
B
/ (R
A
+ R
B
) ADC
ADC_OUT
R
B f
PWM
AM12836v1
DS9836 Rev 7 41/92
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Phase current control: voltage mode powerSTEP01
Motor supply voltage compensation can be enabled setting high the EN_VSCOMP bit of the
CONFIG register (see
). If the EN_VSCOMP bit is low, the compensation is disabled and the internal analog to digital converter is at the user’s disposal; the sampling rate is always equal to PWM frequency.
8.6 Winding resistance thermal drift compensation
The higher the winding resistance the greater the voltage to be applied in order to obtain the same phase current.
The powerSTEP01 integrates a register (K_THERM) which can be used to compensate phase resistance increment due to temperature rising.
The value in the K_THERM register (
) multiplies duty cycle value allowing the higher phase resistance value to be faced.
The compensation algorithm and the eventual motor temperature measurement should be implemented by microcontroller firmware.
42/92 DS9836 Rev 7
powerSTEP01
9
Phase current control: current mode
Phase current control: current mode
When the current mode driving is selected (CM_VM bit in STEP_MODE register is set to 1), the powerSTEP01 performs a new current control technique, named predictive current control, allowing the device to obtain the target average phase current. This method is
described in detail in Section 9.1
. Furthermore, the powerSTEP01 automatically selects the
better decay mode in order to follow the current profile.
Current control algorithm parameters can be programmed by T_FAST, TON_MIN,
TOFF_MIN and CONFIG registers (see
Section 11.1.11 on page 56 , 11.1.12 on page 56 ,
and
11.1.27 on page 66 for details).
Different current amplitude can be set for acceleration, deceleration and constant speed phases and when the motor is stopped through TVAL_ACC, TVAL_DEC, TVAL_RUN and
TVAL_HOLD registers (see
Section 11.1.16 on page 58 ). The output current amplitude can
also be regulated by the ADCIN voltage value (see
Each bridge is driven by an independent control system that shares with the other bridge the control parameters only.
9.1 Predictive current control
Unlike classical peak current control systems, that make the phase current decay when the target value is reached, this new method keeps the power bridge ON for an extra time after reaching the current threshold.
At each cycle the system measures the time required to reach the target current (t
SENSE
After that the power stage is kept in a “predictive” ON state (t
PRED mean value of t in
SENSE
).
) for a time equal to the
in the last two control cycles (actual one and previous one), as shown
Figure 19. Predictive current control
Iout predictive ON state
OFF state t
PRED
(n) = t
SENSE
(n-1) + t
SENSE
(n)
2
Iref t
SENSE
(n-1) t
PRED
(n-1) t
OFF t
PRED
(n) t
SENSE
(n) t
OFF
AM15048v1
At the end of the predictive ON state the power stage is set in OFF state for a fixed time, as in a constant t
OFF
current control. During the OFF state both slow and fast decay can be performed; the better decay combination is automatically selected by the powerSTEP01, as described in
DS9836 Rev 7 43/92
92
Phase current control: current mode powerSTEP01
, the system is able to center the triangular wave on the desired reference value, improving dramatically the accuracy of the current control system: in fact the average value of a triangular wave is exactly equal to the middle point of each of its segment and at steady-state the predictive current control tends to equalize the duration of the t
SENSE
and the t
PRED
time.
Furthermore, the t
OFF
value is recalculated each time a new current value is requested
(microstep change) in order to keep the PWM frequency as near as possible to the programmed one (TSW parameter in the CONFIG register).
The device can be forced to work using classic peak current control setting low the
PRED_EN bit in the CONFIG register (default condition). In this case, after the sense phase
(t
SENSE
) the power stage is set in OFF state, as shown in
Figure 20. Non-predictive current control
Iout sense ON state
OFF state
Iref tOFF tOFF
AM15049v1
9.2 Auto-adjusted decay mode
During the current control, the device automatically selects the better decay mode in order to follow the current profile reducing the current ripple.
At reset, the off-time is performed turning on both the low-side MOS of the power stage and the current recirculates in the lower half of the bridge (slow decay).
If, during a PWM cycle, the target current threshold is reached in a time shorter than the
TON_MIN value, a fast decay of TOFF_FAST/8 (T_FAST register) is immediately performed turning on the opposite MOS of both half-bridges and the current recirculates back to the supply bus.
After this time, the bridge returns to ON state: if the time needed to reach the target current value is still less than TON_MIN, a new fast decay is performed with a period twice the previous one. Otherwise, the normal control sequence is followed as described in
. The maximum fast decay duration is set by the TOFF_FAST value.
44/92 DS9836 Rev 7
powerSTEP01 Phase current control: current mode
Figure 21. Adaptive decay - fast decay tuning
1 st fast decay:
Tfast = TOFF_FAST/8
3 rd fast decay:
Tfast = TOFF_FAST/2
Ton > TON_MIN
Tfast = TOFF_FAST/2 reference current
2 nd fast decay (*):
Tfast = TOFF_FAST/4
(*)Note: starting from 2 nd fast decay the system combines fast and slow decay during the OFF phase.
AM15050v1
When two or more fast decays are performed with the present target current, the control system adds a fast decay at the end of every off-time keeping the OFF state duration constant (t
OFF
is split into t
OFF
, SLOW and t
OFF
, FAST). When the current threshold is increased by a microstep change (rising step), the system returns to normal decay mode
(slow decay only) and the t
FAST
value is halved.
Stopping the motor or reaching the current sinewave zero-crossing causes the current control system to return to the reset state.
DS9836 Rev 7 45/92
92
Phase current control: current mode powerSTEP01
Figure 22. Adaptive decay - switch from normal to slow+ fast decay mode and vice versa
1 st fast decay
2 nd fast decay switch to fast + slow decay mode reference current t
OFF t
FAST t
OFF t
OFF,SLOW t
OFF,FAST
Time
Target current is increased (raising step) system returns to slow decay mode and t
FAST
vaule is halved reference current
9.3
Time
AM15051v1
Auto-adjusted fast decay during the falling steps
When the target current is decreased by a microstep change (falling step), the device performs a fast decay in order to reach the new value as fast as possible. However, exceeding the fast duration could cause a strong ripple on the step change. The powerSTEP01 automatically adjusts these fast decays reducing the current ripple.
At reset the fast decay value (t
FALL
) is set to FALL_STEP/4 (T_FAST register). The t
FALL value is doubled every time, within the same falling step, an extra fast decay is necessary to
obtain an on-time greater than TON_MIN (see Section 11.1.18 on page 59 ). The maximum
t
FALL
value is equal to FALL_STEP.
At the next falling step, the system uses the last t
FALL
value of the previous falling step.
Stopping the motor or reaching the current sinewave zero crossing causes the current control system to return to the reset state.
46/92 DS9836 Rev 7
powerSTEP01 Phase current control: current mode
Figure 23. Fast decay tuning during the falling steps
Falling step
1 st fast decay: t
FALL
= FALL_STEP/4
Falling step
1 st fast decay: t
FALL
= FALL_STEP/2 reference current
9.4
2 nd fast decay: t
FALL
= FALL_STEP/2
Time
AM15052v1
Torque regulation (setting the output current)
The phase currents are monitored through two shunt resistors (one for each power bridge) connected to the respective sense pin (see
Figure 24 ). The integrated comparator
compares the sense resistor voltage with the internal reference generated using the peak value, which is proportional to the output current amplitude, and the microstepping code.
The comparison result is provided to the logic in order to implement the current control algorithm as described in previous sections.
The peak reference voltage can be regulated in two ways: writing TVAL_ACC, TVAL_DEC,
TVAL_RUN and TVAL_HOLD registers or varying the ADCIN voltage value.
The EN_TQREG bit (CONFIG register) sets the torque regulation method. If this bit is high,
ADC_OUT prevalue is used to regulate output current amplitude (see
Otherwise the internal analog-to-digital converter is at the user’s disposal and the output current amplitude is managed by TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC
registers (see Table 18 on page 58
).
The voltage applied to the ADCIN pin is sampled at f
S
frequency and converted in an NADC bit digital signal. The analog-to-digital conversion result is available in the ADC_OUT register.
DS9836 Rev 7 47/92
92
Phase current control: current mode
Figure 24. Current sensing and reference voltage generation powerSTEP01
5PHBUF
ESJWFST
1FBLSFGFSFODF%"$
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.JDSPTUFQ
5PDVSSFOU
DPOUSPMMPHJD
.JDSPTUFQQJOH%"$
5PHBUF
ESJWFST
7
SFG
5PHBUF
ESJWFST
0659 -PBE
5PHBUF
ESJWFST
0659
4&/4&9@1
4&/4&9@1
4&/4&9@4
3
TFOTF
48/92 DS9836 Rev 7
powerSTEP01
10 Serial interface
Serial interface
The integrated 8-bit serial peripheral interface (SPI) is used for a synchronous serial communication between the host microprocessor (always master) and the device (always slave).
The SPI uses chip select (CS), serial clock (CK), serial data input (SDI) and serial data output (SDO) pins. When CS is high the device is unselected and the SDO line is inactive
(high impedance).
The communication starts when CS is forced low. The CK line is used for synchronization of data communication.
All commands and data bytes are shifted into the device through the SDI input, most significant bit first. The SDI is sampled on the rising edges of the CK.
All output data bytes are shifted out of the device through the SDO output, most significant bit first. The SDO is latched on the falling edges of the CK. When a return value from the device is not available, an all zero byte is sent.
After each byte transmission the CS input must be raised and be kept high for at least t disCS in order to allow the device to decode the received command and put the return value into the shift register.
All timing requirements are shown in Figure 25 (see
Section 3 on page 12 for values).
Multiple devices can be connected in daisy chain configuration, as shown in Figure 26 .
Figure 25. SPI timings diagram
CS t setCS t rCK t hCK t fCK t lCK
CK
SDI
SDO
HiZ t enSDO t setSDI t holSDI
MSB t holSDO
MSB
N-1
N-1 t vSDO
N-2
N-2 t disCS t holCS
LSB t disSDO
LSB MSB
AM12837v1
DS9836 Rev 7 49/92
92
Serial interface
HOST SPI signals
CS
SDO
M
Byte N Byte N-1
SDI
M
Byte N Byte N-1
Figure 26. Daisy chain configuration
CS
CK
HOST
SDO
M
SDI
M
Byte 1
Byte 1
Byte N
Byte N powerSTEP01
CS
CK
SDI
SDO
DEV 1
CS
CK
SDI
SDO
DEV 2
DEV N
CS
CK
SDI
SDO
AM12838v1
50/92 DS9836 Rev 7
powerSTEP01
11 Programming manual
Programming manual
11.1 Register and flag description
Following a map of the user available registers (detailed description in respective paragraphs):
Address
[Hex] h16 h17 h18
Register name
STEP_MODE
ALARM_EN
GATECFG1
Register function
Table 12. Register map
Length
[bit]
Reset
[Hex]
General configuration h05 h06 h07 h08 h12 h13 h15 h01 h02 h03 h04
ABS_POS
EL_POS
MARK
SPEED
Current position
Electrical position
Mark position
Current speed
ACC
DEC
Acceleration
Deceleration
MAX_SPEED Maximum speed
MIN_SPEED Minimum speed
ADC_OUT ADC output
OCD_TH
FS_SPD
OCD threshold
Full-step speed
Step mode
Alarm enables
Gate driver configuration
12
12
10
12
5
5
11
22
9
22
20
8
8
11
Reset value
Remarks
(1)
000000
000
0 step
0
R, WS
R, WH
000000 0 step R, WR
00000 0 step/tick (0 step/s) R
08A 125.5e-12 step/tick
2
(2008 step/s
2
) R, WS
08A 125.5e-12 step/tick
2
(2008 step/s
2
) R, WS
041
000
XX( 2 )
8
027
7
FF
0
248e-6 step/tick (991.8 step/s)
0 step/tick (0 step/s)
0
281.25 mV
150.7e-6 step/tick (602.7 step/s)
BUSY/SYNC output used as BUSY,
128 microsteps, voltage mode
All alarms enabled
I gate
= 4 mA, t
CC
= 125 ns, boost disabled, Clock watchdog disabled
R, WR
R, WS
R
R, WR
R, WR
R, WH
R, WS
R, WH h19 GATECFG2
Gate driver configuration
8 0 R, WH h1B h1A
STATUS
CONFIG
Status
IC configuration
16
16
XXXX
(2)
2C88 t
BLANK
= 125 ns, t
DT
= 125 ns
High impedance state, motor stopped, reverse direction, all fault flags released UVLO/reset flag set
Internal 16 MHz oscillator
(OSCOUT at 2 MHz), SW event causes HardStop, overcurrent shutdown, V
CC
= 7.5 V, UVLO threshold low
R
R, WH
DS9836 Rev 7 51/92
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Programming manual powerSTEP01
Address
[Hex]
Register name
Table 12. Register map (continued)
Register function
Length
[bit]
Reset
[Hex]
Reset value
Remarks
(1)
Voltage mode configuration h09 h0A h0B h0C h0D h0E h0F h10 h11
KVAL_HOLD
KVAL_RUN
KVAL_ACC
KVAL_DEC
Holding K
VAL
Constant speed
K
VAL
Acceleration starting K
VAL
Deceleration starting K
VAL
INT_SPEED Intersect speed
ST_SLP Start slope
FN_SLP_ACC
Acceleration final slope
FN_SLP_DEC
Deceleration final slope
K_THERM
Thermal compensation factor
STALL_TH STALL threshold
8
8
8
8
14
8
8
8
4
29
29
29
29
0408
19
29
29
0
0.16 ∙ V
0.16 ∙ V
0.16 ∙ V
0.16 ∙ V
1.0
S
S
S
S
15.4e-6 step/tick (61.5 step/s)
250.038% s/step
0.063% s/step
0.063% s/step
R, WR
R, WR
R, WR
R, WR
R, WH
R, WH
R, WH
R, WH
R, WR h14 h1A CONFIG IC configuration
5
16
10
2C88
531.25 mV
Motor supply voltage compensation disabled, f
PWM
= f
OSC
/ 1024
R, WR
R, WH
Current mode configuration h09 TVAL_HOLD
Holding reference voltage
8 29 328 mV
R, WR h0A h0B h0C h0E
TVAL_RUN
Constant speed reference voltage
TVAL_ACC
TVAL_DEC
T_FAST
Acceleration reference voltage
Deceleration reference voltage
Fast decay setting
TON_MIN Minimum on-time
8
8
8
8
29
29
29
19
328 mV
328 mV
328 mV
1 μs / 5 μs
R, WR
R, WR
R, WR
R, WH h0F 8 29 20.5 μs R, WH h10 TOFF_MIN Minimum off-time 8 29 20.5 μs R, WH h1A CONFIG IC configuration 16 2C88
Predictive current control disabled, t
SW
= 44 s
R, WH
1. R: readable, WH: writable when the outputs are in high impedance only, WS: writable when the motor is stopped only,
WR: always writable.
2. According to startup conditions.
52/92 DS9836 Rev 7
powerSTEP01 Programming manual
11.1.1 ABS_POS
The ABS_POS register contains the current motor absolute position in agreement with the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.). The value is in 2 's complement format and it ranges from -2
21
to +2
21
-1.
At power-on the register is initialized to “0” (HOME position).
Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
11.1.2 EL_POS
The EL_POS register contains the current electrical position of the motor. The two MSbits indicate the current step and the other bits indicate the current microstep (expressed in step/128) within the step.
Bit 8
STEP
Bit 7 Bit 6
Table 13. EL_POS register
Bit 5 Bit 4 Bit 3
MICROSTEP
Bit 2 Bit 1 Bit 0
When the EL_POS register is written by the user the new electrical position is instantly imposed. When the EL_POS register is written, its value must be masked in order to match with the step mode selected in the STEP_MODE register in order to avoid a wrong microstep value generation (
Section 11.1.23 on page 61 ); otherwise the resulting microstep
sequence is incorrect. When the device operates in current mode, the bit number 0, 1 and 2 of the EL_POS register are meaningless because the maximum microstepping resolution is
1/16 th
of step.
Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
).
11.1.3 MARK
The MARK register contains an absolute position called MARK, according to the selected step mode; the stored value unit is equal to the selected step mode (full, half, quarter, etc.).
It is in 2's complement format and it ranges from -2 21 to +2 21 -1.
11.1.4 SPEED
The SPEED register contains the current motor speed, expressed in step/tick (format unsigned fixed point 0.28).
In order to convert the SPEED value in step/s the following formula can be used:
Note:
Equation 4
step/s =
SPEED 2 tick
– 28
------------------------------------where SPEED is the integer number stored in the register and tick is 250 ns.
The available range is from 0 to 15625 step/s with a resolution of 0.015 step/s.
The range effectively available to the user is limited by the MAX_SPEED parameter.
DS9836 Rev 7 53/92
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Programming manual powerSTEP01
Any attempt to write the register causes the command to be ignored and the CMD_ERROR
flag to rise ( Section 11.1.28 on page 71 ).
11.1.5 ACC
The ACC register contains the speed profile acceleration expressed in step/tick
2
(format unsigned fixed point 0.40).
In order to convert the ACC value in step/s
2
the following formula can be used:
Equation 5
step/s
2
=
– 40
----------------------------tick
2 where ACC is the integer number stored in the register and tick is 250 ns.
The available range is from 14.55 to 59590 step/s 2 with a resolution of 14.55 step/s 2 .
The 0xFFF value of the register is reserved and it should never be used.
Any attempt to write to the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
).
11.1.6 DEC
The DEC register contains the speed profile deceleration expressed in step/tick 2 (format unsigned fixed point 0.40).
In order to convert the DEC value in step/s 2 the following formula can be used:
Equation 6
step/s
2
=
DEC 2
– 40
----------------------------tick
2 where DEC is the integer number stored in the register and tick is 250 ns.
The available range is from 14.55to 59590 step/s2 with a resolution of 14.55 step/s2.
Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
).
11.1.7 MAX_SPEED
The MAX_SPEED register contains the speed profile maximum speed expressed in step/tick (format unsigned fixed point 0.18).
In order to convert it in step/s, the following formula can be used:
Equation 7
step/s =
MAX_SPEED 2 tick
– 18
----------------------------------------------------where MAX_SPEE D is the integer number stored in the register and tick is 250 ns.
The available range is from 15.25 to 15610 step/s with a resolution of 15.25 step/s.
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11.1.8 MIN_SPEED
The MIN_SPEED register contains the following parameters:
Bit 12
LSPD_OPT
Table 14. MIN_SPEED register
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MIN_SPEED
The MIN_SPEED parameter contains the speed profile minimum speed. Its value is expressed in step/tick and to convert it in step/s the following formula can be used:
Equation 8
– 24
step/s = tick where MIN_SPEED is the integer number stored in the register and tick is the ramp 250 ns.
The available range is from 0 to 976.3 step/s with a resolution of 0.238 step/s.
When the LSPD_OPT bit is set high, low speed optimization feature is enabled (voltage mode driving only) and the MIN_SPEED value indicates the speed threshold below which the compensation works. In this case the minimum speed of the speed profile is set to zero.
Any attempt to write the register when the motor is running causes the CMD_ERROR flag to rise.
11.1.9 FS_SPD
The FS_SPD register contains the following parameters:
Bit 10
BOOST_MODE
Table 15. FS_SPD register
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
FS_SPD
Bit 3 Bit 2 Bit 1 Bit 0
The FS_SPD threshold speed value over which the step mode is automatically switched to full-step two-phase on. Its value is expressed in step/tick (format unsigned fixed point 0.18) and to convert it in step/s the following formula can be used:
Equation 9
step/s =
tick
2
– 18
-----------------------------------------------------------
If FS_SPD value is set to h3FF (max.) the system always works in Microstepping mode
(SPEED must go over the threshold to switch to Full-step mode). Setting FS_SPD to zero does not have the same effect as setting the step mode to full-step two-phase on: the zero
FS_SPD value is equivalent to a speed threshold of about 7.63 step/s.
The available range is from 7.63 to 15625 step/s with a resolution of 15.25 step/s.
The BOOST_MODE bit sets the amplitude of the voltage squarewave during the full-step operation (see
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Programming manual powerSTEP01
11.1.10 KVAL_HOLD, KVAL_RUN, KVAL_ACC and KVAL_DEC
These registers are specific for voltage mode driving (see
The KVAL_HOLD register contains the K
VAL value that is assigned to the PWM modulators when the motor is stopped (compensations excluded).
The KVAL_RUN register contains the K
VAL
value that is assigned to the PWM modulators when the motor is running at constant speed (compensations excluded).
The KVAL_ACC register contains the starting K
VAL
value that can be assigned to the PWM modulators during acceleration (compensations excluded).
The KVAL_DEC register contains the starting K
VAL
value that can be assigned to the PWM modulators during deceleration (compensations excluded).
The available range is from 0 to 0.996 x V
S
with a resolution of 0.004 x V
S
, as shown in
0
0
0
0
0
0
Table 16. Voltage amplitude regulation registers
KVAL_X [7…0] Output voltage
0
0
0
0
0
0
0
0
0
1
0
V
S
x (1/256)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
V
S
x (254/256)
V
S
x (255/256)
11.1.11 INT_SPEED
This register is specific for voltage mode driving (see Section 8 ).
The INT_SPEED register contains the speed value at which the BEMF compensation curve
changes slope ( Section 8.4 on page 40
for details). Its value is expressed in step/tick and to convert it in [step/s] the following formula can be used:
Equation 10
step/s = tick
– 18
-------------------------------------------------where INT_SPEED is the integer number stored in the register and tick is 250 ns.
The available range is from 0 to 976.5 step/s with a resolution of 0.0596 step/s.
Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
11.1.12 ST_SLP
This register is specific for voltage mode driving (see Section 8 ).
The ST_SLP register contains the BEMF compensation curve slope that is used when the speed is lower than the intersect speed (
). Its value is expressed in s/step and
the available range is from 0 to 0.004 with a resolution of 0.000015.
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powerSTEP01 Programming manual
When ST_SLP, FN_SLP_ACC and FN_SLP_DEC parameters are set to zero, no BEMF compensation is performed.
Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
11.1.13 FN_SLP_ACC
This register is specific for voltage mode driving (see Section 8 on page 38 ).
The FN_SLP_ACC register contains the BEMF compensation curve slope that is used when the speed is greater than the intersect speed during acceleration (
for details). Its value is expressed in s/step and the available range is from 0 to 0.004 with a resolution of 0.000015.
When ST_SLP, FN_SLP_ACC and FN_SLP_DEC parameters are set to zero, no BEMF compensation is performed.
Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
).
11.1.14 FN_SLP_DEC
This register is specific for voltage mode driving (see Section 8 ).
The FN_SLP_DEC register contains the BEMF compensation curve slope that is used when
the speed is greater than the intersect speed during deceleration ( Section 8.4
for details). Its value is expressed in s/step and the available range is from 0 to 0.004 with a resolution of
0.000015.
When ST_SLP, FN_SLP_ACC and FN_SLP_DEC parameters are set to zero, no BEMF compensation is performed.
Any attempt to write the register when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
).
11.1.15 K_THERM
This register is specific for voltage mode driving (see Section 8 ).
The K_THERM register contains the value used by the winding resistance thermal drift compensation system (
The available range is from 1 to 1.46875 with a resolution of 0.03125, as shown in
0
0
Table 17. Winding resistance thermal drift compensation coefficient
K_THERM [3 … 0] Compensation coefficient
0
0
0
0
0
1
1
1.03125
1
1
1
1
1
1
0
1
1.4375
1.46875
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Programming manual powerSTEP01
11.1.16 TVAL_HOLD, TVAL_RUN, TVAL_ACC and TVAL_DEC
These registers are specific for current mode driving (see Section 9 on page 43 ).
The TVAL_HOLD register contains the reference voltage that is assigned to the torque regulation DAC when the motor is stopped.
The TVAL_RUN register contains the reference voltage that is assigned to the torque regulation DAC when the motor is running at constant speed.
The TVAL_ACC register contains the reference voltage that is assigned to the torque regulation DAC during acceleration.
The TVAL_DEC register contains the reference voltage that is assigned to the torque regulation DAC during deceleration.
The available range is from 7.8 mV to 1 V with a resolution of 7.8 mV, as shown in
Table 18. Torque regulation by TVAL_HOLD, TVAL_ACC, TVAL_DEC and TVAL_RUN registers
TVAL_X [6…0] Peak reference voltage
0
0
0
0
0
0
0
0
0
0
0
0
0
1
7.8 mV
15.6 mV
1
1
1
1
1
1
1
1
1
1
1
1
0
1
992.2 mV
1 V
11.1.17 T_FAST
This register is specific for current mode driving (see Section 9
).
The T_FAST register contains the maximum fast decay time (TOFF_FAST) and the
maximum fall step time (FALL_STEP) used by the current control system ( Section 9.2 on page 44
and Section 9.3 on page 46 for details):
Bit 7 Bit 6
TOFF_FAST
Bit 5
Table 19. T_FAST register
Bit 4 Bit 3 Bit 2
FAST_STEP
Bit 1 Bit 0
The available range for both parameters is from 2 μs to 32 μs.
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Table 20. Maximum fast decay times
TOFF_FAST [3 … 0] FAST_STEP [3 … 0] Fast decay time
0
0
0
0
0
0
0
1
2 μs
4 μs
1
1
1
1
1
1
0
1
28 μs
32 μs
Any attempt to write to the register when the motor is running causes the command to be
ignored and CMD_ERROR to rise ( Section 11.1.28 on page 71 ).
11.1.18 TON_MIN
This register is specific for current mode driving (see Section 9 on page 43 ).
This parameter is used by the current control system when current mode operation is selected.
The TON_MIN register contains the minimum on-time value used by the current control system (see
The available range for both parameters is from 0.5 μs to 64 μs.
0
0
0
0
0
0
Table 21. Minimum on-time
TON MIN [6 … 0]
0
0
0
0
0
0
0
1
Time
0.5 μs
1 μs
1
1
1
1
1
1
1
1
1
1
1
1
0
1
63.5 μs
64 μs
Any attempt to write to the register when the motor is running causes the command to be ignored and the CMD_ERROR to rise (see
).
11.1.19 TOFF_MIN
This register is specific for current mode driving (see Section 9
).
This parameter is used by the current control system when current mode operation is selected.
The TOFF_MIN register contains the minimum off-time value used by the current control system (see
Section 9.1 on page 43 for details).
The available range for both parameters is from 0.5 μs to 64 μs.
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Programming manual powerSTEP01
0
0
0
0
0
0
Table 22. Minimum off-time
TOFF MIN [6 … 0]
0
0
0
0
0
0
0
1
Time
0.5 μs
1 μs
1
1
1
1
1
1
1
1
1
1
1
1
0
1
63.5 μs
64 μs
Any attempt to write to the register when the motor is running causes the command to be ignored and CMD_ERROR to rise (see
11.1.20 ADC_OUT
The ADC_OUT register contains the result of the analog to digital conversion of the ADCIN pin voltage.
Any attempt to write to the register causes the command to be ignored and the CMD_ER-
ROR to rise.
Table 23. ADC_OUT value and motor supply voltage compensation feature
V
S
V
ADCIN
/ V
REG
ADC_OUT [4 … 0]
Compensation coefficient
Greater than V
S
, nom
+ 50%
V
S
, nom
+ 50%
> 24/32
24/32
1
1
1
1
X
0
X
0
X
0
0.65625
0.65625
V
S
, nom
16/32 1 0 0 0 0 1
V
S
, nom
– 50%
Lesser than V
S
, nom
– 50%
8/32
< 8/32
0
0
1
0
0
X
0
X
0
X
1.968875
1.968875
Table 24. ADC_OUT value and torque regulation feature
V
ADCIN
/ V
REG
ADC_OUT [4 … 0] Reference voltage
0
1/32
0
0
0
0
0
0
0
0
0
1
31.25 mV
62.5 mV
30/32
31/32
1
1
1
1
1
1
1
1
0
1
968.8 mV
1000 mV
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11.1.21 OCD_TH
The OCD_TH register contains the overcurrent threshold value (
details). The available range is from 31.25 mV to 1 V, steps of 31.25 mV, as shown in
.
0
0
…
1
1
Table 25. Overcurrent detection threshold
OCD_TH [4 … 0] Overcurrent detection threshold
0
0
…
1
1
0
0
…
1
1
0
0
…
1
1
0
1
…
0
1
31.25 mV
62.5 mV
…
968.75 mV
1 V
11.1.22 STALL_TH
This register is specific for voltage mode driving (see Section 8 on page 38 ).
The STALL_TH register contains the stall detection threshold value. The available range is from 31.25 mV to 1 V with a resolution of 31.25 mV.
0
0
…
1
1
STALL_th [4 … 0]
Table 26. Stall detection threshold
Stall detection threshold
0
0
…
1
1
0
0
…
1
1
0
0
…
1
1
0
1
…
0
1
31.25 mV
62.5 mV
…
968.75 mV
1 V
11.1.23 STEP_MODE
The STEP_MODE register has the following structure:
Bit 7
SYNC_EN
Bit 6
Table 27. STEP_MODE register
Bit 5
SYNC_SEL
Bit 4 Bit 3
CM_VM
Bit 2 Bit 1
STEP_SEL
Bit 0
The CM_VM bit sets the current control method between voltage and current mode:
CM_VM
0
1
Table 28. Control mode selection
Control mode
Voltage mode
Advanced current control (current mode)
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Programming manual powerSTEP01
STEP_SEL selects one of eight possible stepping modes:
1
1
1
1
0
0
0
0
STEP_SEL[2 … 0]
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Table 29. Step mode selection
Step mode (CM_VM = 0) Step mode (CM_VM = 1)
Full-step
Half-step
1/4 microstep
1/8 microstep
1/16 microstep
1/32 microstep
1/64 microstep
1/128 microstep
Full-step
Half-step
1/4 microstep
1/8 microstep
1/16 microstep
1/16 microstep
1/16 microstep
1/16 microstep
Every time the step mode changes, the electrical position (i.e.: the point of microstepping sinewave that is generated) resets at the first microstep.
It is important to note that every time STEP_SEL changes, the value in ABS_POS register loses meaning and then it should be reset.
When sync clock is disabled, BUSY/SYNC output is used as BUSY (command state machine busy signaling), otherwise BUSY/SYNC output provides a clock signal according to SYNC_SEL parameter.
Table 30. Sync clock enable
SYNC_EN
0
1
Sync clock
Disabled
Enabled
SYNC_SEL[2 … 0]
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 31. Sync clock selection
Step information (CM_VM = 0)
Full-step
Half-step
1/4 microstep
1/8 microstep
1/16 microstep
1/32 microstep
1/64 microstep
1/128 microstep
Step information (CM_VM = 1)
Full-step
Half-step
1/4 microstep
1/8 microstep
1/16 microstep
Always low
Always low
Always low
Any attempt to write to the register, when the motor is running, causes the command to be ignored and the CMD_ERROR to rise (see
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powerSTEP01 Programming manual
11.1.24 ALARM_EN
The ALARM_EN register allows the selection of which alarm signals are used to generate the FLAG output. If the respective bit of the ALARM_EN register is set high, the alarm condition forces the FLAG pin output down.
ALARM_EN bit
0 (LSB)
1
2
5
6
3
4
7 (MSB)
Table 32. ALARM_EN register
Alarm condition
Overcurrent
Thermal shutdown
Thermal warning
UVLO
ADC UVLO
Stall detection (voltage mode only)
Switch turn-on event
Command error
11.1.25 GATECFG1
The GATECFG1 register has the following structure:
Bit 15
Bit 7
Bit 14
Bit 6
IGATE
Table 33. GATECFG1 register
Bit 13 Bit 12 Bit 11
Bit 5 Bit 4
WD_EN
Bit 3
Bit 10
Bit 2
TCC
Bit 9
TBOOST
Bit 1
Bit 8
Bit 0
The IGATE parameter selects the sink/source current used by gate driving circuitry to charge/discharge the respective gate during commutations. Seven possible values ranging from 4 mA to 96 mA are available, as shown in
1
1
0
1
1
0
0
0
Table 34. IGATE parameter
IGATE [2 … 0}
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
Gate current [mA}
16
24
32
64
96
4
4
8
DS9836 Rev 7 63/92
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Programming manual powerSTEP01
The TCC parameter defines the duration of constant current phase during gate turn-on and turn-off sequences (
1
1
1
0
0
1
1
1
1
0
0
1
Table 35. TCC parameter
TCC [4 … 0]
1
1
1
0
0
1
0
1
1
0
0
0
1
0
1
0
1
0
Constant current time [ns]
125
250
3625
3750
3750
3750
The TBOOST parameter defines the duration of the overboost phase during gate turn-off
TBOOST
[2 … 0]
Table 36. TBOOST parameter
Turn-off boost time
[ns]
1
1
0
1
1
0
0
0
0
0
1
1
0
0
1
1
1. Clock frequency equal to 16 MHz or 32 MHz.
2. Clock frequency equal to 24 MHz.
3. Clock frequency equal to 8 MHz.
1
0
1
0
1
0
1
0
0
62.5
(1)
/ 83.3
(2)
/ 125
(3)
125
250
375
500
750
1000
The WD_EN bit enables the clock source monitoring (
11.1.26 GATECFG2
The GATECFG2 register has the following structure:
Bit 7 Bit 6
TBLANK
Table 37. GATECFG2 register
Bit 5 Bit 4 Bit 3 Bit 2
TDT
Bit 1 Bit 0
64/92 DS9836 Rev 7
powerSTEP01 Programming manual
The TDT parameter defines the deadtime duration between the gate turn-off and the opposite gate turn-on sequences (
).
0
0
1
1
0
0
1
1
Table 38. TDT parameter
TDT [4 … 0]
0
0
1
1
0
0
1
1
0
1
0
1
Deadtime [ns]
125
250
3875
4000
The TBLANK parameter defines the duration of the blanking of the current sensing
comparators (stall detection and overcurrent) after each commutation ( Section 7.17
0
1
1
0
Table 39. TBLANK parameter
TBLANK [2 … 0]
0
1
1
0
0
0
1
1
Blanking time [ns]
125
250
875
1000
DS9836 Rev 7 65/92
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0
0
0
1
1
1
0
1
0
0
Programming manual powerSTEP01
11.1.27 CONFIG
The CONFIG register has the following structure:
CM_VM
0
1
0
1
Bit 15
PRED_EN
Bit 7
OC_SD
OC_SD
Bit 14
F_PWM_INT
Bit 6
Table 40. CONFIG register
Bit 13
Bit 5
Bit 12
TSW
Bit 4
Bit 11
F_PWM_DEC
Bit 3
EN_VSCOMP SW_MODE EXT_CLK
EN_TQREG SW_MODE EXT_CLK
Bit 10
Bit 2
Bit 9 Bit 8
VCCVAL UVLOVAL
VCCVAL UVLOVAL
Bit 1 Bit 0
OSC_SEL
OSC_SEL
The OSC_SEL and EXT_CLK bits set the system clock source:
EXT_CLK OSC_SEL [2 … 0]
Table 41. Oscillator management
Clock source OSCIN
0 0 0 0
OSCOUT
0
0
1
0
0 1
1
1
0
0
0
0
0
1
0
1
0
0
1 1
1
0
Internal oscillator: 16 MHz Unused Unused
1
0
1
Internal oscillator: 16 MHz
Internal oscillator: 16 MHz
Unused
Unused
Supplies a 2 MHz clock
Supplies a 4 MHz clock
Supplies 8 MHz clock 0 Internal oscillator: 16 MHz Unused
1
0
1
0
Internal oscillator: 16 MHz Unused
External crystal or resonator:
8 MHz
External crystal or resonator:
16 MHz
External crystal or resonator:
24 MHz
Crystal/resonator driving
Crystal/resonator driving
Crystal/resonator driving
Supplies a 16 MHz clock
Crystal/resonator driving
Crystal/resonator driving
Crystal/resonator driving
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powerSTEP01
EXT_CLK
0
1
1
1
1
Table 41. Oscillator management (continued)
OSC_SEL [2 … 0] Clock source OSCIN
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
External crystal or resonator:
32 MHz
Ext clock source: 8 MHz
(crystal/resonator driver disabled)
External clock source: 16
MHz (crystal/resonator driver disabled)
External clock source: 24
MHz (crystal/resonator driver disabled)
External clock source: 32
MHz (crystal/resonator driver disabled)
Crystal/resonator driving
Clock source
Clock source
Clock source
Clock source
Programming manual
OSCOUT
Crystal/resonator driving
Supplies inverted
OSCIN signal
Supplies inverted
OSCIN signal
Supplies inverted
OSCIN signal
Supplies inverted
OSCIN signal
The SW_MODE bit sets the external switch to act as HardStop interrupt or not:
Table 42. External switch hard stop interrupt mode
SW_MODE Switch mode
0
1
HardStop interrupt
User disposal
The OC_SD bit sets if an overcurrent event causes or not the bridges to turn-off; the OCD flag in status register is forced low anyway:
OC_SD
1
0
Table 43. Overcurrent event
Overcurrent event
Bridges shut down
Bridges do not shut down
The VCCVAL bit set the internal V
CC
regulator output voltage:
Table 44. Programmable V
CC
voltage regulator output
VCCVAL V
CC voltage
0
1
7.5 V
15 V
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Programming manual
The UVLOVAL bit sets the UVLO protection thresholds:
UVLOVAL
0
1
Table 45. Programmable UVLO thresholds
V ccthOn
V ccthOff
DV
BOOTThOn
6.9 V
10.4 V
6.3 V
10 V
6 V
9.2 V powerSTEP01
DV
BOOTThOff
5.5 V
8.8 V
When the device operates in voltage mode, the EN_VSCOMP bit sets if the motor supply voltage compensation is enabled or not.
Table 46. Motor supply voltage compensation enable
EN_VSCOMP Motor supply voltage compensation
0
1
Disabled
Enabled
1
1
0
1
1
0
0
0
When the device operates in voltage mode, the F_PWM_INT bits set the integer division factor of PWM frequency generation:
Table 47. PWM frequency: integer division factor
F_PWM_INT
[2 … 0]
Integer division factor
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
4
5
6
1
2
3
7
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1
1
1
1
0
0
0
0
When the device operates in voltage mode, the F_PWM_DEC bits set the multiplication factor of PWM frequency generation:
Table 48. PWM frequency: multiplication factor
F_PWM_DEC [2 … 0] Multiplication factor
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0.625
0.75
0.875
1
1.25
1.5
1.75
2
In the following tables all available PWM frequencies are listed according to oscillator frequency, F_PWM_INT and F_PWM_DEC values (CONFIG register OSC_SEL parameter has to be correctly programmed).
Table 49. Available PWM frequencies [kHz]: 8 MHz oscillator frequency
F_PWM_DEC
F_PWM_INT
000
001
010
011
100
101
110
000
2.4
2.0
1.6
1.4
9.8
4.9
3.3
001
11.7
5.9
3.9
2.9
2.3
2.0
1.7
010
13.7
6.8
4.6
3.4
2.7
2.3
2.0
011
15.6
7.8
5.2
3.9
3.1
2.6
2.2
100
19.5
9.8
6.5
4.9
3.9
3.3
2.8
101
23.4
11.7
7.8
5.9
4.7
3.9
3.3
110
27.3
13.7
9.1
6.8
5.5
4.6
3.9
111
31.3
15.6
10.4
7.8
6.3
5.2
4.5
Table 50. Available PWM frequencies [kHz]: 16 MHz oscillator frequency
F_PWM_DEC
F_PWM_INT
000
001
010
011
100
000
19.5
9.8
6.5
4.9
3.9
001
23.4
11.7
7.8
5.9
4.7
010
27.3
13.7
9.1
6.8
5.5
011
31.3
15.6
10.4
7.8
6.3
100
39.1
19.5
13.0
9.8
7.8
101
46.9
23.4
15.6
11.7
9.4
110
54.7
27.3
18.2
13.7
10.9
111
62.5
31.3
20.8
15.6
12.5
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Programming manual powerSTEP01
Table 50. Available PWM frequencies [kHz]: 16 MHz oscillator frequency (continued)
F_PWM_DEC
F_PWM_INT
101
110
000
3.3
2.8
001
3.9
3.3
010
4.6
3.9
011
5.2
4.5
100
6.5
5.6
101
7.8
6.7
110
9.1
7.8
111
10.4
8.9
Table 51. Available PWM frequencies [kHz]: 24 MHz oscillator frequency
F_PWM_DEC
F_PWM_INT
000
001
010
011
100
101
110
000
29.3
14.6
9.8
7.3
5.9
4.9
4.2
001
35.2
17.6
11.7
8.8
7.0
5.9
5.0
010
41.0
20.5
13.7
10.3
8.2
6.8
5.9
011
46.9
23.4
15.6
11.7
9.4
7.8
6.7
100
58.6
29.3
19.5
14.6
11.7
9.8
8.4
101
70.3
35.2
23.4
17.6
14.1
11.7
10.0
110
82.0
41.0
27.3
20.5
16.4
13.7
11.7
111
93.8
46.9
31.3
23.4
18.8
15.6
13.4
Table 52. Available PWM frequencies [kHz]: 32 MHz oscillator frequency
F_PWM_DEC
F_PWM_INT
000
001
010
011
100
101
110
000
39.1
19.5
13.0
9.8
7.8
6.5
5.6
001
46.9
23.4
15.6
11.7
9.4
7.8
6.7
010
54.7
27.3
18.2
13.7
10.9
9.1
7.8
011
62.5
31.3
20.8
15.6
12.5
10.4
8.9
100
78.1
39.1
26.0
19.5
15.6
13.0
11.2
101
93.8
46.9
31.3
23.4
18.8
15.6
13.4
110
109.4
54.7
36.5
27.3
21.9
18.2
15.6
111
125.0
62.5
41.7
31.3
25.0
20.8
17.9
When the device operates in current mode, the EN_TQREG bit sets if the peak current is adjusted through the ADCIN input or not.
EN_TQREG
Table 53. External torque regulation enable
Peak current adjust. through ADCIN
0
1
Disabled
Enabled
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powerSTEP01 Programming manual
When the device operates in current mode, the PRED_EN bit sets if the predictive current control method is enabled or not.
Table 54. Motor supply voltage compensation enable
PRED_EN Predictive current control
0
1
Disabled
Enabled
When the device operates in current mode, the TSW bits set the target switching period of the current control algorithm:
0
0
0
0
0
0
TSW [4 … 0]
0
0
0
Table 55. Switching period
0
0
1
0
1
0
Switching period
4 μs (250 kHz)
4 μs (250 kHz)
8 μs (125 kHz)
1 1 1 1 1 124 μs (8 kHz)
Any attempt to write the CONFIG register when the outputs are enabled causes the
command to be ignored and the CMD_ERROR flag to rise (see Section 11.1.28
11.1.28 STATUS
The STATUS register has the following structure:
Bit 15 Bit 14 Bit 13
STALL_A STALL_B
Bit 7
CMD_ERR
OR
Bit 6
OCD
Bit 5
MOT_STATUS
Table 56. STATUS register
Bit 12 Bit 11 Bit 10
TH_STATUS
Bit 4 Bit 3
DIR SW_EVN SW_F
Bit 9
UVLO_ADC UVLO STCK_MOD
Bit 2 Bit 1 Bit 0
BUSY
Bit 15
HiZ
When HiZ flag is high it indicates that the bridges are in high impedance state. Whichever motion command makes the device to exit from High Z state (HardStop and SoftStop included), unless error flags forcing a High Z state are active.
The UVLO flag is active low and is set by an undervoltage lock out or reset events (powerup included).
The UVLO_ADC flag is active low and indicates an ADC undervoltage event.
The OCD flag is active low and indicates an overcurrent detection event.
The STALL_A and STALL_B flags are forced low when a stall condition is detected on bridge A or bridge B respectively. The stall detection is operative only when the voltage mode control is selected.
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Programming manual powerSTEP01
The CMD_ERROR flag is active high and indicates that the command received by SPI can't be performed or does not exist at all.
The SW_F report the SW input status (low for open and high for closed).
The SW_EVN flag is active high and indicates a switch turn-on event (SW input falling edge).
TH_STATUS bits indicate the current device thermal status (see
1
1
0
0
TH_STATUS
Table 57. STATUS register TH_STATUS bits
Status
0
1
0
1
Normal
Warning
Bridge shutdown
Device shutdown
UVLO, UVLO_ADC, OCD, STEP_LOSS_A, STEP_LOSS_B, CMD_ERROR, SW_EVN and
TH_STATUS bits are latched: when the respective conditions make them active (low or high) they remain in that state until a GetStatus command is sent to the IC.
The BUSY bit reflects the BUSY pin status. The BUSY flag is low when a constant speed, positioning or motion command is under execution and is released (high) after the command have been completed.
The STCK_MOD bit is an active high flag indicating that the device is working in step clock mode. In this case the step clock signal should be provided through STCK input pin.
The DIR bit indicates the current motor direction:
DIR
1
0
Table 58. STATUS register DIR bit
Motor direction
Forward
Reverse
MOT_STATUS indicates the current motor status:
1
1
0
0
Table 59. STATUS register MOT_STATUS bits
MOT_STATUS Motor status
0
1
0
1
Stopped
Acceleration
Deceleration
Constant speed
Any attempt to write to the register causes the command to be ignored and the
CMD_ERROR flag to rise.
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powerSTEP01 Programming manual
11.2 Application commands
The command summary is given in
Command mnemonic
Table 60. Application commands
Command binary code Action
[7…5] [4] [3] [2…1] [0]
NOP 000 0
SetParam(PARAM,VALUE) 000
GetParam(PARAM)
Run(DIR,SPD)
001
010 1
0
0
00
[PARAM]
[PARAM]
00
StepClock(DIR)
Move(DIR,N_STEP)
GoTo(ABS_POS)
GoTo_DIR(DIR,ABS_POS)
GoUntil(ACT,DIR,SPD)
ReleseSW(ACT, DIR)
GoHome
GoMark
ResetPos
ResetDevice
SoftStop
HardStop
SoftHiZ
HardHiZ
GetStatus
RESERVED
RESERVED
010
010
011
011
100
100
011
011
110
110
101
101
101
101
110
111
111
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
1
0
0
1
ACT
ACT
0
1
1
0
0
1
0
1
0
1
1
00
00
00
00
01
01
00
00
00
00
00
00
00
00
00
01
00
0 Nothing
Writes VALUE in PARAM register
Returns the stored value in PARAM register
DIR Sets the target speed and the motor direction
DIR
DIR
Puts the device in step-clock mode and imposes
DIR direction
Makes N_STEP (micro)steps in DIR direction
(Not performable when motor is running)
0
DIR
DIR
DIR
Brings motor in ABS_POS position (minimum path)
Brings motor in ABS_POS position forcing DIR direction
Performs a motion in DIR direction with speed
SPD until SW is closed, the ACT action is executed then a SoftStop takes place
Performs a motion in DIR direction at minimum speed until the SW is released (open), the ACT action is executed then a HardStop takes place
0 Brings the motor in HOME position
0 Brings the motor in MARK position
0
Resets the ABS_POS register (sets HOME position)
0 Device is reset to power-up conditions
0 Stops motor with a deceleration phase
0 Stops motor immediately
0
Puts the bridges in high impedance status after a deceleration phase
0
Puts the bridges in high impedance status immediately
0 Returns the status register value
1 RESERVED COMMAND
0 RESERVED COMMAND
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Programming manual powerSTEP01
11.2.1 Command management
The host microcontroller can control motor motion and configure the powerSTEP01 through a complete set of commands.
All commands are composed by a single byte. After the command byte, some bytes of arguments should be needed (see
Figure 27 ). Argument length can vary from 1 to 3 bytes.
6',
IURPKRVW
Figure 27. Command with 3-byte argument
&RPPDQGE\WH
$UJXPHQWE\WH
06%
$UJXPHQWE\WH
$UJXPHQWE\WH
/6%
6'2
WRKRVW
[ [ [ [
$0Y
By default, the device returns an all zero response for any received byte, the only exceptions are GetParam and GetStatus commands. When one of these commands is
received, the following response bytes represent the related register value (see Figure 28 ).
Response length can vary from 1 to 3 bytes.
Figure 28. Command with 3-byte response
6',
IURPKRVW
6'2
WRKRVW
&RPPDQGE\WH
[
123
5HVSRQVHE\WH
06%
123
5HVSRQVHE\WH
123
5HVSRQVHE\WH
/6%
$0Y
During response transmission, new commands can be sent. If a command requiring a response is sent before the previous response is completed, the response transmission is aborted and the new response is loaded into the output communication buffer (see
).
Figure 29. Command response aborted
6',
IURPKRVW
6'2
WRKRVW
&RPPDQG
E\WHUHVSH[SHFWHG
[
&RPPDQG
QRUHVSH[SHFWHG
5HVSRQVHE\WH
06%
&RPPDQG
E\WHUHVSH[SHFWHG
5HVSRQVHE\WH
&RPPDQG
QRUHVSH[SHFWHG
5HVSRQVHE\WH
06%
&RPPDQG
QRUHVSH[SHFWHG
5HVSRQVHE\WH
/6%
&RPPDQGUHVSRQVH
LVDERUWHG
$0Y
When a byte that does not correspond to a command is sent to the IC it is ignored and the
CMD_ERROR flag in the STATUS register is raised (see paragraph
74/92 DS9836 Rev 7
powerSTEP01
11.2.2 Nop
Table 61. Nop command structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 0 0 0
Programming manual
From host
Nothing is performed.
11.2.3 SetParam (PARAM, VALUE)
Table 62. SetParam command structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 PARAM
VALUE byte 2 (if needed)
VALUE byte 1 (if needed)
VALUE byte 0
From host
The SetParam command sets the PARAM register value equal to VALUE; PARAM is the respective register address listed in
.
The command should be followed by the new register VALUE (most significant byte first).
The number of bytes composing the VALUE argument depends on the length of the target
).
Some registers cannot be written (see Table 12 ); any attempt to write one of those registers
causes the command to be ignored and the CMD_ERROR flag to rise at the end of the
command byte, as if an unknown command code were sent (see Section 11.1.28 on page
Some registers can only be written in particular conditions (see
write one of those registers when the conditions are not satisfied causes the command to be ignored and the CMD_ERROR flag to rise at the end of the last argument byte (see
Any attempt to set an inexistent register (wrong address value) causes the command to be ignored and the CMD_ERROR flag to rise at the end of the command byte as if an unknown command code were sent.
11.2.4 GetParam (PARAM)
Bit 7
0
Bit 6
0
Bit 5
Table 63. GetParam command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 PARAM
ANS byte 2 (if needed)
ANS byte 1 (if needed)
ANS byte 0
From host
To host
To host
To host
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Programming manual powerSTEP01
This command reads the current PARAM register value; PARAM is the respective register address listed in
The command response is the current value of the register (most significant byte first). The number of bytes composing the command response depends on the length of the target
).
The returned value is the register one at the moment of GetParam command decoding. If register values change after this moment, the response is not accordingly updated.
All registers can be read anytime.
Any attempt to read an inexistent register (wrong address value) causes the command to be ignored and the CMD_ERROR flag to rise at the end of the command byte as if an unknown command code were sent.
11.2.5 Run (DIR, SPD)
Bit 7
0
X
Bit 6
1
X
Bit 5
0
X
Table 64. Run command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1
X
0
SPD (byte 1)
SPD (byte 0)
0 0
SPD (byte 2)
DIR From host
From host
From host
From host
Note:
The Run command produces a motion at SPD speed; the direction is selected by the DIR bit: '1' forward or '0' reverse. The SPD value is expressed in step/tick (format unsigned fixed point 0.28) that is the same format as the SPEED register (
The SPD value should be lower than MAX_SPEED and greater than MIN_SPEED, otherwise the Run command is executed at MAX_SPEED or MIN_SPEED respectively.
This command keeps the BUSY flag low until the target speed is reached.
This command can be given anytime and is immediately executed.
11.2.6 StepClock (DIR)
Bit 7
0
Bit 6
1
Bit 5
Table 65. StepClock command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 1 1 0 0 DIR From host
The StepClock command switches the device in Step-clock mode ( Section 7.7.5 on page
28 ) and imposes the forward (DIR = '1') or reverse (DIR = '0') direction.
When the device is in Step-clock mode, the SCK_MOD flag in the STATUS register is raised and the motor is always considered stopped (
The device exits Step-clock mode when a constant speed, absolute positioning or motion command is sent through SPI. Motion direction is imposed by the respective StepClock
76/92 DS9836 Rev 7
powerSTEP01 Programming manual command argument and can by changed by a new StepClock command without exiting
Step-clock mode.
Events that cause bridges to be forced into high impedance state (overtemperature, overcurrent, etc.) do not cause the device to leave Step-clock mode.
The StepClock command does not force the BUSY flag low. This command can only be given when the motor is stopped. If a motion is in progress, the motor should be stopped and it is then possible to send a StepClock command.
Any attempt to perform a StepClock command when the motor is running causes the
command to be ignored and the CMD_ERROR flag to rise ( Section 11.1.28 on page 71 ).
11.2.7 Move (DIR, N_STEP)
Bit 7
0
X
Bit 6
1
X
Bit 5
0
Table 66. Move command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 DIR 0 0 0
N_STEP (byte 2)
N_STEP (byte 1)
N_STEP (byte 0)
From host
From host
From host
From host
The move command produces a motion of N_STEP microsteps; the direction is selected by the DIR bit ('1' forward or '0' reverse).
The N_STEP value is always in agreement with the selected step mode; the parameter value unit is equal to the selected step mode (full, half, quarter, etc.).
This command keeps the BUSY flag low until the target number of steps is performed. This command can only be performed when the motor is stopped. If a motion is in progress the motor must be stopped and it is then possible to perform a move command.
Any attempt to perform a move command when the motor is running causes the command to be ignored and the CMD_ERROR flag to rise (
11.2.8 GoTo (ABS_POS)
Bit 7
0
X
Bit 6
1
X
Bit 5
Table 67. GoTo command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 0 0 0 0 0
ABS_POS (byte 2)
ABS_POS (byte 1)
ABS_POS (byte 0)
From host
From host
From host
From host
The GoTo command produces a motion to ABS_POS absolute position through the shortest path. The ABS_POS value is always in agreement with the selected step mode; the parameter value unit is equal to the selected step mode (full, half, quarter, etc.).
The GoTo command keeps the BUSY flag low until the target position is reached.
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Programming manual powerSTEP01
This command can be given only when the previous motion command as been completed
(BUSY flag released).
Any attempt to perform a GoTo command when a previous command is under execution
(BUSY low) causes the command to be ignored and the CMD_ERROR flag to rise
( Section 11.1.28 on page 71 ).
11.2.9 GoTo_DIR (DIR, ABS_POS)
Bit 7
0
X
Bit 6
1
X
Bit 5
Table 68. GoTo_DIR command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 0 DIR 0 1 0
ABS_POS (byte 2)
ABS_POS (byte 1)
ABS_POS (byte 0)
From host
From host
From host
From host
The GoTo_DIR command produces a motion to ABS_POS absolute position imposing a forward (DIR = '1') or a reverse (DIR = '0') rotation. The ABS_POS value is always in agreement with the selected step mode; the parameter value unit is equal to the selected step mode (full, half, quarter, etc.).
The GoTo_DIR command keeps the BUSY flag low until the target speed is reached. This command can be given only when the previous motion command has been completed
(BUSY flag released).
Any attempt to perform a GoTo_DIR command when a previous command is under execution (BUSY low) causes the command to be ignored and the CMD_ERROR flag to
11.2.10 GoUntil (ACT, DIR, SPD)
Bit 7
1
X
Bit 6
0
X
Bit 5
Table 69. GoUntil command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
X
0
X
ACT
SPD (byte 1)
SPD (byte 0)
0 1
SPD (byte 2)
DIR From host
From host
From host
From host
The GoUntil command produces a motion at SPD speed imposing a forward (DIR = '1') or
), the ABS_POS register is reset (if ACT = '0') or the ABS_POS register value is copied into the MARK register (if ACT = '1'); the system then performs a SoftStop command.
The SPD value is expressed in step/tick (format unsigned fixed point 0.28) that is the same format as the SPEED register (
The SPD value should be lower than MAX_SPEED and greater than MIN_SPEED, otherwise the target speed is imposed at MAX_SPEED or MIN_SPEED respectively.
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powerSTEP01 Programming manual
If the SW_MODE bit of the CONFIG register is set low, the external switch turn-on event
causes a HardStop interrupt instead of the SoftStop one ( Section 7.14 on page 33
and
This command keeps the BUSY flag low until the switch turn-on event occurs and the motor is stopped. This command can be given anytime and is immediately executed.
11.2.11 ReleaseSW (ACT, DIR)
Bit 7
1
Bit 6
0
Table 70. ReleaseSW command structure
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 1 ACT 0 1 DIR From host
The ReleaseSW command produces a motion at minimum speed imposing a forward
(DIR = '1') or reverse (DIR = '0') rotation. When SW is released (opened) the ABS_POS register is reset (ACT = '0') or the ABS_POS register value is copied into the MARK register
(ACT = '1'); the system then performs a HardStop command.
Note that, resetting the ABS_POS register is equivalent to setting the HOME position.
If the minimum speed value is less than 5 step/s or low speed optimization is enabled, the motion is performed at 5 step/s.
The ReleaseSW command keeps the BUSY flag low until the switch input is released and the motor is stopped.
11.2.12 GoHome
Bit 7
0
Bit 6
1
Bit 5
Table 71. GoHome command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 1 0 0 0 0 From host
The GoHome command produces a motion to the HOME position (zero position) via the shortest path.
Note that, this command is equivalent to the “GoTo(0…0)” command. If a motor direction is mandatory, the GoTo_DIR command must be used (
The GoHome command keeps the BUSY flag low until the home position is reached. This command can be given only when the previous motion command has been completed. Any attempt to perform a GoHome command when a previous command is under execution
(BUSY low) causes the command to be ignored and the CMD_ERROR to rise
( Section 11.1.28 on page 71 ).
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Programming manual
11.2.13 GoMark
Bit 7
0
Bit 6
1
Bit 5
Table 72. GoMark command structure
Bit 4 Bit 3 Bit 2 Bit 1
1 1 1 0 0
Bit 0
0 powerSTEP01
From host
The GoMark command produces a motion to the MARK position performing the minimum path.
Note that, this command is equivalent to the “GoTo (MARK)” command. If a motor direction is mandatory, the GoTo_DIR command must be used.
The GoMark command keeps the BUSY flag low until the MARK position is reached. This command can be given only when the previous motion command has been completed
(BUSY flag released).
Any attempt to perform a GoMark command when a previous command is under execution
(BUSY low) causes the command to be ignored and the CMD_ERROR flag to rise
( Section 11.1.28 on page 71 ).
11.2.14 ResetPos
Bit 7
1
Bit 6
1
Bit 5
Table 73. ResetPos command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 1 1 0 0 0 From host
The ResetPos command resets the ABS_POS register to zero. The zero position is also defined as the HOME position (
11.2.15 ResetDevice
Bit 7
1
Bit 6
1
Table 74. ResetDevice command structure
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 0 From host
Note:
The ResetDevice command resets the device to power-up conditions (
At power-up the power bridges are disabled.
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11.2.16 SoftStop
Bit 7
1
Bit 6
0
Programming manual
Bit 5
Table 75. SoftStop command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 1 0 0 0 0 From host
The SoftStop command causes an immediate deceleration to zero speed and a consequent motor stop; the deceleration value used is the one stored in the DEC register
).
When the motor is in high impedance state, a SoftStop command forces the bridges to exit from high impedance state; no motion is performed.
This command can be given anytime and is immediately executed. This command keeps the BUSY flag low until the motor is stopped.
11.2.17 HardStop
Bit 7
1
Bit 6
0
Bit 5
Table 76. HardStop command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 1 1 0 0 0 From host
The HardStop command causes an immediate motor stop with infinite deceleration.
When the motor is in high impedance state, a HardStop command forces the bridges to exit high impedance state; no motion is performed.
This command can be given anytime and is immediately executed. This command keeps the BUSY flag low until the motor is stopped.
11.2.18 SoftHiZ
Bit 7
1
Bit 6
0
Bit 5
Table 77. SoftHiZ command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 0 0 0 0 0 From host
The SoftHiZ command disables the power bridges (high impedance state) after a deceleration to zero; the deceleration value used is the one stored in the DEC register
). When bridges are disabled, the HiZ flag is raised.
When the motor is stopped, a SoftHiZ command forces the bridges to enter high impedance state.
This command can be given anytime and is immediately executed. This command keeps the BUSY flag low until the motor is stopped.
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Programming manual
11.2.19 HardHiZ
Bit 7
1
Bit 6
0
Bit 5
Table 78. HardHiZ command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 0 1 0 0 0 powerSTEP01
From host
The HardHiZ command immediately disables the power bridges (high impedance state) and raises the HiZ flag.
When the motor is stopped, a HardHiZ command forces the bridges to enter high impedance state.
This command can be given anytime and is immediately executed.
This command keeps the BUSY flag low until the motor is stopped.
11.2.20 GetStatus
Bit 7
1
Bit 6
1
Bit 5
Table 79. GetStatus command structure
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 1 0 0 0 0 From host
STATUS MSbyte
STATUS LSbyte
To host
To host
The GetStatus command returns the status register value.
The GetStatus command resets the STATUS register warning flags. The command forces the system to exit from any error state. The GetStatus command does not reset the HiZ flag.
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12 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK is an ST trademark.
12.1 VFQFPN 11x14x10 package information
Figure 30. VFQFPN (11x14x1.0) package outline
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Package information powerSTEP01
Figure 31. VFQFPN (11x14x1.0) bottom view package outline
84/92 DS9836 Rev 7
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Figure 32. VFQFPN (11x14x1.0) pin identifier package outline
DS9836 Rev 7 85/92
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Package information powerSTEP01
Symbol
Table 80. VFQFPN (11x 14x1.0) package mechanical data (1)
Dimensions (mm)
Min.
Typ.
Max.
Note
E3
D4
E4
L
E1
D2
E2
D3
A
A1
A3 b
D
E
D1 aaa bbb ccc ddd eee
N
0.80
0.00
---
0.15
10.90
13.90
2.00
2.70
5.35
4.54
2.17
2.88
1.01
0.54
0.30
0.90
0.02
0.20 ref.
0.2
11.00
14.00
2.15
2.85
5.50
4.69
2.32
3.04
1.16
0.69
0.40
0.10
0.10
0.10
0.05
0.08
89
1.00
0.05
---
0.25
11.10
14.10
2.25
2.95
5.60
4.79
2.42
3.13
1.26
0.79
0.50
(2)
(3)
(4)
1. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. Exact shape and size of this feature is optional.
2. VFQFPN stands for thermally enhanced very thin fine pitch quad flat packages no lead. Very thin: 0.80 mm
< A ≤1.00 mm / fine pitch: e < 1.00 mm. Dimensioning and tolerances conform to ASME Y14.5-2009. All dimensions are in millimeters. The location of the marked terminal #1 identifier is within the hatched area.
Coplanarity applies to the terminals and all other bottom surface metalization.
3. Dimension b applies to the metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has a radius on the other end of it, dimension b should not be measured in that radius area.
4. N is the total number of terminals.
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Figure 33. VFQFPN (11x 14x1.0) suggested footprint
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Figure 34. VFQFPN (11x 14x1.0) footprint lead land positioning
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Figure 35. VFQFPN (11x 14x1.0) land size and exposed pad positioning
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Figure 36. VFQFPN (11x 14x1.0) footprint - detail A and B powerSTEP01
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13 Revision history
Revision history
2
Date
22-Jul-2013
16-Jun-2014
03-Oct-2014
22-Apr-2015
10-Jun-2015
09-Nov-2017
28-Jan-2020
Table 81. Document revision history
Revision Changes
1
2
3
4
5
6
7
Initial release.
Several modifications.
Updated main title on page 1 (replaced “8-N channel” by “10 A”).
Updated package silhouette on page 1 (replaced by new figure).
Updated Section : Applications on page 1 (added sub-list).
I
Updated Table 2 on page 10 (removed “P tot
OUT1x
symbol).
”, “Peak” and unit of
Updated Table 4 on page 12 (updated “Test conditions” and values of R
DS(on)
, SR
OUT
, I
DSS and t
OCD,SD
symbols).
Added Section 7.15 on page 34 . Minor modifications throughout document.
Document updated from “preliminary” to “production data”.
Updated Table 4 on page 12 (updated max. values).
Updated Table 5 on page 18 (updated pin no. of OUTA1).
Updated Table 8 on page 32 [replaced “Of” by “On” in High-side gate driver supply turn-on threshold V
BOOTthon
)].
Updated Table 12 on page 51 (updated length column of
STEP_MODE and FS_SPD).
Updated Table 15 on page 55 (removed Bit 11 column).
Updated Section 12: Package information on page 83 (replaced
Figure 30 to Figure 32 and Table 80 by new figures/table).
Minor modifications throughout document.
Updated Table 4 on page 12 (updated max. values).
Updated Table 45 on page 68 (updated values).
Added Figure 33 on page 87 to Figure 36 on page 90 .
Minor modifications throughout document.
Updated Section 12.1: VFQFPN 11x14x10 package information
.
Minor text changes.
amended and Footnotes added.
Table 12 updated. Change to title of
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
92/92 DS9836 Rev 7
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