STMicroelectronics VNN1NV04P-E Datasheet

VNN1NV04P-E, VNS1NV04P-E

OMNIFET II fully autoprotected Power MOSFET

Features

Parameter Symbol Value

Max on-state resistance (per ch.) R

Current limitation (typ)

Drain-source clamp voltage

I

ON

LIMH

V

CLAMP

250 m 

1.7 A

40 V

• Linear current limitation

• Thermal shutdown

• Short circuit protection

• Integrated clamp

• Low current drawn from input pin

• Diagnostic feedback through input pin

• ESD protection

• Direct access to the gate of the Power

MOSFET (analog driving)

• Compatible with standard Power MOSFET

2

1

2

3

SOT-223 SO-8

Description

The VNN1NV04P-E, VNS1NV04P-E are monolithic devices designed in

STMicroelectronics VIPower M0-3 Technology, intended for replacement of standard Power

MOSFETs from DC up to 50 kHz applications.

Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments.

Fault feedback can be detected by monitoring the voltage at the input pin.

September 2013

Table 1.

Device summary

Order codes

Package

Tube Tape and reel

SOT-223 VNN1NV04P-E VNN1NV04PTR-E

SO-8 VNS1NV04P-E VNS1NV04PTR-E

Doc ID 15586 Rev 3 1/28 www.st.com

28

2/28

3

4

1

2

Contents

Contents

5

6

VNN1NV04P-E, VNS1NV04P-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1

SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1

SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2

SO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3

SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.4

SO8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SOT-223 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Doc ID 15586 Rev 3 3/28

List of figures

List of figures

VNN1NV04P-E, VNS1NV04P-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4.

Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5.

Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6.

Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7.

Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8.

Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9.

Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 10.

Static drain-source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11.

Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 12.

Static drain-source on resistance vs input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 13.

Static drain-source on resistance vs input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 14.

Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 15.

Static drain-source on resistance vs Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 16.

Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 17.

Turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 18.

Turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 19.

Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 20.

Turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 21.

Turn-off drain-source voltage slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 22.

Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 23.

Switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 24.

Switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 25.

Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 26.

Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 27.

Normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 28.

Normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 29.

Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 30.

SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 31.

SOT-223 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . 17

Figure 32.

SOT-223 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 33.

SOT-223 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 34.

SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 35.

SO-8 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . 19

Figure 36.

SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 37.

SO-8 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 38.

SOT-223 mechanical data and package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 39.

SO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 40.

SOT-223 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 41.

SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 42.

SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4/28 Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

DRAIN

2

Overvoltage

Clamp

INPUT

1

Gate

Control

Over

Temperature

Linear

Current

Limiter

3

SOURCE

Figure 2.

Configuration diagram (top view)

(a)

SOURCE

SOURCE

SOURCE

INPUT

1

4

8

5

DRAIN

DRAIN

DRAIN

DRAIN a. For the pins configuration related to SOT-223 see outline at page 1.

Doc ID 15586 Rev 3 5/28

Electrical specifications VNN1NV04P-E, VNS1NV04P-E

Figure 3.

Current and voltage conventions

I

IN

R

IN

INPUT

DRAIN

SOURCE

I

D

V

IN

V

DS

2.1 Absolute maximum ratings

Stress values that exceed those listed in the “Absolute maximum ratings” table can cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions greater than those, indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality documents.

Table 2.

Absolute maximum ratings

Symbol Parameter

V

DSn

V

INn

I

INn

R

IN MINn

I

Dn

I

Rn

V

ESD1

V

ESD2

P tot

T j

T c

T stg

Drain-source voltage (V

INn

=0 V)

Input voltage

Input current

Minimum input series impedance

Drain current

Reverse DC output current

Electrostatic discharge (R=1.5 K  , C=100 pF)

Electrostatic discharge on output pins only

(R=330  , C=150 pF)

Total dissipation at T c

=25 °C

Operating junction temperature

Case operating temperature

Storage temperature

Value

SOT-223 SO-8

Internally clamped

Internally clamped

+/-20

330

Internally limited

-3

4000

16500

7 8.3

Internally limited

Internally limited

-55 to 150

Unit

V

W

°C

°C

°C

V

V mA



A

A

V

6/28 Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E Electrical specifications

Table 3.

Thermal data

Max value

Symbol Parameter Unit

SOT-223 SO-8

R thj-case

Thermal resistance junction-case 18 °C/W

R thj-lead

R thj-amb

Thermal resistance junction-lead

Thermal resistance junction-ambient 70 (1)

15

65 (1)

°C/W

°C/W

1. When mounted on a standard single-sided FR4 board with 50 mm 2 to all DRAIN pins

of Cu (at least 35  m thick) connected

Table 4.

Symbol

Electrical characteristics

Parameter Test conditions Min Typ

Off (-40 °C<Tj<150 °C, unless otherwise specified)

V

CLAMP

V

CLTH

Drain-source clamp voltage

Drain-source clamp threshold voltage

V

V

IN

IN

=0 V; I

=0 V; I

D

D

=0.5 A 40

=2 mA 36

45

V

V

I

I

INTH

ISS

INCL

DSS

Input threshold voltage V

DS

=V

IN

; I

D

=1 mA 0.5

Supply current from input pin V

DS

=0 V; V

IN

=5 V 100

Input-source clamp voltage

I

IN

=1 mA

I

IN

=-1 mA

6

-1.0

6.8

Zero input voltage drain current (V

IN

=0 V)

V

DS

=13 V; V

IN

=0 V; T j

=25 °C

V

DS

=25 V; V

IN

=0 V

On (-40 °C<Tj<150 °C, unless otherwise specified)

R

DS(on)

Static drain-source on resistance

V

IN

=5 V; I

D

=0.5 A; T j

=25 °C

V

IN

=5 V; I

D

=0.5 A

Dynamic (T j

=25 °C, unless otherwise specified) g fs

(1)

Forward transconductance V

DD

=13 V; I

D

=0.5 A

C

OSS

Output capacitance

2

V

DS

=13 V; f=1 MHz; V

IN

=0 V 90

Switching (T j

=25 °C, unless otherwise specified) t d(on) t r t d(off) t f

Turn-on delay time

Rise time

Turn-off delay time

Fall time

V

DD

V gen

=15 V; I

D

(see

=5 V; R gen

Figure 4

=0.5 A

)

=R

IN MIN

=330 

70

170

350

200

Max

55

250

500

200

500

1000

600

2.5

150

8

-0.3

30

75

Unit

µA m 

S pF ns ns ns ns

V

V

V

µA

V

Doc ID 15586 Rev 3 7/28

8/28

Electrical specifications VNN1NV04P-E, VNS1NV04P-E

Table 4.

Symbol

Electrical characteristics (continued)

Parameter Test conditions Min t d(on) t r t d(off) t f

Turn-on delay time

Rise time

Turn-off delay time

Fall time

V

DD

V gen

=15 V; I

D

(see

=5 V; R gen

Figure 4

=0.5 A

)

=2.2 K 

(dI/dt)

Q i on

Turn-on current slope

Total input charge

V

DD

=15 V; I

D

=1.5 A

V gen

=5 V; R gen

=R

IN MIN

=330 

V

DD

=12 V; I

D

=0.5 A; V

IN

=5 V

I gen

=2.13 mA (see

Figure 7

)

Source drain diode (T j

=25 °C, unless otherwise specified)

V

SD

(1)

t rr

Forward on voltage

Reverse recovery time

I

SD

=0.5 A; V

IN

=0 V

Q rr

Reverse recovery charge

I

RRM

Reverse recovery current

I

SD

=0.5 A; dI/dt=6 A/µs

V

DD

=30 V; L=200 µH

(see Figure 5 )

Protections (-40 °C<T j

<150 °C, unless otherwise specified)

I lim t dlim

T jsh

T jrs

I gf

E as

Drain current limit

Step response current limit

Over temperature shutdown

Over temperature reset

V

V

IN

IN

=5 V; V

=5 V; V

DS

DS

=13 V 1.7

=13 V

Fault sink current

Single pulse avalanche energy

V

IN

=5 V; V

DS

=13 V; T j

=T jsh

Starting T j

=25 °C; V

DD

=24 V

V

IN

=5 V R gen

=R

IN MIN

=330 

L=50 mH

(see Figure 6 and

Figure 8

)

150

135

10

55

1. Pulsed: pulse duration = 300 µs, duty cycle 1.5 %

5

0.8

205

100

0.7

Typ

0.25

1.3

1.8

1.2

5

Max

1.0

4.0

5.5

4.0

Unit

µs

µs

µs

µs

A/µs

2.0

175

15

3.5

200

20 nC

A

µs

°C

°C mA mJ

V ns nC

A

Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E

Figure 4.

Switching time test circuit for resistive load

Electrical specifications

I

D

V gen t d(on) t r

90%

10% t d(off) t f

V gen

V

D

R gen t t

Doc ID 15586 Rev 3 9/28

Electrical specifications

Figure 5.

Test circuit for diode recovery times

VNN1NV04P-E, VNS1NV04P-E

330 

D

I

OMNIFET

S

B

A

FAST

DIODE

R gen

A

B

I

OMNIFET

D

L=100uH

V

DD

V gen

S

8.5 

Figure 6.

Unclamped inductive load test circuits

10/28

V

IN

P

W

R

GEN

Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E

Figure 7.

Input charge test circuit

Electrical specifications

V

IN

GEN

Figure 8.

Unclamped inductive waveforms

ND8003

Doc ID 15586 Rev 3 11/28

Electrical specifications VNN1NV04P-E, VNS1NV04P-E

Figure 9.

Source-drain diode forward characteristics

Vsd (mV)

1000

950

900

850

800

750

700

0 2

Vin=0V

4 6

Id (A)

8

Figure 11. Derating curve

10 12 14

Figure 13. Static drain-source on resistance vs input voltage (part 2/2)

Rds(on) (mohms)

500

Tj=150ºC

450

400

350

300

250

Tj=25ºC

200

150

Tj=-40ºC

100

50

0

3 3.5

4 4.5

Vin(V)

5 5.5

6

Id=1.5A

Id=1A

Id=1.5A

Id=1A

Id=1.5A

Id=1A

6.5

Figure 10. Static drain-source on resistance

Rds(on) (ohms)

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

0

Vin=2.5V

0.05

0.1

Tj=-40ºC

0.15

Id(A)

0.2

0.25

Tj=25ºC

Tj=150ºC

0.3

Figure 12. Static drain-source on resistance vs input voltage (part 1/2)

Rds(on) (mohms)

500

450

400

350

300

250

200

150

100

50

0

3 3.5

4 4.5

5

Vin(V)

5.5

Id=0.5A

Tj=150ºC

6

Tj=25ºC

Tj=-40ºC

6.5

7

Figure 14. Transconductance

Gfs (S)

6

3

2.5

2

1.5

1

0.5

0

5.5

5

4.5

4

3.5

0 0.25

Vds=13V

0.5

0.75

1

Id(A)

1.25

Tj=-40ºC

Tj=25ºC

Tj=150ºC

1.5

1.75

2

12/28 Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E Electrical specifications

Figure 15. Static drain-source on resistance vs Id

300

250

200

150

100

50

0

0

Rds(on) (mohms)

500

450

400

350

0.25

0.5

Tj=150ºC

Tj=25ºC

Tj=-40ºC

0.75

1

Id(A)

1.25

Vin=3.5V

Vin=5V

Vin=3.5V

Vin=5V

Vin=3.5V

Vin=5V

1.5

1.75

2

Figure 17. Turn-on current slope (part 1/2) di/dt(A/us)

6

Figure 16. Transfer characteristics

1.5

1.25

1

0.75

0.5

0.25

Idon(A)

2.25

2

1.75

Vds=13.5V

Tj=150ºC

Tj=-40ºC

Tj=25ºC

0

1.5

1.75

2

2.25

2.5

2.75

3

3.25

3.5

3.75

Vin(V)

4

4.25

4.5

4.75

5

Figure 18. Turn-on current slope (part 2/2) di/dt(A/us)

1.4

5

1.2

4

Vin=5V

Vdd=15V

Id=1.5A

1

Vin=3.5V

Vdd=15V

Id=1.5A

3

0.8

2

0.6

1

0.4

0

0 500 1000

Rg(ohm)

1500 2000 2500

Figure 19. Input voltage vs input charge

Vin (V)

6

5

4

3

2

1

0

0 1

Vds=12V

Id=0.5A

2 3

Qg (nC)

4 5 6

0.2

0 500 1000 1500

Rg(ohm)

2000 2500

Figure 20. Turn-off drain source voltage slope

(part 1/2) dv/dt(V/us)

350

300

250

200

150

100

50

0

0 500 1000 1500

Rg(ohm)

Vin=5V

Vdd=15V

Id=0.5A

2000 2500

Doc ID 15586 Rev 3 13/28

Electrical specifications VNN1NV04P-E, VNS1NV04P-E

Figure 21. Turn-off drain-source voltage slope

(part 2/2)

Figure 22. Capacitance variations dv/dt(V/us)

350

C(pF)

225

300

200

250

Vin=3.5V

Vdd=15V

Id=0.5A

175 f=1MHz

Vin=0V

200

150

150

125

100

100

50

75

50

0 5 10 15

Vds(V)

20 25 30

0

0 500 1000

Rg(ohm)

1500 2000 2500

Figure 23. Switching time resistive load

(part 1/2) t(us)

2

1.75

1.5

1.25

1

Vdd=15V

Id=0.5A

Vin=5V td(off) tr tf

0.75

0.5

0.25

td(on)

0

0 250 500 750 1000 1250 1500 1750 2000 2250 2500

Rg(ohm)

Figure 25. Output characteristics

35

Figure 24. Switching time resistive load

(part 2/2) t(ns)

550

500

450

400

350

300

250

200

150

100

50

0

3.25

3.5

tr td(on)

3.75

4 4.25

Vin(V)

4.5

Vdd=15V

Id=0.5A

Rg=330ohm td(off)

4.75

tf

5 5.25

Figure 26. Normalized on resistance vs temperature

Rds(on) (mOhm)

2.25

ID(A)

1.4

1.2

1

0.8

0.6

0.4

0.2

0

2.4

2.2

2

1.8

1.6

0 1 2 3 4

Vin=5.5V

Vin=4.5V

Vin=3.5V

Vin=3V

5 6

VDS(V)

7 8 9 10 11 12

2

1.75

1.5

1.25

1

0.75

0.5

-50 -25

Vin=5V

Id=0.5A

0 25 50 75

Tc (ºC)

100 125 150 175

14/28 Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E Electrical specifications

Figure 27. Normalized input threshold voltage vs temperature

Figure 28. Normalized current limit vs junction temperature

1.2

1

0.8

0.6

0.4

0.2

0

-50

Vinth (V)

2

1.8

1.6

1.4

-25

Vds=Vin

Id=1mA

0 25 50 75

Tc (ºC)

100 125 150 175

Ilim (A)

5

4.5

4

3.5

3

2.5

2

1.5

0.5

1

0

-50 -25

Vin=5V

Vds=13V

0 25 50 75

Tc (ºC)

100 125 150 175

Figure 29. Step response current limit

Tdlim(us)

2.4

2.3

2.2

2.1

Vin=5V

Rg=330ohm

2

1.9

5 10 15 20

Vdd(V)

25 30 35

Doc ID 15586 Rev 3 15/28

16/28

Protection features VNN1NV04P-E, VNS1NV04P-E

During normal operation, the input pin is electrically connected to the gate of the internal

Power MOSFET through a low impedance path.

The device then behaves like a standard Power MOSFET and can be used as a switch from

DC up to 50 kHz. The only difference from the user’s standpoint is that a small DC current

I

ISS

(typ. 100 µA) flows into the input pin in order to supply the internal circuitry.

The device integrates:

?

?

?

?

Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.

Linear current limiter circuit: limits the drain current I

D

to I lim

whatever the input pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the over temperature threshold T jsh.

Over temperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Over temperature cutout occurs in the range 150 to 190 °C, a typical value being 170 °C. The device is automatically restarted when the chip temperature falls of about 15 °C below shutdown temperature.

Status feedback: in the case of an over temperature fault condition (T j device tries to sink a diagnostic current I gf

> T jsh

), the

through the input pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the input pin driver is not able to supply the current I gf

, the input pin will fall to 0 V.

This will not however affect the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current I

ISS

.

Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL logic circuit.

Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E

4 Package and PCB thermal data

Package and PCB thermal data

4.1 SOT-223 thermal data

Figure 30. SOT-223 PC board

Note:

.

Layout condition of R th

and Z th

measurements (PCB FR4 area = 58 mm x 58 mm,PCB thickness = 2 mm, Cu thickness=35 µm, Copper areas: from minimum pad layout to

0.8 cm 2 ).

Figure 31. SOT-223 R thj-amb

vs PCB copper area in open box free air condition

140

130

120

110

100

90

80

70

60

0 footprint

0,5 1 1,5 2

PCB Cu heatsink area (cm^ 2) - (refer to PCB layout)

2,5

Doc ID 15586 Rev 3 17/28

Package and PCB thermal data VNN1NV04P-E, VNS1NV04P-E

Figure 32. SOT-223 thermal impedance junction ambient single pulse

ZTH (°C/ W)

1000

100

Footprint

2 cm 2

10

1

0,1

0,0001 0,001 0,01 0,1

Time ( s)

1 10

Equation 1: pulse calculation formula

ZTH



= RTH where  = t

P

/T

  + –  

Figure 33. SOT-223 thermal fitting model of a single channel

100 1000

18/28

Table 5.

SOT-223 thermal parameter

Area/island (cm

2

)

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

Doc ID 15586 Rev 3

FP

0.8

1.6

4.5

24

0.1

100

2

45

VNN1NV04P-E, VNS1NV04P-E Package and PCB thermal data

Table 5.

SOT-223 thermal parameter (continued)

Area/island (cm 2 ) FP

C1 (W·s/°C)

C2 (W·s/°C)

C3 (W·s/°C)

C4 (W·s/°C)

C5 (W·s/°C)

C6 (W·s/°C)

0.00006

0.0005

0.03

0.16

1000

0.5

2

2

4.2 SO-8 thermal data

Figure 34. SO-8 PC board

Note: Layout condition of R th

and Z th

measurements (PCB FR4 area = 58 mm x 58 mm,PCB thickness = 2 mm, Cu thickness=35 µm, Copper areas: from minimum pad layout to 2 cm 2 ).

Figure 35. SO-8 R thj-amb

vs PCB copper area in open box free air condition

105 footprint

95

85

75

65

0 0,5 1 1,5 2

PCB Cu heatsink area (cm^ 2) - (refer to PCB layout)

2,5

Doc ID 15586 Rev 3 19/28

Package and PCB thermal data VNN1NV04P-E, VNS1NV04P-E

Figure 36. SO-8 thermal impedance junction ambient single pulse

ZTH (°C/ W )

1000

100

Footprint

2 cm 2

10

1

0,1

0,0001 0,001 0,01 0,1

Time (s)

1 10

Equation 2: pulse calculation formula

ZTH



= RTH   + –   where  = t

P

/T

Figure 37. SO-8 thermal fitting model of a single channel

100 1000

20/28

Table 6.

SO-8 thermal parameter

Area/island (cm

2

)

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

Doc ID 15586 Rev 3

FP

0.8

2.6

3.5

21

2

VNN1NV04P-E, VNS1NV04P-E Package and PCB thermal data

Table 6.

SO-8 thermal parameter (continued)

Area/island (cm 2 )

R5 (°C/W)

R6 (°C/W)

C1 (W·s/°C)

C2 (W·s/°C)

C3 (W·s/°C)

C4 (W·s/°C)

C5 (W·s/°C)

C6 (W·s/°C)

FP

16

58

0.00006

0.0005

0.0075

0.045

0.35

1.05

2

28

2

Doc ID 15586 Rev 3 21/28

Package and packing information

5 Package and packing information

VNN1NV04P-E, VNS1NV04P-E

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

5.1 SOT-223 mechanical data

Figure 38. SOT-223 mechanical data and package outline

22/28 Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E Package and packing information

Table 7.

SO-8 mechanical data mm

Dim.

A

Min. Typ. Max.

A1 0.10

A2 1.25

b 0.28

c 0.17

D

(1)

4.80

E 5.80

E1

(2)

3.80

4.90

6.00

3.90

1.75

0.25

0.48

0.23

5.00

6.20

4.00 h 0.25

L 0.40

L1 k 0° ccc

1.04

0.50

1.27

8°

0.10

1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side).

2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side.

Doc ID 15586 Rev 3 23/28

Package and packing information

Figure 39. SO-8 package dimension

VNN1NV04P-E, VNS1NV04P-E

0016023 D

24/28 Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E

5.3 SOT-223 packing information

Package and packing information

Figure 40. SOT-223 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

1000

1000

330

1.5

13

20.2

12.4

60

18.4

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W 12

P0 (± 0.1)

P

4

8

D (+ 0.1/-0) 1.5

D1 (min)

F (± 0.05)

K (max)

P1 (± 0.1)

1.5

5.5

4.5

2

All dimensions are in mm.

End

Top cover tape

No components

500mm min

Components No components

Empty components pockets saled with cover tape.

500mm min

User direction of feed

Start

Doc ID 15586 Rev 3 25/28

Package and packing information VNN1NV04P-E, VNS1NV04P-E

Figure 41. SO-8 tube shipment (no suffix)

B

C

A

Base Q.ty

Bulk Q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

All dimensions are in mm.

100

2000

532

3.2

6

0.6

Figure 42. SO-8 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

2500

2500

330

1.5

13

20.2

12.4

60

18.4

All dimensions are in mm.

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (± 0.1)

12

4

P 8

D (+ 0.1/-0) 1.5

D1 (min)

F (± 0.05)

K (max)

P1 (± 0.1)

1.5

5.5

4.5

2

All dimensions are in mm.

End

Top cover tape

No components

500mm min

Components No components

Empty components pockets saled with cover tape.

500mm min

User direction of feed

Start

26/28 Doc ID 15586 Rev 3

VNN1NV04P-E, VNS1NV04P-E

Table 8.

Date

Document revision history

16-May-2009

29-Sep-2009

20-Sep-2013

Revision

1

2

3

Changes

Initial release.

Removed target specification on cover page.

Updated Disclaimer.

Revision history

Doc ID 15586 Rev 3 27/28

VNN1NV04P-E, VNS1NV04P-E

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28/28 Doc ID 15586 Rev 3