STMicroelectronics L5988D Datasheet

L5988D

4 A continuous (more than 5 A pulsed) step-down switching regulator with synchronous rectification

Datasheet

-

production data

 F

SW

programmable up to 1 MHz

 Voltage feed forward

 Zero load current operation

 Programmable current limit on both switches

 Programmable sink current capability

 Pre-bias start up capability

 Thermal shutdown

HTSSOP16

Applications

Features

 4 A output current (more than 5 pulsed)

 Operating input voltage from 2.9 V to 18 V

 External 1.8 V ± 2% reference voltage

 Output voltage from 0.6 to input voltage

 MLCC compatible

 200 ns T

ON

 Programmable UVLO matches 3.3 V, 5 V and

12 V bus

 Consumer: STB, DVD, LCD TV, VCR, car radio, LCD monitors







Networking: XDSL, modems, routers and switches

 Computer and peripherals: printers, audio / graphic cards, optical storage, hard disk drive

Industrial: DC-DC modules, factory automation

HC LED driving

Figure 1. Test application circuit

April 2015

This is information on a product in full production.

DocID15324 Rev 4 1/52 www.st.com

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Contents

Contents

6

L5988D

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1

Multifunction pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2

Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3

External voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.4

Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5

Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.5.1

5.5.2

5.5.3

5.5.4

Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.6

Minimum on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.7

Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1

Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.2

Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3

Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4

Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.1

6.4.2

Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.5

R.M.S. current of the embedded power MOSFETs . . . . . . . . . . . . . . . . . 36

6.6

Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.7

Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.8

Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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L5988D

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8

Contents

Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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52

List of tables

List of tables

L5988D

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

A/D voltage windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

UOS voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FSW resistor examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9.

ILIM-ADJ resistor examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 10.

Uncompensated error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 11.

Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 12.

Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 13.

Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 14.

Component list application circuit (f

SW

Table 15.

Component list application circuit (f

SW

= 400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

= 600 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 16.

HTSSOP16 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 17.

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 18.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4/52 DocID15324 Rev 4

L5988D

List of figures

List of figures

Figure 1.

Test application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2.

Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

Voltage mode control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4.

Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6.

Sawtooth: voltage feed forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7.

Sawtooth: synchronization and frequency adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8.

Input RMS current of two synchronized regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9.

OVP not latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10.

OVP latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11.

Constant current protection at extreme duty cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12.

Minimum TON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13.

Type III compensation network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14.

Open loop gain: module bode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 15.

Open loop gain bode diagram with ceramic output capacitor . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 16.

Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 17.

Open loop gain: module bode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 18.

Open loop gain bode diagram with high ESR output capacitor . . . . . . . . . . . . . . . . . . . . . 35

Figure 19.

Maximum continuous output current vs. duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 20.

Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 21.

Estimation of the internal power losses (V

IN

Figure 22.

Estimation of the internal power losses (V

IN

= 12 V, V

OUT

= 5 V, V

OUT

= 1.2 V, f

= 1.2 V, f

SW

SW

= 400 kHz). . . . . . 39

= 400 kHz). . . . . . . 40

Figure 23.

Measurement of the thermal impedance of the evaluation board. . . . . . . . . . . . . . . . . . . . 41

Figure 24.

Top board layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 25.

Bottom board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 26.

Demonstration board application circuit (f

SW

Figure 27.

Demonstration board application circuit (f

SW

Figure 28.

Junction temperature vs. f

SW at V

IN

= 400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 43

= 600 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 45

= 12 V, V

OUT at V

IN

= 5 V, V

OUT

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . 46

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 29.

Junction temperature vs.

f

SW

Figure 30.

Figure 31.

Junction temperature vs. V

Figure 32.

Junction temperature vs. V

OUT at V

IN

Figure 33.

Junction temperature vs. V

OUT at V

IN

Figure 34.

Figure 35.

Junction temperature vs. f

SW at V

OUT at V

Efficiency vs. output current at V

Efficiency vs. output current at V

IN

IN

IN

= 3.3 V, V

OUT

IN

= 12 V, f

= 5 V, f

SW

= 400 kHz . . . . . . . . . . . . . . . . . . . . . . . 47

= 3.3 V, f

SW

= 3.3 V, f

SW

= 5 V, f

SW

= 1.2 V . . . . . . . . . . . . . . . . . . . . . . . . 46

SW

= 400 kHz . . . . . . . . . . . . . . . . . . . . . . 46

= 400 kHz . . . . . . . . . . . . . . . . . . . . . . 47

= 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . 47

= 250 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 36.

Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 37.

Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 38.

Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 39.

Load transient from 0 to 3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 40.

Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 41.

HTSSOP16 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DocID15324 Rev 4 5/52

52

Description

1 Description

L5988D

The L5988D is a monolithic step down power switching regulator able to deliver a continuous output current of 4 A to the load in most of the application conditions limited only by the thermal performance. The device is able to deliver more than 5 A to the load for a maximum time which is dependent on the thermal impedance of the system and the specific operating conditions).

The input voltage can range from 2.9 V to 18 V. The device is capable of 100% duty cycle operation thanks to the embedded high side PMOS switch which doesn’t need external bootstrap capacitor to be driven.

The internal switching frequency is adjustable by external resistor and can be set continuously from 100 kHz to 1 MHz. The L5988D can also be synchronized to an external frequency signal driven to the SYNCH pin I/O pin.

The multifunction UOS pin allows to set-up properly the additional embedded features depending on the value of the voltage level.

 U (UVLO): two UVLO thresholds can be selected to match the 3.3 V and 5 V or 12 V input buses

 O (OVP): latched or not latched OVP protection selectable. In latched mode the switching activity is interrupted until an UVLO or INH event happens

 S (SINK): the sink capability is always disabled during soft-start time to support prebiased output voltage. Afterwards the sink capability can be enabled or not depending on the voltage set on the multifunction pin.

During soft-start phase a constant current protection is active to deliver extra current necessary to load the output capacitor. The current limit protection is achieved by sensing the current flowing in both embedded switches to assure an effective protection even at extreme duty cycle operations. Finished the soft-start phase the current protection feature triggers the “HICCUP” mode forcing the soft-start capacitor to be discharged and recharged.

The current thresholds of both switches can be adjusted in tracking by using an external resistor to dimension the current protection accordingly to the local application.

The soft-start time is based on a constant current charge of an external capacitor. As a consequence the time can be set accordingly to the value of the output capacitor.

The latest smart power technology BCD6 (Bipolar-CMOS-DMOS version 6) features a low resistance of the embedded switches (35 m  typical for a NMOS, 50 m  typical for a

PMOS), achieving high efficiency levels.

The HTSSOP16 package with exposed pad accomplishes low R thJA

(40 °C/W), useful in dissipating power internally generated during high output current / high frequency operations.

6/52 DocID15324 Rev 4

L5988D

Figure 2. Pin connection

Pin function

No.

1, 16

2, 3

4

5

6

7

8

9

10

11

12

13

14, 15

Name

Table 1. Pinout description

Description

OUT

VIN

VCC

Regulator output

Unregulated DC input voltage

Unregulated DC signal input voltage

SS/INH

An external logic signal (active LOW) disables the device. In case the pin is floating the device deliver a constant current (22  A typ.) to charge the

soft-start capacitor (see Section 5.4 on page 18 )

COMP Error amplifier output for frequency compensation

ILIM-ADJ

Connecting a pull-up resistor to VREF or a pull-down resistor to GND the internal current limit thresholds can be tuned to match the local application.

In case the pin is left floating no changes are applied to the default current limit thresholds

FB

Feedback input. Connecting the output voltage directly to this pin results in a regulation voltage of 600 mV. An external resistive divider is required for higher output voltages

SYNCH Master/slave synchronization

FSW

U/O/S

Connecting a pull-up resistor to VREF or a pull-down resistor to GND the internal oscillator frequency will be increased or decreased respectively. In case the pin is left floating the predefined oscillator frequency

(400 kHz ± 10%) is active

Multifunction pin used to program additional features: UVLO thresholds,

OVP latched/not latched, SINK enabled/disabled

VREF 1.8 V voltage reference

SGND Signal ground

PGND Power ground

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52

Maximum ratings L5988D

Symbol

Table 2. Absolute maximum ratings

Parameter Value Unit

VCC

VOUT

Input voltage

Output DC voltage

20

-0.3

(1) to VCC

U/O/S, SS/INH,

COMP, SYNCH,

Fsw, ILIM-ADJ

Analog pins

FB Feedback voltage

-0.3 to 4 V

1.5

V

P tot

T

J

T

STG

Power dissipation at T

A

< 60 °C

Junction temperature range

Storage temperature range

2.25

-40 to 150

-55 to 150

1. During the switching activity the negative peak voltage could reach -1.5 V without any damage for the device.

W

°C

°C

V

V

Symbol

Table 3. Thermal data

Parameter

R thJA

Thermal resistance junction to ambient max.

1. HTSSOP16 package mounted on ST demonstration board.

Table 4. ESD protection

Value

40

(1)

Unit

°C/W

ESD

HBM

CDM

Value

1

250

Unit kV

V

8/52 DocID15324 Rev 4

L5988D Electrical characteristics

V

CC

= 12 V, T

J

= 25 °C unless otherwise specified.

R

R

Symbol

V

CC

DS(on)

DS(on)

VFB

Parameter

Table 5. Electrical characteristic

Test condition

Operating input voltage range

Voltage feedback in regulation

Vout = 0.6 V; Iout = 3 A

HS High side MOSFET on resistance Iout = 1.0 A

LS Low side MOSFET on resistance Iout = 1.0 A

I

L HIGH SIDE

I

L LOW SIDE f

SW f

SW ADJ

D

Maximum peak limiting current I

LIM-ADJ

= float

Maximum valley limiting current I

LIM-ADJ

= float

Switching frequency FSW = floating adjusted switching frequency R

FSW PULL DWN

= 27 k 

Duty cycle

Selectable under voltage lockout (UVLO)

(1)

(1)

Min.

Typ.

Max.

Unit

2.9

75 85

18

95

V m 

111 120 132 m 

62 67 72 m 

92

3.6

100 106 m 

4 4.4

A

4.14

4.6

5.06

A

360

0

400

1000

3.3 V BUS

12 V BUS

Turn ON Vcc threshold

Turn OFF Vcc threshold 2.4

2.7

2.5

Hysteresis 200

Turn ON Vcc threshold

Turn OFF Vcc threshold 6.8

Hysteresis 1

8

7

DC characteristic

I

SS

Soft-start current

V

SS/INH

= 2 V

V

SS/INH

= 0

Device ON level

INH

I q

I q st-by

Device OFF level

Quiescent current

Total stand-by quiescent current

Duty cycle = 0; V

Dynamic characteristic (see

Figure 1 on page 1 )

FB

= 1 V

0.8

22

5

2.9 V < VCC < 18 V

(1)

440

100

2.8

8.6

0.3

3

35

0.595

0.6

0.605

0.592

0.6

0.609

kHz kHz

%

V mA

 A

 A

 A

V

V

V

V

V

V mV

V

Error amplifier

V

OH

V

OL

High level output voltage

Low level output voltage

V

FB

= 0.2 V; SS floating

V

FB

= 1.0 V

3.1

0.1

V

V

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52

Electrical characteristics L5988D

Symbol

Table 5. Electrical characteristic (continued)

Parameter Test condition

(2)

I

O SOURCE

I

O SRCE LIM

I

O SINK

A

V0

Sync function

Source output current

Source current limitation

Sink output current

DC open loop gain

V

FB

= 0.2 V

V

FB

= 0.2 V, V

COMP

= 3 V

V

FB

= 1.0 V, V

COMP

= 0.5 V

(2)

High input voltage

Low input voltage

Slave sink current

Master output amplitude

Output pulse width

Input pulse width

Reference section

V

SYNC

= 3.3 V; FSW = float

I

SOURCE

= 5 mA

SYNCH = floating

V

REF

Reference voltage Vcc = 2.9 V to 18 V

Min.

Typ.

Max.

Unit

25

2

30

100 mA mA mA dB

2.9

2.9

70

1

100

4.0

0.74

V ns ns

V

V mA

(1)

1.756

1.8

1.837

V

1.754

1.8

1.852

V

Line regulation

Vcc = 2.9 V to 18 V

I

REF

= 0 mA

I

REF

= 0 to 5 mA

12

6

7.5

18

12

15

24 mV mV mA

Load regulation

Short circuit current

Protections

V

FB_OVP

Overvoltage trip

(V

FB_OVP

- V

FB

) / V

FB

Bus thresholds

TH1

TH2

TH3

TH4

TH5

– UVLO 3.3 V bus

– OVP not latched

– No sink

– UVLO 3.3 V bus

– OVP not latched

– Sink

– UVLO 3.3 V bus

– OVP latched

– No sink

– UVLO 3.3 V bus

– OVP latched

– Sink

– UVLO 12 V bus

– OVP not latched

– No sink

V

FB rising

(3)

(3)

(3)

(3)

(3)

15

0

0.26

0.48

0.71

0.93

20 24

0.2

0.65

%

V

FB

V

0.425

V

V

0.875

V

1.085

V

10/52 DocID15324 Rev 4

L5988D Electrical characteristics

Symbol

Table 5. Electrical characteristic (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

TH6

TH7

TH8

– UVLO 12 V bus

– OVP not latched

– Sink

– UVLO 12 V bus

– OVP latched

– No sink

– UVLO 12 V bus

– OVP latched

– Sink

(3)

(3)

(3)

1.16

1.385

1.615

1.31

1.525

VREF

1. Specification over the junction temperature range (T statistical correlation.

J

) of -40 to +125 °C are guaranteed by design, characterization and

2. Guaranteed by design.

3. V

CC

= 4 V.

V

V

V

DocID15324 Rev 4 11/52

52

Functional description L5988D

The L5988D is based on a voltage mode control loop. Therefore the duty ratio of the internal switch is obtained through a comparison between a saw-tooth waveform (generated by an

oscillator) and the output voltage of the error amplifier as shown in Figure 3.

The advantage of this technique is the very short conduction time of the power elements thanks to the proper operation of the control loop without a precise current sense, which instead is required in current mode regulators. Thanks to this architecture the L5988D supports extremely low conversion ratio (D = V

OUT

(up to 1 MHz).

/V

IN

) even at very high switching frequency

Figure 3. Voltage mode control loop

-

+ + + +

-

+ +

The main internal blocks are represented in Figure 4.

Figure 4. Internal block diagram

12/52 DocID15324 Rev 4

L5988D Functional description

Below follows a brief description of the main blocks:

 A voltage pre-regulator supplies the internal circuitry. The external 1.8 V voltage reference is supplied by this regulator.

 A voltage monitor circuit that checks the input and internal voltages

 A fully integrated sawtooth oscillator whose frequency is 400 kHz ± 10% when the Fsw pin is floating. Its frequency can be increased/decreased connecting a proper resistor to GND or VREF

 The internal current limitation circuitry monitors the current flowing in both embedded switches to guarantee an effective protection even in extreme duty cycle conditions

 The over voltage protection (OVP) monitors the feedback voltage. If the voltage of this pin overcomes the 20% of the internal reference value (600 mV ± 1%) it will force the conduction of the low side switch until the overshoot is present

 A voltage mode amplifier. The inverting input and the output are externally available for compensation

 A pulse width modulator (PWM) comparator and the relative logic to drive the embedded switches

 The soft-start circuit charges an external capacitor with a constant current equal to

20 µA (typ.). The soft-start feature is realized clamping the output of the error amplifier until the voltage across the capacitor is below 2.7 V

 The circuitry acting on the SYNCH pin provides external signal reference to slave devices when the regulator works as a master or accept the synchronization from an external reference source

 The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and the decoding logic. It recognizes eight different voltage windows of a VREF voltage magnitude for selecting additional features.

 An inhibit block for stand-by operation

 A circuit to realize the thermal protection function

The UOS pin is used to configure the device additional features accordingly to the voltage bias imposed through VREF voltage partitioning.

The selectable options are:

 UVLO level: two pre-defined the under voltage lock out thresholds can be selected to match the 3.3 V and 5 V or 12 V power bus

 SINK capability: this feature is always disabled during the soft-start period to be compatible with pre-biased output voltages. After the soft-start phase, the synchronous rectification can be enabled or not depending on the status of the UOS pin. Anyway, in case an overvoltage is detected, the sink capability is always enabled to bring the FB back to regulation as fast as possible

 OVP management: in case the latched mode is selected and an overvoltage event recurs, the switching activity will be suspended until VCC is reapplied or the SS/INH pin is toggled. Otherwise when the overvoltage transient is ended the regulator will work accordingly to the load request without regulation discontinuity

DocID15324 Rev 4 13/52

52

Functional description L5988D

The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and

the decoding logic. Table 6

shows the internal thresholds of each voltage window composing the VREF magnitude. The voltage biasing of the multifunction can be set accordingly to table

Table 7.

UVLO

Table 6. A/D voltage windows

OVP SINK

1.8 V

1.575 V

1.35 V

1.125 V

0.9 V

0.675 V

0.45 V

0.225 V

0 V

12 V BUS

12 V BUS

12 V BUS

12 V BUS

3.3 V BUS

3.3 V BUS

3.3 V BUS

3.3 V BUS

LATCH

LATCH

NO LATCH

NO LATCH

LATCH

LATCH

NO LATCH

NO LATCH

SINK

NO SINK

SINK

NO SINK

SINK

NO SINK

SINK

NO SINK

R1 (k  )

0

0.68

1.2

2

3.3

6.2

11

N.C.

R2 (k  )

N.C.

2.7

2.7

2.7

2.7

2.7

2.7

0

Table 7. UOS voltage biasing

V

OUS

(V) UVLO

1.8

1.438

1.246

1.034

0.810

0.546

0.355

0

12 V BUS

12 V BUS

12 V BUS

12 V BUS

3.3 V BUS

3.3 V BUS

3.3 V BUS

3.3 V BUS

OVP

LATCH

LATCH

NO LATCH

NO LATCH

LATCH

LATCH

NO LATCH

NO LATCH

SINK

SINK

NO SINK

SINK

NO SINK

SINK

NO SINK

SINK

NO SINK

14/52 DocID15324 Rev 4

L5988D Functional description

5.2 Oscillator synchronization

The generation of the internal saw-tooth waveform is based on the constant current charge / discharge of an internal capacitor. The current generator is designed to get a switching frequency of 400 kHz ± 10% in case the FSW pin is left floating.

The current mirror connected to FSW (see

Figure 5 ) pin acts increasing / decreasing the

value of the internal charging current to adjust the oscillator frequency. Since the internal circuitry forces the FSW voltage bias at 1.235 V, the user can easily source / sink current in this pin connecting a pull up resistor to VREF or a pull down to GND respectively.

Figure 5. Oscillator circuit block diagram

The value of the pull up resistor versus VREF to decrease the oscillator frequency follows the formula:

Equation 1

R

1

 K   =

8.5 10

–

SW



3

KHz 

+ 0.95

In the same way to increase the switching frequency the pull down resistor is selected using the formula:

Equation 2

R

2

 K   =

F

SW



3

KHz  – 400

– 2.1

Table 11 on page 26 shows some resistor values to adjust the oscillator frequency.

DocID15324 Rev 4 15/52

52

Functional description L5988D

R1 (k  )

82

110

150

220

43

47

56

62

Table 8. FSW resistor examples f

SW

(kHz) R2 (k  )

295

322

343

361

198

215

245

261

56

43

33

27

360

180

120

91 f

SW

(kHz)

450

499

548

594

711

801

915

1022

To improve the line transient performance, the voltage feed forward is implemented by

changing the slope of the sawtooth according to the input voltage change (see Figure 6

a).

Figure 6. Sawtooth: voltage feed forward

The slope of the sawtooth does not change if the oscillator frequency is increased by an

external signal or adjusted by the external resistor (see Figure 7

). As a consequence the gain of the PWM stage is a function of the switching frequency and its contribution must be taken in account when performing the calculations of the compensation network (see

Section 6.4.1 on page 29

and

Section 6.4.2 on page 33

).

Figure 7. Sawtooth: synchronization and frequency adjust

16/52 DocID15324 Rev 4

L5988D Functional description

Beating frequency noise is an issue when more than one voltage rail is on the same board.

A simple way to avoid this problem is to operate all the regulators at the same switching frequency. The synchronization feature of a set of L5988D is simply get connecting together their SYNCH pin. The device with highest switching frequency will be the MASTER and provides the synchronization signal to the others. Therefore the SYNCH is a I/O pin to deliver or recognize a frequency signal.

In order to minimize the RMS current flowing through the input filter, the L5988D provides a phase shift of 180° between the master and the SLAVES. In cases where more than two devices are synchronized, all slaves will have a common 180° phase shift with respect to the master.

In case the synchronized set shares a switching frequency different to the nominal 400 kHz, it is suggested to provide the proper FSW resistor to each device. In this way all the devices will have a common peak amplitude of the internal sawtooth signal so the same oscillator gain in the open loop gain transfer function. In this way the same compensation network is valid for all the devices.

Taking in account the case of two synchronized L5988D regulating the same output voltage, the RMS current in the input filter will be optimized and will observe the following formula:

Equation 3

I

RMS

=





I

OUT

2

 2D   –









I

OUT

  2D 1   



–

if D < 0.5

 if D > 0.5

Multiple regulators can be also synchronized to an external frequency signal fed to the

SYNCH pin. In this case the set is phased to the reference and all the devices will work with

0° phase shift.

The graphical representation of the input RMS current of the input filter in the case of two devices with 0° phase shift (synchronized to an external signal) or 180° phase shift

(synchronized connecting their SYNCH pins) regulating the same output voltage is provided in

Figure 8.

To dimension the proper input capacitor please refer to Section 6.1 on page 25

.

DocID15324 Rev 4 17/52

52

Functional description

Figure 8. Input RMS current of two synchronized regulators

L5988D

5.3 External voltage reference

An external 1.8 V regulated voltage is provided. This reference is useful to set the voltage at the multifunction pin (see

Section 5.1 on page 13 ) or to source current to ILIM-ADJ and

FSW pins (see Section 5.2

and

Section 5.5.2

). The typical current capability is 4 mA.

5.4 Soft-start

When VCC is above the selected UVLO threshold the start-up phase takes place. At startup, a voltage ramp is generated charging the external capacitor C

SS

with an internal current generator. The device is in inhibit mode as long as SS/ INH pin is below the INH threshold.

The L5988D implements the soft-start phase by clamping the output of the error amplifier and, being based on a voltage mode control, the duty cycle. In fact the comparison between the output of the error amplifier and the internal saw tooth waveform generates the duty cycle needed to keep the output voltage in regulation.

Two different current sources charge the external capacitor depending on the pin voltage in order to reduce the power consumption in INH mode.

Equation 4

I

SS

=





I

SS1

I

SS2

= 5  

SS/INH

= 2 2  

SS/INH





1

2.9

The equation for the soft-start time is:

Equation 5

T

SS

=  T

1

+  T

2

=

I

C

----------  1 0

SS1

 +

I

C

----------  2.9 1

SS2



18/52 DocID15324 Rev 4

L5988D Functional description

Considering I

SS2 follows:

/I

SS1

= 22/5 = 4.4, the proper soft-start capacitor is simply calculated as

Equation 6

C nF  =    3.5

During the soft-start phase (V

SS

< 2.9 V):

 the sink capability is always disabled (independently from the multifunction pin settings) to be compatible with pre-biased output voltage

 in case the overcurrent limit is detected, a constant current protection is provided in

order to deliver extra current for charging the output capacitor (see Section 5.5.2

for

description of current protection management).

During normal operation the C

SS is discharged with a constant current of 22  A (typ.) only if:

 HICCUP mode is triggered (see

Section 5.5.2

)

 the input voltage goes below the UVLO threshold (see

Section 5.5.3

)

 the internal temperature is over 150°C (see

Section 5.5.4

)

A new SS cycle will start when the V

SS

drops below the INH threshold.

New high performance ICs often require more than one supply voltage. Most of these applications require well defined start-up sequencing, in order to avoid potential damage and latch-up of the processing core. Sharing the same soft-start capacitor for a set of regulators, the output voltages increase with the same slew rate implementing a “simultaneous start-up” sequencing method.

5.5 Monitoring protections

5.5.1 Overvoltage

The device provides the overvoltage protection monitoring the output voltage through the

FB pin. If the voltage sensed on FB pin reaches a value 20% (typ.) greater than the reference of the error amplifier, the low-side MOSFET is turned on to discharge as fast as possible the output capacitor. It is possible to set two different behaviors in case of OVP:

 In case the OVP latched mode is active (see

Section 5.1 on page 13 ), the internal

oscillator is suspended and the low side switch will be kept on until the input voltage goes below the selected UVLO threshold or the SS/ INH pin is forced below the INH threshold.

 In case of NOT latched OVP mode is active, the low side MOS is forced ON until the feedback voltage is higher than the OVP threshold (20% greater than the reference of the error amplifier).

DocID15324 Rev 4 19/52

52

Functional description

Figure 9. OVP not latched

L5988D

Figure 10. OVP latched

20/52 DocID15324 Rev 4

L5988D Functional description

The current limiting feature acts in different ways depending on the operative conditions.

 In case an overcurrent detection happens after the soft-start phase, the internal logic will trigger the “HICCUP” mode. Both switches are turned off and the soft-start capacitor is discharged with a constant current of 22  A (typ.). When the SS/ INH voltage drops below the INH threshold a new SS cycle will start.

 During the soft-start phase the overcurrent information is used to provide a constant current protection. In this way additional current is available to charge the output capacitor during power up.

The most common way is to sense the current flowing through the power MOSFETs.

However, due to the noise created by the switching activity of the power MOSFETs, the current sense is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. For this reason, the current cannot be sensed through the high-side

MOSFET in the case of extremely low duty cycles, nor through the low-side MOSFET in the case of very high duty cycles.

The L5988D assures the effective protection sensing the current flowing in both embedded switches. The protection achieved by sensing the current in the high-side MOSFET is called

“peak overcurrent protection”, while the protection achieved by sensing the current in the low-side MOSFET is called “valley overcurrent protection”. When the current limit is reached during normal operation, the so called HICCUP mode is triggered, and the soft-start cap is discharged and recharged. However, during the start-up phase, additional current is required to charge the output capacitor. This could continuously trigger the HICCUP intervention preventing the system from reaching a steady working condition. For this reason the HICCUP feature is disabled during the start-up phase and a constant current mode is active to charge the output capacitor. In this case, when the peak current limit is triggered after a conduction time equal to the “masking time”, the high-side MOSFET is turned off and the low side MOSFET is kept on until the flowing current goes below the

“valley” current limit. If necessary, some switching pulses are skipped, as illustrated in

Figure 11

. Thus, the combination of the “peak” and “valley” current limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions. The current threshold of the low side is designed higher than the high side one to guarantee the proper protection.

The constant current mode during the soft-start phase limits the maximum current up to:

Equation 7

I

MAX

= I

VALLEY_TH

+

V

IN

–

L

V

 T

MASK

The overcurrent limit protection is adjustable (higher or lower than the nominal value) through an external resistor. To guarantee effective protection, both thresholds (valley and peak) are in tracking.

DocID15324 Rev 4 21/52

52

Functional description L5988D

The typical active thresholds in case of ILIM-ADJ pin left floating are I

PEAK_TH

I

VALLEY_TH peak (and valley) thresholds follows the formula:

= 4.0 A,

= 4.7 A. The dimensioning of the pull up resistor versus VREF to decrease the

Equation 8

R

9

=

 10

5

PEAK_TH

In the same way the pull down resistor is selected using the following formula to increase the maximum current thresholds:

Equation 9

R

3

=

I

PEAK_TH

10

–

5

4.0

Figure 11. Constant current protection at extreme duty cycles

22/52 DocID15324 Rev 4

L5988D Functional description

R9(k  )

68

91

120

200

560

43

47

56

Table 9

shows some resistor values to adjust the current limits

I

LIM PEAK

(A)

Table 9. ILIM-ADJ resistor examples

I

LIM VALLEY

(A) R3(k  ) I

LIM PEAK

(A)

1.24

1.62

1500 4.2

1.47

1.88

2.26

2.71

3.03

3.43

3.81

1.87

2.31

2.71

3.18

3.52

3.94

4.35

750

470

330

270

220

180

160

4.38

4.6

4.8

5.0

5.20

5.50

5.70

I

LIM VALLEY

(A)

4.75

4.95

5.18

5.42

5.62

5.82

6.12

6.30

5.5.3 UVLO

The under-voltage-lockout (UVLO) is adjustable by the multifunction pin (see

Section 5.1 on page 13 ). It is possible to set two different thresholds:

 2.9 V for 3.3 V BUS

 8 V for 12 V BUS

5.6

When the junction temperature reaches 150 °C the device enters in thermal shutdown. Both

MOSFETs are turned off and the soft-start capacitor is discharged with a current of 22 µA.

The device doesn’t restart until the junction temperature goes down to 120 °C.

Minimum on time

The L5988D is based on a voltage mode control loop. The advantage of this technique is the very short conduction time of the power elements thanks to the proper functioning of the control loop without a current sense (that is challenging with low conduction times), which instead is required in current mode regulators. The optimized architecture, the design solutions and the high performance fabrication technique allow power elements to achieve extremely short conduction times. This allows very high switching frequency operation even

in very low duty cycle applications. Figure 12

shows how the L5988D can easily manage a minimum conduction time of 200ns. Moreover, thanks to the embedded P-MOS used for the high-side, no bootstrap capacitor is required. This means that the device is able to manage a duty cycle of 100%.

DocID15324 Rev 4 23/52

52

Functional description

Figure 12. Minimum T

ON

L5988D

24/52

The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance.

The uncompensated error amplifier characteristics are the following:

Table 10. Uncompensated error amplifier

Parameter description Value

Low frequency gain

GBWP

Slew rate

Output voltage swing

Maximum source/sink current

100 dB

4.5 MHz

7 V/  s

0 to 3.3 V

25 mA / 40 mA

In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type

III compensation network has to be used (see Section 6.4 on page 28

for details about the compensation network selection).

Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin.

DocID15324 Rev 4

L5988D Application information

6.1 Input capacitor selection

The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.

So the input capacitor must have a RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 10

I

RMS

= I

O

 D –

2

+

D

2

-------



2

Where Io is the maximum DC output current, D is the duty cycles,   is the efficiency. This function has a maximum at D = 0.5 and, considering  = 1, it is equal to Io/2.

In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as:

Equation 11

D

MAX

=

V

INMIN

+

V

OUT

 V

+  V

LOW_SIDE

LOW_SIDE

–  V

HIGH_SIDE and

Equation 12

D

MIN

=

V

INMAX

V

+

OUT

 V

+  V

LOW_SIDE

LOW_SIDE

–  V

HIGH_SIDE

Where



V

HIGH_SIDE and



V

LOW_SIDE are the voltage drops across the embedded switches.

The peak to peak voltage across the input filter can be calculated as:

Equation 13

V

PP

=

C

IN

I



O f

SW







1 – ----





 D +

D



  1 D  +

O

Given a physical dimension, ceramic capacitors can met well the requirements of the input filter substaining an higher input current than electrolytic / tantalum types. In this case the equation of C

IN

as a function of the target V

PP

can be written as follows:

Equation 14

C

IN

=

V

PP

I

O

 f

SW







1 – ----





 D +

D



  1 D 

DocID15324 Rev 4 25/52

52

Application information L5988D

Considering  this function has its maximum in D = 0.5:

Equation 15

C

IN_MIN

=

I

O

2 V

PP_MAX f

SW

Typically C

IN

is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 1% V

IN_MAX .

Manufacture

MURATA

TDK

Table 11. Input capacitors

Series Cap value (  F)

GRM31

GRM55

C3225

10

10

10

Rated voltage (V)

25

25

25

26/52

The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple has to be selected.

The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.

The inductance value can be calculated by the following equation:

Equation 16

 I

L

=

V

IN

–

L

V

OUT  T

ON

=

V

L

 T

OFF

Where T

ON and T

OFF

are the on and off time of the internal power switch. The maximum current ripple, at fixed Vout, is obtained at maximum T

OFF

that is at minimum duty cycle (see previous section to calculate minimum duty). So fixing  I

L

= 20% to 40% of the maximum output current, the minimum inductance value can be calculated:

Equation 17

L

MIN

=

V

OUT

 I

+

----------------------------

MAX

V

F



1 D

F

MIN

SW where F

SW

is the switching frequency 1/(T

ON

+ T

OFF

).

For example for V

OUT

= 3.3 V, V

IN inductance value to have  I

L

= 12 V, I

= 30% of I

O

O

= 4 A and F

is about 4.7 µH.

SW

= 400 kHz the minimum

The peak current through the inductor is given by:

Equation 18

I = I

O

+

 I

2

So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit.

DocID15324 Rev 4

L5988D Application information

In

Table 12

some inductor part numbers are listed.

Manufacturer

Coilcraft

Wurth

Coiltronics

BI

SUMIDA

Table 12. Inductors

Series Inductor value (  H) Saturation current (A)

XPL7030

MSS1048

MSS1260

WE-HC/HCA

WE-TPC type XLH

WE-PD type L

DR74

DR125

HM78-60

HM78-60

2.2 to 4.7

2.2 to 6.8

10

3.3 to 4.7

3.6 to 6.2

10

3.3 to 4.7

10

4.7 to 10

4.7 to 10

6.8 to 10.5

4.14 to 6.62

5.5

7 to 11

4.5 to 6.4

5.6

4.3 to 5.4

5.3

5.4 to 6.8

5.4 to 6.8

6.3 Output capacitor selection

The current in the capacitor has a triangular waveform (with zero average value) which generates a voltage ripple across it. This ripple is due to the capacitive component and the resistive component (ESR). So the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements.

The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection.

Equation 19

 V

OUT

= ESR   I

MAX

+

 I

MAX



OUT



SW

Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR value.

The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In

Section 6.4

, it will be illustrated how to consider its effect in the

system stability.

For example with V

OUT order to have a  V

OUT

= 3.3 V, V

= 0.01·V

IN

OUT

= 12 V,  I

L

= 0.6 A (resulting by the inductor value), in

, if the multi layer capacitor are adopted, 10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So 100 µF with ESR = 40 m  is compliant with the requested output voltage ripple 

The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application the output capacitor and system bandwidth

DocID15324 Rev 4 27/52

52

Application information L5988D have to be chosen in order to sustain load transient and to have a fast response to the transient.

In

Table 13

some capacitor series are listed.

Manufacturer

MURATA

PANASONIC

SANYO

TDK

Series

Table 13. Output capacitors

Cap value (  F) Rated voltage (V)

GRM32

GRM31

ECJ

EEFCD

TPA/B/C

C3225

22 to 100

10 to 47

10 to 22

10 to 68

100 to 470

22 to 100

6.3 to 25

6.3 to 25

6.3

6.3

4 to 16

6.3

ESR (m  )

< 5

< 5

< 5

15 to 55

40 to 80

< 5

28/52

The compensation network has to assure stability and good dynamic performance. The loop of the L5988D is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So selecting the compensation network the E/A will be considered as ideal, that is, its bandwidth is much larger than the system one.

The transfer functions of PWM modulator and the output LC filter are studied. The transfer function PWM modulator, from the error amplifier output (COMP pin) to the OUT pin, results:

Equation 20

G

PW0

 f

SW0

 =

V

V s

 

SW0

 where V

S is the sawtooth amplitude and H represent its reliance on the switching frequency.

As seen in

Section 5.2 on page 15 , the voltage feed forward generates a sawtooth

amplitude directly proportional to the input voltage, that is:

Equation 21

V

S

 f

SW0

 = K V

IN

 

SW0



The internal saw tooth is designed in order to have the maximum amplitude at the natural switching frequency of the device.

At f

SW0

= 400 kHz the PWM modulator can be written as:

Equation 22

G

PW0

 400 kHz  =

K

=

V

S



V

IN

400 kHz 

= 9

The synchronization of the device with an external clock fed into the SYNCH pin and the adjustment of the switching frequency through the FSW pin modify the gain of the internal

saw tooth (see Section 5.2 on page 15

).

DocID15324 Rev 4

L5988D

6.4.1

Application information

The PWM modulator gain is a function of the switching frequency:

Equation 23

G

PW0

 f

SW

 = G

PW0

 400 kHz   f

SW

 kHz

400



= 9  f

SW

 kHz

400



The transfer function on the LC filter is given by:

Equation 24

G

LC

=

1 +

2  f s

1 +

 s

2  Q f

LC

+





2  s f

LC





2 where:

Equation 25 f

LC

=

2   L C

OUT

 1 +

R

OUT

 f zESR

=

2 

1



OUT

Equation 26

Q =

R  

OUT

OUT

 R

  R

OUT

OUT



+

E SR

ESR 

, R

OUT

=

V

OUT

OUT

Two different kinds of networks can compensate the loop depending on the output capacitor.

Type II network is used to compensate the loop with high ESR output capacitors, type III with low ESR output capacitors (MLCC). In the two following paragraph the guidelines to select the Type II and Type III compensation network are illustrated.

Type III compensation network

The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero dB frequency.

In Figure 13 the type III compensation network is shown. This network introduces two zeros

(f

Z1

, f

Z2

) and three poles (f

P0

, f

P1

, f

P2

). They expression are:

Equation 27 f

Z1

=

2   C

7



1

 R

8

R

7



 f

Z2

=



5



5

Equation 28 f

P0

= 0  f

P1

=

2   R

7

 C

7

 f

P2

=

2   R

5



C 

C

5

+

C

6

C

6

DocID15324 Rev 4 29/52

52

Application information

Figure 13. Type III compensation network

L5988D

In

Figure 14 the Bode diagram of the PWM and LC filter transfer function [G

PW0 and the open loop gain [G

LOOP

(f) = G

PW0

· G

LC

(f) · G

TYPEIII

(f)] are drawn.

· G

LC

(f)]

Figure 14. Open loop gain: module bode diagram

30/52 DocID15324 Rev 4

L5988D Application information

The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow:

1.

Choose a value for R

1

, usually between 1 k  and 5 k  .

2. Choose a gain (R

5

/R

8

) in order to have the required bandwidth (BW), that means:

Equation 29

R

5

= f

LC

1

R

8 where K is the feed forward constant and 1/K is equals to 18.

5

by placing the zero at 50% of the output filter double pole frequency (f

LC

):

Equation 30

C

5

=

  R

5

 f

LC

6

by placing the second pole at four times the system bandwidth (BW):

Equation 31

C

6

=

2   R

5

 C

C

5

5

 – 1

5. Set also the fist pole at four times the system bandwidth and also the second zero at the output filter double pole:

Equation 32

R

7

=

R

--------------------------

-----------------

LC

– 1

C

7

=

2   R

7

4 BW

The suggested maximum system bandwidth is equals to the switching frequency divided by

3.5 (F

SW

/3.5), anyway lower than 120 kHz if the F

SW

is set higher than 500kHz.

For example with V

OUT

= 1.2 V, V

IN

= 12 V, I

O compensation network is:

= 4 A, L = 4.7  H, C

OUT

= 47  F, the type III

Equation 33

R

8

= 4.7k

  R

6

= 4.7k

  R

7

= 56   R

5

= 1.2K

  C

7

= 10nF  C

5

= 22nF  C

6

= 1nF

DocID15324 Rev 4 31/52

52

Application information L5988D

In

Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about

68 kHz and the phase margin is 50°.

Figure 15. Open loop gain bode diagram with ceramic output capacitor

32/52 DocID15324 Rev 4

L5988D Application information

In

Figure 16 the type II network is shown.

Figure 16. Type II compensation network

The singularities of the network are:

Equation 34 f

Z1

=

2  

1

R

5

 C

5

 f

P0

= 0  f

P1

=

2   R

5



C

5

C

5



+

C

C

6

In

Figure 17 the bode diagram of the PWM and LC filter transfer function (G

PW0 and the open loop gain (G

LOOP

(f) = G

PW0

· G

LC

(f) · G

TYPEII

(f)) are drawn.

· G

LC

(f))

Figure 17. Open loop gain: module bode diagram

DocID15324 Rev 4 33/52

52

Application information L5988D

The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow:

1.

Choose a value for R

8

, usually between 1k and 5k, in order to have values of C5 and

C6 not comparable with parasitic capacitance of the board.

2. Choose a gain (R

5

/R

8

) in order to have the required bandwidth (BW), that means:

Equation 35

R

5

=



 f

------------

LC





2

 f

ESR



V

V

IN

 R

8

Where f

ESR

is the ESR zero:

Equation 36 f

ESR

=

2  

1



OUT and V

S

is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant.

5

by placing the zero one decade below the output filter double pole:

Equation 37

C

5

=

2  

10

R

5



LC

7

in order to place the second pole at four times the system bandwidth

(BW):

Equation 38

C

7

=

2   R

5

 C

C

5

5

 – 1

For example with V

OUT

= 1.2V, V

IN

= 12 V, I

O

= 4 A, L = 4.7  H, C

ESR = 35 m  the type II compensation network is:

OUT

= 330  F,

Equation 39

R

8

= 4.7k

  R

6

= 4.7K

  R

5

= 22k   C

5

= 2.2nF

 C

6

= 33pF

34/52 DocID15324 Rev 4

L5988D Application information

In

Figure 18 is shown the module and phase of the open loop gain. The bandwidth is about

42 kHz and the phase margin is 56°.

Figure 18. Open loop gain bode diagram with high ESR output capacitor

The response of the system to a load transition in terms of output voltage regulation is affected not only by the designed compensation network but it also rely on the selection of the power components (the inductor value, for example, limits the slew rate of the current).

DocID15324 Rev 4 35/52

52

Application information L5988D

Some measurements of the output regulation during load transient for the examples

provided in Section 6.8 on page 43

are provided at the end of this document.

6.5 R.M.S. current of the embedded power MOSFETs

The L5988D integrates both the power elements (high side and low side) and so the power dissipation is often the bottleneck for the output current capability (refer to

Section 6.6

for

the estimation of the operating temperature).

Nevertheless, as mentioned in

Section 1: Description on page 6

the device can manage a continuous output current of 4 A in most of the application conditions.

However the rated continuous current is 5 A and the rated RMS current of the power elements is 4.5 A, where:

Equation 40

I

RMS HS

= I

LOAD

 D

Equation 41

I

RMS LS

= I

LOAD

 and the duty cycle D:

Equation 42

D =

V

V

IN

OUT

+ 

+  R

R

DS ON LS

– R

+ DCR 

DS ON HS

 I



LOAD

 I

LOAD

Fixing the limit of 4.5 A for I

RMS HS as illustrated in

Figure 19

.

and I

RMS LS

the maximum output current can be derived,

36/52 DocID15324 Rev 4

L5988D Application information

Figure 19. Maximum continuous output current vs. duty cycle

The thermal design is important to prevent the thermal shutdown of the device if the junction temperature goes above 150 °C. The three different sources of losses within the device are: a) conduction losses due to the not negligible R

DSON equal to:

of the power switch; these are

Equation 43

P

ON

= R

DSON_HS

  I

OUT



2

 +

DSON_LS

  I

OUT



2

  1 D 

Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between V

OUT

an V

IN

, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case.

b) switching losses due to power MOSFET turn ON and OFF; these can be calculated as:

Equation 44

P

SW

= V

IN

 I

OUT



 T +

2

T

FALL



 Fsw = V

IN

 I

OUT

 T

SW

 F

SW

Where T

RISE and T

FALL

represent the switching times of the power element that cause the switching losses when driving an inductive load (see switching time.

Figure 20 ). T

SW

is the equivalent

DocID15324 Rev 4 37/52

52

Application information

Figure 20. Switching losses

L5988D

38/52

Equation 45

P

Q

= V

IN

 I

Q where I

Q

is the quiescent current.

The junction temperature T

J

can be calculated as:

Equation 46

T

J

= T

A

+ Rth

JA

 P

TOT

Where T

A

is the ambient temperature and P

TOT

is the sum of the power losses just seen.

R thJA

is the equivalent static thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient.

For this device the path through the exposed pad is the one conducting the largest amount of heat. The static Rth

JA

measured on the application is about 40 °/W.

The thermal impedance of the system, considered as the device in HTSSOP16 package soldered on the application board, takes on an important rule when the maximum output power is limited by the static thermal performance and not by the electrical performance of the device. Therefore the embedded power elements could manage an higher current but the system is already taking away the maximum power generated by the internal losses.

In case the output power increases the thermal shutdown will be triggered because the junction temperature triggers the designed thermal shutdown threshold.

The R

TH

is a static parameter of the package: it sets the maximum power loss which can be generated from the system given the operation conditions.

DocID15324 Rev 4

L5988D Application information

If we suppose, as an example, T

A

= 40  C, 140 before triggering the thermal shutdown and R

TH

 C is the maximum operating temperature

= 40  C/W so the maximum power loss achievable with the thermal performance of the system will be:

Equation 47

P

MAX DC

=

 T

R

TH

=

T

R

–

TH

T

-------------------------------------=

100

40

= 2.5W

f

The switching, conduction and quiescent losses in case of V

IN

= 12 V, V

OUT

= 1.2 V,

SW

= 400 kHz are plotted in

Figure 21.

The calculations are performed considering the typical R

(R details).

DS(on)

DS_ON HS

of the power element for a junction temperature of 125  C

= 120 m  , R

DS_ON LS

= 83 m 

; see Section 3: Maximum ratings on page 8 for

Figure 21. Estimation of the internal power losses (V

IN

= 12 V, V

OUT

= 1.2 V, f

SW

= 400 kHz)

The red trace represents the maximum power which can be taken away as calculated above, whilst the purple trace is the total internal losses.

As a consequence, given these operating conditions, the system can manage a continuous output current up to 4.2 A. The device could deliver a continuous output current up to 5 A to the load (see

Section 6.5

), however the maximum power loss of 2.5 W is reached with an

output current of 4.2 A, so the maximum output power is derated.

The calculation of the internal power losses must be done for each specific operating condition given by the final application.

For example, the result showed in

Figure 21.

is not valid in case the V

IN

is equal to 5 V instead of 12 V: the lower contribution of the switching losses, which are proportional to the input voltage, increases the maximum output current from 4.2 A to 4.5 A (see

Figure 22.

).

DocID15324 Rev 4 39/52

52

Application information L5988D

Figure 22. Estimation of the internal power losses (V

IN f

SW

= 400 kHz)

= 5 V, V

OUT

= 1.2 V,

40/52

In applications where the current to the output is pulsed, the thermal impedance should be considered instead of the thermal resistance. Also, in these conditions, the current

limitations described in Section 6.5 on page 36

are no more valid since they are related to continuous output current delivery.

The thermal impedance of the system could be much lower than the thermal resistance, which is a static parameter. As a consequence the maximum power losses can be higher than 2.5 W if a pulsed output power is requested from the load:

Equation 48

P

MAX

=

 T

TH t

=

T

Z

–

TH

T t

AMB

So, depending on the pulse duration and its frequency, the maximum output current (even more than 5 A) can be delivered to the load.

The characterization of the thermal impedance is strictly dependent on the layout of the

board. In Figure 23.

the measurement of the thermal impedance of the evaluation board of

the L5988D is provided.

DocID15324 Rev 4

L5988D Application information

Figure 23. Measurement of the thermal impedance of the evaluation board

As it can be see, for example, for load pulses with duration of 1 second, the actual thermal impedance is lower than 20  C/W. This means that, for short pulses, a current higher that

5 A (provided the current limitation is set correctly) can be managed.

The PC board layout of switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops. The L5988D is a monolithic device so most of the critical path are designed internally minimizing the potential issues introduced by the board layout.

In the operation of a step down converter two high current loops become evident and critical. The conduction of the high side switch highlight a current loop composed by the input capacitor, the inductor and the output capacitor whilst during the conduction of the low side switch the current flows from the power ground to the inductor and again the output capacitor.

The first consideration is to keep the trace of the switching node as short as possible to reduce radiated emission.

The bandwidth of the external power supply is limited if compared to the switching frequency of the device so the power supply delivers a certain RMS current in the switching period. As a consequence the input filter substains the input voltage during the conduction time of the HS switch delivering an impulsive extra current equal to I

LOAD

+ I

RIPPLE

- I

IN RMS and it is recharged during the conduction time of the low side by the external power supply.

The golden rule is to reduce as much as possible the stray inductance of the path related to the capacitor and V

IN

to reduce injected noise: the suggested layout (see Figure 24 and

DocID15324 Rev 4 41/52

52

Application information L5988D

Figure 25

) solves this matter placing the input filter just above the package of the device to minimize noise. This placement offers the best filtering for the device and minimize the noise injected by the pulsing current path. The additional stray inductance introduced in the path from the switching node and the external inductor is not critical for the operation of the device.

The pin 4 of the L5988D supplies most of the analog circuitry and MOSFET drivers so an

RMS current of few mA flows in its trace. A decoupling path between the power and signal input reduces the issues induced by the switching noise: an RC network is helpful to filter the signal supply from the noise generated by the switching activity and it becomes effective when its time constant is bigger than two or three switching cycles. The pin 4 supplies the drivers of the embedded MOSFET so the R value has to be kept limited to avoid voltage spikes during the operation of the embedded driver (the maximum value is in the order of few ohms).

The inductor current flows from power GND to the output capacitor during the conduction time of the LS switch: the power ground plane and the signal ground are kept partitioned in the PCB layout to minimize the injected noise on the signal ground. They are connected together below the ground of the output capacitor which is the less noisy power component.

The connection of the external resistor divider to the feedback pin (FB) is an high impedance node, so the interferences can be minimized placing the routing of feedback node as far as possible from the high current paths. To reduce the pick up noise the resistor divider has to be placed very close to the device.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion.

Figure 24. Top board layout

42/52 DocID15324 Rev 4

L5988D

Figure 25. Bottom board layout

Application information

In

Figure 26 is shown the demonstration board application circuit working.

The operating switching frequency is 400 kHz. The designed system bandwidth is 68 kHz with a the phase margin of 50  . The peak current limitation is set 5.2 A, the valley current limitation 5.8 A in order to deliver up to 4 A DC to the load.

Figure 26. Demonstration board application circuit (f

SW

= 400 kHz)

DocID15324 Rev 4 43/52

52

Application information L5988D

Reference

R3

R5

R6

R7

R8

L1

R1

R2

R12

U1

C3

C5

C6

C7

C1

C10

C2A

C8

Table 14. Component list application circuit (f

SW

= 400 kHz)

Part number Description Manufacturer

GRM32ER61E226KE15

GRM188R71E105KA12

GRM32ER61C476KE15

744 311 470

Chip capacitor 22 µF 25 V

Chip capacitor 1µF 25 V

Chip capacitor 47 µF 16 V

Chip capacitor 1 µF

Chip capacitor 330 nF

Chip capacitor 22 nF

Chip capacitor 1 nF

Chip capacitor 10 nF

Inductor 4.7 µH

Chip resistor 12 k  ± 1%

Chip resistor 3.3 k  ± 1%

Chip resistor 220 k  ± 1%

Chip resistor 1.2 k  ± 1%

Chip resistor 4.7 k  ± 1%

Chip resistor 56  ± 1%

Chip resistor 4.7 k  ± 1%

Chip resistor 5.6 R ± 1%

I.C. L5988D

Murata

Murata

Wurth elektronik

STMicroelectronics

In

Figure 27 is shown an additional application example where the L5988D operates at

a switching of 600 kHz. The designed system bandwidth is 73 kHz with a the phase margin of 51  . The peak current limitation is set 5.2 A, the valley current limitation 5.8 A in order to deliver up to 4 A DC to the load.

44/52 DocID15324 Rev 4

L5988D Application information

Figure 27. Demonstration board application circuit (f

SW

= 600 kHz)

Reference

R4

R5

R6

R7

L1

R1

R2

R3

C3

C5

C6

C7

C1

C10

C2A

C8

R8

R12

U1

Table 15. Component list application circuit (f

SW

= 600 kHz)

Part number Description Manufacturer

GRM32ER61E226KE15

GRM188R71E105KA12

GRM32ER61C476KE15

744 311 330

Chip capacitor 22 µF 25 V

Chip capacitor 1 µF 25 V

Chip capacitor 47 µF 16 V

Chip capacitor 2.2 µF

Chip capacitor 330 nF

Chip capacitor 22 nF

Chip capacitor 1 nF

Chip capacitor 10 nF

Inductor 3.3 µH

Chip resistor 12 k  ±1%

Chip resistor 3.3 k  ±1%

Chip resistor 220 k  ±1%

Chip resistor 82 k  ±1%

Chip resistor 560  ±1%

Chip resistor 1.1 k  ±1%

Chip resistor 68  ± 1%

Chip resistor 4.99 k  ±1%

Chip resistor 5.6  ±1%

I.C. L5988D

Murata

Murata

Wurth elektronik

STMicroelectronics

DocID15324 Rev 4 45/52

52

Typical characteristics L5988D

Figure 28. Junction temperature vs. f

SW at V

IN

= 12 V, V

OUT

= 3.3 V

Figure 29. Junction temperature vs.

at V

IN

= 5 V, V

OUT

= 3.3 V f

SW

Figure 30. Junction temperature vs. f

SW at V

IN

= 3.3 V, V

OUT

= 1.2 V

Figure 31. Junction temperature vs. V

OUT at V

IN

= 12 V, f

SW

= 400 kHz

46/52 DocID15324 Rev 4

L5988D Typical characteristics

Figure 32. Junction temperature vs. V

OUT at V

IN

= 5 V, f

SW

= 400 kHz

Figure 33. Junction temperature vs. V

OUT at V

IN

= 3.3 V, f

SW

= 400 kHz

Figure 34. Efficiency vs. output current at V

IN

= 3.3 V, f

SW

= 400 kHz

98.00

93.00

88.00

83.00

V

IN

= 3.3v f

SW

= 400 kHz

78.00

73.00

VIN=3.3 VOUT=1.2 250 kHz

VIN=3.3 VOUT=1.5 250 kHz

VIN=3.3 VOUT=1.8 250 kHz

VIN=3.3 VOUT=2.5 250 kHz 68.00

63.00

0.2

0.6

1.0

1.4

1.8

2.2

I

LOAD

(A)

2.6

3.0

3.4

3.8

Figure 35. Efficiency vs. output current at V

IN

= 5 V, f

SW

= 250 kHz

V

IN

= 5v f

SW

= 250 kHz

95.00

90.00

85.00

80.00

75.00

70.00

VIN=5 VOUT=1.2 250 kHz

VIN=5 VOUT=1.5 250 kHz

VIN=5 VOUT=1.8 250 kHz

VIN=5 VOUT=2.5 250 kHz

VIN=5 VOUT=3.3 250 kHz

65.00

0.2

0.6

1.0

1.4

1.8

2.2

I

LOAD

(A)

2.6

3.0

3.4

3.8

DocID15324 Rev 4 47/52

52

Typical characteristics L5988D

Figure 36. Efficiency vs. output current

95.00

90.00

85.00

80.00

V

IN

= 12v f

SW

= 250 kHz

75.00

70.00

65.00

VIN=12 VOUT=1.2 250 kHz

VIN=12 VOUT=1.5 250 kHz

VIN=12 VOUT=1.8 250 kHz

VIN=12 VOUT=2.5 250 kHz

VIN=12 VOUT=3.3 250 kHz

VIN=12 VOUT=5.0 250 kHz

60.00

0.2

0.6

1.0

1.4

1.8

2.2

I

LOAD

(A)

2.6

3.0

3.4

3.8

Figure 38. Line regulation

3.36

3.355

3.35

3.345

3.34

3.335

η (%) 3.33

3.325

3.32

3.315

3.31

3.305

3.3

3.5

5.5

L5988D LINE REGULATION (L = 4.7

μ H)

7.5

L5988D_3.3v_400k

9.5

11.5

I

LOAD

(A)

13.5

15.5

17.5

Figure 40. Soft-start fsw=400 kHz

3.36

3.355

3.35

3.345

3.34

3.335

η (%) 3.33

3.325

3.32

3.315

3.31

3.305

3.3

0

Figure 37. Load regulation

L5988D LOAD REGULATION (V

IN

12V - L = 4.7

μ H)

0.5

1

L5988D_3.3v_400k_AFP]

1.5

2

I

LOAD

(A)

2.5

3 3.5

4

Figure 39. Load transient from 0 to 3 A

100mV/div fsw=600 kHz

Cout=47uF

SR = 2.5A/us

48/52 DocID15324 Rev 4

L5988D Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK ® is an ST trademark.

HTSSOP16 package information

Figure 41. HTSSOP16 package outline

DocID15324 Rev 4 49/52

52

Package information L5988D

Table 16. HTSSOP16 package mechanical data

Dimensions (mm)

Symbol

Min. Typ. Max.

A 1.20

A1 0.15

A2 0.80

1.00

1.05

b 0.19

c 0.09

D 4.90

D1 2.8

E 6.20

E1 4.30

E2 2.8

3 e 0.65

5.00

3

6.40

4.40

0.30

0.20

5.10

3.2

6.60

4.50

3.2

L 0.45

0.60

L1 1.00

0.75

k 0.00

8.00

aaa 0.10

50/52 DocID15324 Rev 4

L5988D Order codes

Order codes

L5988D

L5988DTR

Table 17. Order codes

Package

HTSSOP16

Packaging

Tube tape and reel

Date

20-Jan-2009

24-Sep-2009

18-Jan-2010

02-Apr-2015

Revision

Table 18. Document revision history

Changes

1

2

3

4

Initial release

Updated: coverpage,

Table 5 on page 9

Updated: Section 5.2 on page 15 ,

Section 6.4 on page 28 and

Table 14 on page 44

Added

Table 4 on page 8 .

Added titles to equations throughout document.

Added/updated/removed cross-references throughout document.

Updated

Table 10 on page 24 (added header).

Updated Section 8: Package information on page 49 (updated/added

titles, headers, reformatted section).

Updated

Table 17 on page 51 (updated package name).

Minor modifications throughout document.

DocID15324 Rev 4 51/52

52

L5988D

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2015 STMicroelectronics – All rights reserved

52/52 DocID15324 Rev 4