Arm ® Cortex ® -M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (up to 128 Kbytes of Flash memory and 16 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (two I 2 Cs, two SPI/I 2 S, one HDMI CEC and four USARTs), one

USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven 16-bit timers, one 32-bit timer and an advanced-control PWM timer.

The STM32F072x8/xB microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

The STM32F072x8/xB microcontrollers include devices in seven different packages ranging from 48 pins to 100 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included.

These features make the STM32F072x8/xB microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,

PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.

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STM32F072x8 STM32F072xB Description

Table 2. STM32F072x8/xB family device features and peripheral counts

Peripheral STM32F072Cx STM32F072Rx STM32F072Vx

Flash memory (Kbyte)

SRAM (Kbyte)

Timers

Advanced control

General purpose

64 128 64

1 (16-bit)

128 64

Comm. interfaces

Basic

SPI [I

(1)

USART

CAN

5 (16-bit)

1 (32-bit)

2 (16-bit)

2 [2]

USB

CEC

12-bit ADC

(number of channels)

12-bit DAC

(number of channels)

(10 ext. + 3 int.)

(16 ext. + 3 int.)

Analog comparator

GPIOs

Capacitive sensing channels

Max. CPU frequency

17 18

(2)

Operating voltage

48 MHz

2.0 to 3.6 V

Operating temperature

Ambient operating temperature: -40°C to 85°C / -40°C to 105°C

Junction temperature: -40°C to 105°C / -40°C to 125°C

Packages

LQFP48

UFQFPN48

WLCSP49

LQFP64

UFBGA64

1. The SPI interface can be used either in SPI mode or in I 2 S audio mode.

LQFP100

UFBGA100

128

DS9826 Rev 6 11/128

Description STM32F072x8 STM32F072xB

SWCLK

SWDIO as AF

Serial Wire

Debug

CORTEX-M0 CPU f

MAX

= 48 MHz

NVIC

GP DMA

7 channels

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[10:9], PF6

PF[3:0]

GPIO port A

GPIO port B

GPIO port C

GPIO port D

GPIO port E

GPIO port F

8 groups of

4 channels

SYNC

87 AF

D+, D-

TX, RX as AF

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS as AF

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS as AF

PAD

Analog switches

SPI1/I2S1

SPI2/I2S2

SYSCFG IF

Touch

Sensing

Controller

EXT. IT WKUP

USB

PHY

@ V

DDIO2

USB

SRAM 768B

SRAM 256B

BxCAN

Figure 1. Block diagram

AHB

APB

HSI14

HSI

PLLCLK

LSI

HSI48

DD18

Flash GPL up to 128 KB

32-bit

SRAM

16 KB

@ V

DDA

DDIO2

OKIN

POR

Reset

Int

RC 14 MHz

RC 8 MHz

PLL

RC 40 kHz

RC 48MHz

VOLT.REG

3.3 V to 1.8 V

@ V

POWER

SUPPLY

SUPERVISION

POR/PDR

PVD

@ V

DDA

@ V

XTAL OSC

4-32 MHz

RESET & CLOCK

CONTROL

Ind. Window WDG

Power

Controller V

@ V

BAT

System and peripheral clocks

XTAL32 kHz

RTC

Backup reg

RTC interface

CRS

CRC

Window WDG

PWM TIMER 1

TIMER 2 32-bit

TIMER 3

TIMER 14

TIMER 15

TIMER 16

TIMER 17

DBGMCU

USART1

USART2

USART3

USART4

NRST

DDA

SSA

= 2 to 3.6 V

OSC_IN

OSC_OUT

BAT

= 1.65 to 3.6 V

OSC32_IN

OSC32_OUT

3 TAMPER-RTC

(ALARM OUT)

SYNC

4 channels

3 compl. channels

BRK, ETR input as AF

4 ch., ETR as AF

1 channel as AF

2 channels

1 compl, BRK as AF

1 channel

1 compl, BRK as AF

1 channel

1 compl, BRK as AF

IR_OUT as AF

RX, TX,CTS, RTS,

CK as AF

RX, TX,CTS, RTS,

CK as AF

RX, TX,CTS, RTS,

CK as AF

RX, TX,CTS, RTS,

CK as AF

INPUT +

INPUT -

OUTPUT as AF

16x

AD input

DDA

SSA

GP comparator 1

GP comparator 2

@ V

DDA

Temp. sensor

12-bit ADC IF

@ V

DDA

TIMER 6

TIMER 7

I2C1

I2C2

HDMI-CEC

12-bit DAC

@ V

DDA

SCL, SDA, SMBA

(20 mA FM+) as AF

SCL, SDA

(20 mA FM+) as AF

CEC as AF

DAC_OUT1

DAC_OUT2

Power domain of analog blocks : V

BAT

DDA

DDIO2

MSv31404V4

12/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Functional overview

Figure 1 shows the general block diagram of the STM32F072x8/xB devices.

3.1 Arm

®

-Cortex

®

-M0 core

The Arm

Cortex

-M0 is a generation of Arm 32-bit RISC processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The Arm

Cortex

-M0 processors feature exceptional code-efficiency, delivering the high performance expected from an Arm core, with memory sizes usually associated with 8- and

16-bit devices.

The STM32F072x8/xB devices embed Arm core and are compatible with all Arm tools and software.

3.2 Memories

The device has the following features:

• 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications.

• The non-volatile memory is divided into two arrays:

– 64 to 128 Kbytes of embedded Flash memory for programs and data

– Option bytes

The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:

– Level 0: no readout protection

– Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

– Level 2: chip readout protection, debug features (Arm ® Cortex ® -M0 serial wire) and boot in RAM selection disabled

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:

• boot from User Flash memory

• boot from System Memory

• boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15, or PA9/PA10 or I 2 C on pins PB6/PB7 or through the USB

DFU interface.

DS9826 Rev 6 13/128

Functional overview STM32F072x8 STM32F072xB

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.5.1

3.5.2

Power supply schemes

• V

= V

DDIO1

= 2.0 to 3.6 V: external power supply for I/Os (V

DDIO1

) and the internal regulator. It is provided externally through VDD pins.

• V

DDA

= from V

to 3.6 V: external analog power supply for ADC, DAC, Reset blocks,

RCs and PLL (minimum voltage to be applied to V

DDA

is 2.4 V when the ADC or DAC are used). It is provided externally through VDDA pin. The V

DDA always greater or equal to the V

voltage level must be

voltage level and must be established first.

• V

DDIO2 from V

DDIO2

= 1.65 to 3.6 V: external power supply for marked I/Os. V

DDIO2 externally through the VDDIO2 pin. The V

DDIO2

is provided

voltage level is completely independent

supply is monitored and compared with the internal reference voltage

REFINT

or V

DDA

, but it must not be provided without a valid supply on V

. The

). When the V

DDIO2

is below this threshold, all the I/Os supplied from this rail are disabled by hardware. The output of this comparator is connected to EXTI line 31 and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for concerned I/Os list.

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to

Figure 13: Power supply scheme

Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.

They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold,

POR/PDR

, without the need for an external reset circuit.

• The POR monitors only the V

DD that V

DDA

supply voltage. During the startup phase it is required

should arrive first and be greater than or equal to V

• The PDR monitors both the V

and V

DDA

supply voltages, however the V

DDA

power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V

DDA equal to V

is higher than or

The device features an embedded programmable voltage detector (PVD) that monitors the

power supply and compares it to the V

PVD

threshold. An interrupt can be generated when V

drops below the V

PVD

threshold and/or when V

is higher than the V

PVD

14/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Functional overview threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

The regulator has two operating modes and it is always enabled after reset.

• Main (MR) is used in normal operating mode (Run).

• Low power (LPR) can be used in Stop mode where the power demand is reduced.

In Standby mode, it is put in power down mode. In this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost).

Note:

3.6

The STM32F072x8/xB microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the

HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines, the PVD output, RTC, I2C1, USART1,

USART2, USB, COMPx, V

DDIO2 supply comparator or the CEC.

The CEC, USART1, USART2 and I2C1 peripherals can be configured to enable the

HSI RC oscillator so as to get clock for processing incoming data. If this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the RTC domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches

DS9826 Rev 6 15/128

Functional overview STM32F072x8 STM32F072xB back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Figure 2. Clock tree

SYNC

LSE

USB SOF

SYNCSRC

CRS

Trim

48 MHz

HSI RC

HSI48

HSI

HSI48

HSI

I2C1SW

FLITFCLK

SYSCLK

Flash memory programming interface

I2C1

I2S1/SPI1

I2S2/SPI2

CECSW

LSE

/244

CEC

8 MHz

HSI RC

HSI

PREDIV

PLLSRC PLLMUL

/1,/2,..

../16

PLL x2,x3,..

...x16

HSI48

HSI

PLLCLK

HSE

SYSCLK

/1,/2,…

…/512

HPRE

HCLK

/1,/2,/4,

/8,/16

PPRE

AHB, core, memory, DMA,

Cortex FCLK free-run clock

PCLK

Cortex system timer

APB peripherals

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

MCO

4-32 MHz

HSE OSC

32.768 kHz

LSE OSC

HSE

LSE

/32

LSE

CSS

RTCCLK

PPRE x1, x2

PCLK

SYSCLK

HSI

LSE

USARTxSW

USBSW

HSI48

TIM1,2,3,6,7,

14,15,16,17

USART1

USART2

RTC

40 kHz

LSI RC

Main clock output

MCOPRE

/1,/2,/4,..

../128

TIM14

LSI

RTCSEL

MCO

PLLNODIV

PLLCLK

HSI48

HSE

LSI

LSE

/1,/2

HSI

HSI14

SYSCLK

14 MHz RC

HSI14

Legend black white

HSI14

USB

IWDG

ADC asynchronous clock input clock tree element clock tree control element clock line control line

MSv31418V2

Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

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STM32F072x8 STM32F072xB Functional overview

Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL input source. This oscillator can be automatically fine-trimmed by the means of the CRS peripheral using the external synchronization.

3.8

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

Direct memory access controller (DMA)

The 7-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers

(except TIM14), DAC and ADC.

3.9 Interrupts events

3.9.1 Nested vectored interrupt controller (NVIC)

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex

®

-M0) and 4 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

DS9826 Rev 6 17/128

Functional overview

3.9.2 Extended interrupt/event controller (EXTI)

STM32F072x8 STM32F072xB

The extended interrupt/event controller consists of 32 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 87

GPIOs can be connected to the 16 external interrupt lines.

3.10 Analog-to-digital converter (ADC)

The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, VBAT voltage measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The temperature sensor (TS) generates a voltage V

SENSE temperature.

that varies linearly with

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

Table 3. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

TS ADC raw data acquired at a temperature of 110 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7B8 - 0x1FFF F7B9

0x1FFF F7C2 - 0x1FFF F7C3

3.10.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC and comparators. V

REFINT

) provides a stable (bandgap) voltage output for the

is internally connected to the ADC_IN17 input channel. The

18/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Functional overview precise voltage of V

REFINT

is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 4. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7BA - 0x1FFF F7BB

3.10.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT using the internal ADC channel ADC_IN18. As the V

BAT and thus outside the ADC input range, the V

battery voltage

voltage may be higher than V

BAT

pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the V

BAT

voltage.

DDA

The two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration.

This digital Interface supports the following features:

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

Six DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger outputs and the DAC interface is generating its own DMA requests.

The device embeds two fast rail-to-rail low-power comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output pins

•

Internal reference voltage or submultiple (1/4, 1/2, 3/4).Refer to Table 28: Embedded internal reference voltage

for the value and precision of the internal reference voltage.

DS9826 Rev 6 19/128

Functional overview STM32F072x8 STM32F072xB

Both comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined into a window comparator.

3.13 Touch sensing controller (TSC)

The STM32F072x8/xB devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists in charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.

For operation, one capacitive sensing GPIO in each group is connected to an external capacitor and cannot be used as effective touch sensing channel.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

Table 5. Capacitive sensing GPIOs available on STM32F072x8/xB devices

Group

Capacitive sensing signal name

Pin name

Group

Capacitive sensing signal name

Pin name

TSC_G1_IO1

TSC_G1_IO2

TSC_G1_IO3

TSC_G1_IO4

TSC_G2_IO1

TSC_G2_IO2

TSC_G2_IO3

TSC_G2_IO4

TSC_G3_IO1

TSC_G3_IO2

TSC_G3_IO3

TSC_G3_IO4

TSC_G4_IO1

TSC_G4_IO2

TSC_G4_IO3

TSC_G4_IO4

PC5

PB0

PB1

PB2

PA9

PA10

PA11

PA12

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

TSC_G5_IO1

TSC_G5_IO2

TSC_G5_IO3

TSC_G5_IO4

TSC_G6_IO1

TSC_G6_IO2

TSC_G6_IO3

TSC_G6_IO4

TSC_G7_IO1

TSC_G7_IO2

TSC_G7_IO3

TSC_G7_IO4

TSC_G8_IO1

TSC_G8_IO2

TSC_G8_IO3

TSC_G8_IO4

PE2

PE3

PE4

PE5

PD12

PD13

PD14

PD15

PB3

PB4

PB6

PB7

PB11

PB12

PB13

PB14

20/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Functional overview

Table 6. Number of capacitive sensing channels available

on STM32F072x8/xB devices

Number of capacitive sensing channels

Analog I/O group

STM32F072Vx STM32F072Rx STM32F072Cx

Number of capacitive sensing channels

3.14 Timers and watchdogs

The STM32F072x8/xB devices include up to six general-purpose timers, two basic timers and an advanced control timer.

Table 7 compares the features of the different timers.

Timer type

General purpose

Basic

Timer

Advanced control

TIM1

TIM3

TIM14

TIM15

TIM16

TIM17

TIM6

TIM7

Counter resolution

16-bit

TIM2 32-bit

16-bit

Table 7. Timer feature comparison

Counter type

Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

Up, down, up/down

Up integer from

1 to 65536 integer from

1 to 65536

Yes

DS9826 Rev 6 21/128

Functional overview STM32F072x8 STM32F072xB

3.14.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for:

• input capture

• output compare

• PWM generation (edge or center-aligned modes)

• one-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard timers which have the same architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining.

There are six synchronizable general-purpose timers embedded in the STM32F072x8/xB

devices (see Table 7 for differences). Each general-purpose timer can be used to generate

PWM outputs, or as simple time base.

TIM2, TIM3

STM32F072x8/xB devices feature two synchronizable 4-channel general-purpose timers.

TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining.

TIM2 and TIM3 both have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

Their counters can be frozen in debug mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output.

Its counter can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

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STM32F072x8 STM32F072xB Functional overview

TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output.

The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate withTIM1 via the Timer Link feature for synchronization or event chaining.

TIM15 can be synchronized with TIM16 and TIM17.

TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and independent DMA request generation.

Their counters can be frozen in debug mode.

3.14.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as generic

16-bit time bases.

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.14.5 System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode.

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• a 24-bit down counter

• autoreload capability

• maskable system interrupt generation when the counter reaches 0

• programmable clock source (HCLK or HCLK/8)

The RTC and the five backup registers are supplied through a switch that takes power either on V

supply when present or through the V

BAT

pin. The backup registers are five 32-bit registers used to store 20 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, or at wake up from Standby mode.

DS9826 Rev 6 23/128

Functional overview STM32F072x8 STM32F072xB

The RTC is an independent BCD timer/counter. Its main features are the following:

• calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format

• automatic correction for 28, 29 (leap year), 30, and 31 day of the month

• programmable alarm with wake up from Stop and Standby mode capability

• Periodic wakeup unit with programmable resolution and period.

• on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize the RTC with a master clock

• digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy

• Three anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection

• timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection

• reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision

The RTC clock sources can be:

• a 32.768 kHz external crystal

• a resonator or oscillator

• the internal low-power RC oscillator (typical frequency of 40 kHz)

• the high-speed external clock divided by 32

circuit interface (I

2

C)

Up to two I 2 C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode

Plus (up to 1 Mbit/s) with 20 mA output drive on most of the associated I/Os.

Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). They also include programmable analog and digital noise filters.

Table 8. Comparison of I 2 C analog and digital filters

Aspect

Pulse width of suppressed spikes

Benefits

Drawbacks

Analog filter

≥ 50 ns

Available in Stop mode

Variations depending on temperature, voltage, process

Digital filter

Programmable length from 1 to 15

I2Cx peripheral clocks

–Extra filtering capability vs.

standard requirements

–Stable length

Wakeup from Stop on address match is not available when digital filter is enabled.

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts

24/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Functional overview verifications and ALERT protocol management. I2C1 also has a clock domain independent from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.

The I2C peripherals can be served by the DMA controller.

Refer to Table 9

for the differences between I2C1 and I2C2.

Table 9. STM32F072x8/xB I 2 C implementation

C features

(1)

I2C1 I2C2

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive I/Os

Independent clock

SMBus

Wakeup from STOP

1. X = supported.

(USART)

The device embeds four universal synchronous/asynchronous receivers/transmitters

(USART1, USART2, USART3, USART4) which communicate at speeds of up to 6 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. USART1 and USART2 support also SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have a clock domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.

The USART interfaces can be served by the DMA controller.

Table 10. STM32F072x8/xB USART implementation

USART modes/features

(1)

USART1 and

USART2

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

USART3 and

USART4

DS9826 Rev 6 25/128

Functional overview STM32F072x8 STM32F072xB

Table 10. STM32F072x8/xB USART implementation (continued)

USART modes/features

(1)

USART1 and

USART2

USART3 and

USART4

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

1. X = supported.

3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I

2

S)

Two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

Two standard I 2 S interfaces (multiplexed with SPI1 and SPI2 respectively) supporting four different audio standards can operate as master or slave at half-duplex communication mode. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to

192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, they can output a clock for an external audio component at 256 times the sampling frequency.

Hardware CRC calculation

Rx/Tx FIFO

NSS pulse mode

I 2 S mode

TI mode

1. X = supported.

Table 11. STM32F072x8/xB SPI/I 2 S implementation

SPI features (1) SPI1 and SPI2

3.19 High-definition electronics control (CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the

Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory

26/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Functional overview overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception.

3.20 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

3.21 Universal serial bus (USB)

The STM32F072x8/xB embeds a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification

Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has software-configurable endpoint setting with packet memory up-to 1 KB (the last 256 byte are used for CAN peripheral if enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal-less operation.

The STM32F072x8/xB embeds a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

3.23 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

DS9826 Rev 6 27/128

Memory mapping STM32F072x8 STM32F072xB

28/128

To the difference of STM32F072xB memory map in

Figure 3

, the two bottom code memory spaces of STM32F072x8 end at 0x0000 FFFF and 0x0800 FFFF, respectively.

Figure 3. STM32F072xB memory map

0xFFFF FFFF

Reserved

0xE010 0000

0xE000 0000

Cortex-M0 internal peripherals

0xC000 0000

Reserved

0xA000 0000

Reserved

0x8000 0000

Reserved

3 Reserved

0x6000 0000

0x4000 0000

Reserved

Peripherals

Reserved

0x2000 0000

SRAM

0x0000 0000

CODE

0x1FFF FFFF

0x1FFF FC00

0x1FFF F800

Reserved

Option Bytes

System memory

0x1FFF C800

Reserved

0x0802 0000

Flash memory

0x0800 0000

Reserved

0x0002 0000

0x0000 0000

Flash, system memory or SRAM, depending on BOOT configuration

0x4800 17FF

0x4800 0000

AHB2

Reserved

0x4002 43FF

0x4002 0000

AHB1

Reserved

0x4001 8000

APB

0x4001 0000

Reserved

0x4000 8000

APB

0x4000 0000

MS31409V2

DS9826 Rev 6

STM32F072x8 STM32F072xB

Bus

AHB2

AHB1

APB

Memory mapping

0x4800 1800 - 0x5FFF FFFF

0x4800 1400 - 0x4800 17FF

0x4800 1000 - 0x4800 13FF

0x4800 0C00 - 0x4800 0FFF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 4000 - 0x4002 43FF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0000 - 0x4002 03FF

0x4001 8000 - 0x4001 FFFF

0x4001 5C00 - 0x4001 7FFF

0x4001 5800 - 0x4001 5BFF

0x4001 4C00 - 0x4001 57FF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2800 - 0x4001 2BFF

0x4001 2400 - 0x4001 27FF

0x4001 0800 - 0x4001 23FF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 8000 - 0x4000 FFFF

Table 12. Peripheral register boundary addresses

Boundary address Size Peripheral

Reserved

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

Reserved

TSC

Reserved

CRC

Reserved

Flash memory interface

Reserved

RCC

Reserved

DMA

Reserved

DBGMCU

Reserved

TIM17

TIM16

TIM15

Reserved

USART1

Reserved

SPI1/I2S1

TIM1

Reserved

ADC

Reserved

EXTI

SYSCFG + COMP

Reserved

3 KB

1 KB

3 KB

1 KB

32 KB

9 KB

1 KB

3 KB

1 KB

3 KB

1 KB

3 KB

~384 MB

1 KB

~128 MB

1 KB

7 KB

1 KB

32 KB

DS9826 Rev 6 29/128

Memory mapping

Bus

APB

STM32F072x8 STM32F072xB

Table 12. Peripheral register boundary addresses (continued)

Boundary address Size Peripheral

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 3C00 - 0x4000 43FF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1800 - 0x4000 1FFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0800 - 0x4000 0FFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

1 KB

2 KB

1 KB

2 KB

1 KB

2 KB

1 KB

IWDG

WWDG

RTC

Reserved

TIM14

Reserved

TIM7

TIM6

Reserved

TIM3

TIM2

Reserved

CEC

DAC

PWR

CRS

Reserved

BxCAN

USB/CAN RAM

USB

I2C2

I2C1

Reserved

USART4

USART3

USART2

Reserved

SPI2

Reserved

30/128 DS9826 Rev 6

STM32F072x8 STM32F072xB

5 Pinouts and pin descriptions

Figure 4. UFBGA100 package pinout

Pinouts and pin descriptions

Top view

1 2 3 4 5 6 7 8 9 10 11 12

PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12

PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11

PC13 PE5 PE0

PC14-

OSC32_

PC15-

OSC32_

OUT

PF0-

OSC_

PE6

VBAT

PF9

PF1-

OSC_

OUT

PF10

VSS

PC0 NRST VDD

VDD PB5 PD2 PD0 PC11

PA9

PC8

PF6 PA10

PA8

PC7

PC9

PC6

VSS VSS

VDDIO2 VDD

PD15 PD14 PD13

PF2

VSSA

PC1

PC3

PC2

PA2 PA5 PC4

PD12 PD11 PD10

PD9 PD8 PB15 PB14 PB13

PF3 PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12

VDDA PA1 PA4 PA7 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15

UFBGA100

I/O supplied from VDDIO2

MSv33167V4

DS9826 Rev 6 31/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Figure 5. LQFP100 package pinout

Top view

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF9

PF10

PF0-OSC_IN

PF1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

PF2

VSSA

VDDA

PF3

PA0

PA1

PA2

LQFP100

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

VDDIO2

VSS

PF6

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

I/O supplied from VDDIO2

MSv31410V2

32/128 DS9826 Rev 6

STM32F072x8 STM32F072xB

Top view

Pinouts and pin descriptions

Figure 6. UFBGA64 package pinout

2 3 4 5 6 7 8

PC14-

OSC32_

PC13

PC15-

OSC32_

OUT

VBAT

PF0-

OSC_

PF1-

OSC_

OUT

VSS

VDD

PB9

PB8

PB7

PB6

PB4 PB3

BOOT0 PD2

PB5

VSS

PC12

VSS

PA15

PC11

PA10

VSS

PA14

PC10

PA9

PA8

PA13

PA12

PA11

PC9

NRST PC1 PC0 VDD VDD VDDIO2 PC7 PC8

VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14

PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13

VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12

UFBGA64

I/O supplied from VDDIO2

MSv39735V1

DS9826 Rev 6 33/128

Pinouts and pin descriptions

Top view

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VDDA

PA0

PA1

PA2

STM32F072x8 STM32F072xB

Figure 7. LQFP64 package pinout

LQFP64

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VDDIO2

VSS

PA13

PA12

PA11

PA10

PA9

I/O supplied from VDDIO2

Figure 8. LQFP48 package pinout

Top view

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

NRST

VSSA

VDDA

PA0

PA1

PA2

LQFP48

VDDIO2

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

MSv31411V2

I/O supplied from VDDIO2

MSv31412V2

34/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Figure 9. UFQFPN48 package pinout

Top view

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

NRST

VSSA

VDDA

PA0

PA1

PA2

UFQFPN48

VDDIO2

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

I/O supplied from VDDIO2

MSv32166V2

Figure 10. WLCSP49 package pinout

Top view

1 2 3 4 5 6 7

PA14 PA15 PB3 PB4 BOOT0 VSS VDD

VSS

PA8

VDDIO2

PA9

PA13

PA11 PA10 PA12

VSS

PB5 PB8 NC VBAT

PB6

PB7

PB9

PC13

PC15-

OSC32_

OUT

PC14-

OSC32_

PF1-

OSC_

OUT

PF0-

OSC_

PB15 PB12 PB10 PA3 PA2 VSSA NRST

PB14 VDD PA7 PA6 PA5 PA0 VDDA

G PB13 PB11 PB2 PB1 PB0 PA4 PA1

WLCSP49

I/O supplied from VDDIO2

MSv32165V4

1. The above figure shows the package in top view, changing from bottom view in the previous document versions.

DS9826 Rev 6 35/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Name

Table 13. Legend/abbreviations used in the pinout table

Abbreviation Definition

I/O structure

Pin name

Pin type functions

Notes

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input-only pin

I/O

FTf

TTa

Input / output pin

5 V-tolerant I/O

5 V-tolerant I/O, FM+ capable

3.3 V-tolerant I/O directly connected to ADC

Standard 3.3 V I/O

Dedicated BOOT0 pin

RST Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.

Alternate functions

Additional functions

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Pin numbers

Table 14. STM32F072x8/xB pin definitions

Pin functions

Pin name

(function upon reset)

Pin type

Alternate functions

Additional functions

B2 1

A1 2

B1 3

C2 4

D2 5 -

E2 6 B2 1

1 B7

PE2

PE3

PE4

PE5

I/O FT

PE6 I/O FT -

VBAT S -

TSC_G7_IO1,

TIM3_ETR

TSC_G7_IO2,

TIM3_CH1

TSC_G7_IO3,

TIM3_CH2

TSC_G7_IO4,

TIM3_CH3

TIM3_CH4

WKUP3,

RTC_TAMP3

Backup power supply

36/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Pin numbers

Table 14. STM32F072x8/xB pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate functions

Additional functions

C1 7 A2 2 2 D5 PC13 I/O TC

(1)

(2)

WKUP2,

RTC_TAMP1,

RTC_TS,

RTC_OUT

D1 8 A1 3

E1 9 B1 4

F2 10

G2 11

F1 12 C1 5

G1 13 D1 6

3 C7

4 C6

5 D7

6 D6

PC14-

OSC32_IN

(PC14)

PC15-

OSC32_OUT

(PC15)

PF9

PF10

PF0-OSC_IN

(PF0)

PF1-OSC_OUT

(PF1)

I/O TC

I/O FT

(1)

(2)

(1)

(2)

I/O FT -

H2 14 E1 7

H1 15 E3 8

J2 16 E2 9

J3 17 F2 10 -

K2 18 G1 11 -

J1 19 -

K1 20 F1 12 8 E6

M1 21 H1 13 9 F7

L1 22 -

L2 23 G2 14 10 F6

NRST

PC0

PC1

PC2

PC3

PF2

VSSA

VDDA

PF3

PA0

I/O RST -

I/O TTa -

I/O FT -

S -

I/O FT -

I/O TTa -

TIM15_CH1

TIM15_CH2

CRS_ SYNC

OSC32_IN

OSC32_OUT

OSC_IN

OSC_OUT

Device reset input / internal reset output

(active low)

EVENTOUT

SPI2_MISO, I2S2_MCK,

EVENTOUT

SPI2_MOSI, I2S2_SD,

EVENTOUT

ADC_IN10

ADC_IN11

ADC_IN12

ADC_IN13

EVENTOUT

Analog ground

USART2_CTS,

TIM2_CH1_ETR,

COMP1_OUT,

TSC_G1_IO1,

USART4_TX

WKUP8

Analog power supply

EVENTOUT

RTC_ TAMP2,

WKUP1,

ADC_IN0,

COMP1_INM6

DS9826 Rev 6 37/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Pin numbers

Table 14. STM32F072x8/xB pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate functions

Additional functions

24 H2 15 11 G7 PA1

L3 26 G3 17 13 E4

D3 27 C2 18 -

H3 28 D2 19 -

M3 29 H3 20 14 G6

PA3

VSS

VDD

PA4

PA2

PA5

PA6

PA7

I/O TTa -

USART2_RTS,

TIM2_CH2,

TIM15_CH1N,

TSC_G1_IO2,

USART4_RX,

EVENTOUT

USART2_TX,

COMP2_OUT,

TIM2_CH3,

TIM15_CH1,

TSC_G1_IO3

USART2_RX,TIM2_CH4,

TIM15_CH2,

TSC_G1_IO4

ADC_IN1,

COMP1_INP

ADC_IN2,

COMP2_INM6,

WKUP4

ADC_IN3,

COMP2_INP

Ground

Digital power supply

SPI1_NSS, I2S1_WS,

TIM14_CH1,

TSC_G2_IO1,

USART2_CK

SPI1_SCK, I2S1_CK,

CEC,

TIM2_CH1_ETR,

TSC_G2_IO2

SPI1_MISO, I2S1_MCK,

TIM3_CH1, TIM1_BKIN,

TIM16_CH1,

COMP1_OUT,

TSC_G2_IO3,

EVENTOUT,

USART3_CTS

SPI1_MOSI, I2S1_SD,

TIM3_CH2, TIM14_CH1,

TIM1_CH1N,

TIM17_CH1,

COMP2_OUT,

TSC_G2_IO4,

EVENTOUT

COMP1_INM4,

COMP2_INM4,

ADC_IN4,

DAC_OUT1

COMP1_INM5,

COMP2_INM5,

ADC_IN5,

DAC_OUT2

ADC_IN6

ADC_IN7

38/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Pin numbers

Table 14. STM32F072x8/xB pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate functions

Additional functions

K5 33 H5 24 -

L5 34 H6 25 -

M5 35 F5 26 18 G5

M6 36 G5 27 19 G4

L6 37 G6 28 20 G3

M7 38

L7 39

M8 40

L8 41

M9 42

L9 43 -

M10 44 -

M11 45 -

M12 46 -

L10 47 G7 29 21 E3

L11 48 H7 30 22 G2

F12 49 D5 31 23 D3

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS

I/O TTa -

I/O FT -

S -

EVENTOUT,

USART3_TX

TSC_G3_IO1,

USART3_RX

TIM3_CH3, TIM1_CH2N,

TSC_G3_IO2,

EVENTOUT,

USART3_CK

TIM3_CH4,

USART3_RTS,

TIM14_CH1,

TIM1_CH3N,

TSC_G3_IO3

TSC_G3_IO4

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

SPI1_NSS, I2S1_WS,

TIM1_CH3N

SPI1_SCK, I2S1_CK,

TIM1_CH3

SPI1_MISO, I2S1_MCK,

TIM1_CH4

SPI1_MOSI, I2S1_SD,

TIM1_BKIN

SPI2_SCK, I2C2_SCL,

USART3_TX, CEC,

TSC_SYNC, TIM2_CH3

USART3_RX,

TIM2_CH4,

EVENTOUT,

TSC_G6_IO1,

I2C2_SDA

Ground

ADC_IN14

ADC_IN15,

WKUP5

ADC_IN8

ADC_IN9

DS9826 Rev 6 39/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Pin numbers

Table 14. STM32F072x8/xB pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate functions

Additional functions

G12 50

L12 51

K12 52 G8 34 26 G1

K11

K10

40/128

K9 55

K8 56

J12 57

J11 58

J10 59

H12 60

H11 61

H10 62 -

E12 63 F6 37 -

E11 64 E7 38 -

E10 65 E8 39 -

D12 66 D8 40 -

VDD

PB12

PB13

PB14

PB15

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PC6

PC7

PC8

PC9

I/O

FTf

(3)

Digital power supply

TIM1_BKIN,

TIM15_BKIN,

SPI2_NSS, I2S2_WS,

USART3_CK,

TSC_G6_IO2,

EVENTOUT

SPI2_SCK, I2S2_CK,

I2C2_SCL,

USART3_CTS,

TIM1_CH1N,

TSC_G6_IO3

SPI2_MISO, I2S2_MCK,

I2C2_SDA,

USART3_RTS,

TIM1_CH2N,

TIM15_CH1,

TSC_G6_IO4

SPI2_MOSI, I2S2_SD,

TIM1_CH3N,

TIM15_CH1N,

TIM15_CH2

WKUP7,

RTC_REFIN

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

USART3_RTS,

TSC_G8_IO1

TSC_G8_IO2

TSC_G8_IO3

TSC_G8_IO4,

CRS_SYNC

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4 -

DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Pin numbers

Table 14. STM32F072x8/xB pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate functions

Additional functions

D11

D10

C12

B12

A12

B11

PA8

PA9

PA10

PA11

PA12

A11 72 A8 46 34 B3

C11 73 -

F11 74 D6 47 35 B1

G11 75 E6 48 36 B2

A10 76 A7 49 37 A1

PA13

PF6

VSS

VDDIO2

PA14

A9 77 A6 50 38 A2 PA15

PC10

I/O FT

S -

I/O FT

(3)

(4)

(3)

(4)

USART1_CK,

TIM1_CH1,

EVENTOUT, MCO,

CRS_SYNC

USART1_TX,

TIM1_CH2,

TIM15_BKIN,

TSC_G4_IO1

USART1_RX,

TIM1_CH3,

TIM17_BKIN,

TSC_G4_IO2

CAN_RX,

USART1_CTS,

TIM1_CH4,

COMP1_OUT,

TSC_G4_IO3,

EVENTOUT

USB_DM

CAN_TX, USART1_RTS,

TIM1_ETR,

COMP2_OUT,

TSC_G4_IO4,

EVENTOUT

IR_OUT, SWDIO,

USB_NOE

USB_DP

Ground

Digital power supply

USART2_TX, SWCLK -

(3)

SPI1_NSS, I2S1_WS,

USART2_RX,

USART4_RTS,

TIM2_CH1_ETR,

EVENTOUT

USART3_TX,

USART4_TX

DS9826 Rev 6 41/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Pin numbers

Table 14. STM32F072x8/xB pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate functions

Additional functions

C10 79 B6 52 -

B10 80 C5 53 -

C8 83 B5 54 -

B8 84 -

B7 85

A6 86

B6 87

A5 88

A8 89 A5 55 39 A3

PD2

PD3

PD4

PD5

PD6

PD7

PC11

PC12

PD0

PD1

PB3

PB4

PB5

PB6

I/O

FTf

(3)

USART3_RX,

USART4_RX

USART3_CK,

USART4_CK

SPI2_NSS, I2S2_WS,

CAN_RX

SPI2_SCK, I2S2_CK,

CAN_TX

USART3_RTS,

TIM3_ETR

SPI2_MISO, I2S2_MCK,

USART2_CTS

SPI2_MOSI, I2S2_SD,

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

SPI1_SCK, I2S1_CK,

TIM2_CH2,

TSC_G5_IO1,

EVENTOUT

SPI1_MISO, I2S1_MCK,

TIM17_BKIN,

TIM3_CH1,

TSC_G5_IO2,

EVENTOUT

SPI1_MOSI, I2S1_SD,

I2C1_SMBA,

TIM16_BKIN,

TIM3_CH2

I2C1_SCL, USART1_TX,

TIM16_CH1N,

TSC_G5_I03

WKUP6

42/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Pin numbers

Table 14. STM32F072x8/xB pin definitions (continued)

Pin functions

Pin name

(function upon reset)

Pin type

Alternate functions

Additional functions

C3 97 -

A2 98 -

D3 99 D4 63 47 A6

C4 100 E4 64 48 A7

PB7

BOOT0

PB8

PB9

PE0

PE1

VSS

VDD

I/O

FTf

I2C1_SDA,

USART1_RX,

USART4_CTS,

TIM17_CH1N,

TSC_G5_IO4

Boot memory selection

I/O FTf -

I2C1_SCL, CEC,

TIM16_CH1,

TSC_SYNC,

CAN_RX

I/O FTf -

SPI2_NSS, I2S2_WS,

I2C1_SDA, IR_OUT,

TIM17_CH1,

EVENTOUT,

CAN_TX

I/O FT EVENTOUT, TIM16_CH1

I/O FT EVENTOUT, TIM17_CH1

S Ground

S Digital power supply

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual.

3. PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1 and PD2 I/Os are supplied by VDDIO2.

4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin and the internal pull-down on the SWCLK pin are activated.

DS9826 Rev 6 43/128

Pin name

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

PA0

PA1

PA2

PA3

PA4

PA5

PA6

Table 15. Alternate functions selected through GPIOA_AFR registers for port A

AF0

EVENTOUT

TIM15_CH1

TIM15_CH2

SPI1_NSS, I2S1_WS

SPI1_SCK, I2S1_CK

SPI1_MISO, I2S1_MCK

SPI1_MOSI, I2S1_SD

MCO

TIM15_BKIN

TIM17_BKIN

EVENTOUT

SWDIO

SWCLK

SPI1_NSS, I2S1_WS

AF1 AF2 AF3 AF4 AF5 AF6 AF7

USART2_CTS TIM2_CH1_ETR TSC_G1_IO1 USART4_TX

USART2_RTS

USART2_TX

TIM2_CH2

TIM2_CH3

TSC_G1_IO2

TSC_G1_IO3

USART4_RX

TIM15_CH1N

USART2_RX

USART2_CK

CEC

TIM3_CH1

TIM2_CH4

TSC_G1_IO4

TSC_G2_IO1

TIM14_CH1 -

COMP1_OUT

COMP2_OUT

TIM2_CH1_ETR TSC_G2_IO2

TIM1_BKIN TSC_G2_IO3

USART3_CTS

TIM16_CH1

EVENTOUT

COMP1_OUT

TIM3_CH2

USART1_CK

USART1_TX

USART1_RX

TIM1_CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TSC_G2_IO4 TIM14_CH1

EVENTOUT CRS_SYNC

TSC_G4_IO1

TSC_G4_IO2

USART1_CTS

USART1_RTS

IR_OUT

USART2_TX

TIM1_CH4

TIM1_ETR

USB_NOE

TSC_G4_IO3

TSC_G4_IO4

CAN_RX

CAN_TX

USART2_RX TIM2_CH1_ETR EVENTOUT USART4_RTS

TIM17_CH1 EVENTOUT COMP2_OUT

COMP1_OUT

COMP2_OUT

Pin name

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

PB0

PB1

PB2

PB3

PB4

PB5

PB6

AF0

Table 16. Alternate functions selected through GPIOB_AFR registers for port B

AF1 AF2 AF3 AF4

EVENTOUT

TIM14_CH1

SPI1_SCK, I2S1_CK

SPI1_MISO, I2S1_MCK

SPI1_MOSI, I2S1_SD

USART1_TX

USART1_RX

CEC

IR_OUT

CEC

EVENTOUT

SPI2_NSS, I2S2_WS

SPI2_SCK, I2S2_CK

SPI2_MISO, I2S2_MCK

SPI2_MOSI, I2S2_SD

TIM3_CH3

TIM3_CH4

EVENTOUT

TIM3_CH1

TIM3_CH2

I2C1_SCL

I2C1_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

EVENTOUT

TIM15_CH1

TIM15_CH2

TIM1_CH2N

TIM1_CH3N

TIM2_CH2

EVENTOUT

TIM16_BKIN

TIM16_CH1N

TIM17_CH1N

TIM16_CH1

TIM17_CH1

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

TSC_G3_IO2

TSC_G3_IO3

TSC_G3_IO4

TSC_G5_IO1

TSC_G5_IO2

I2C1_SMBA

TSC_G5_IO3

TSC_G5_IO4

TSC_SYNC

EVENTOUT

TSC_SYNC

TSC_G6_IO1

TSC_G6_IO2

TSC_G6_IO3

TSC_G6_IO4

TIM15_CH1N

USART3_CK

USART3_RTS

USART4_CTS

CAN_RX

CAN_TX

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

USART3_RTS

AF5

TIM17_BKIN

SPI2_NSS, I2S2_WS

SPI2_SCK, I2S2_CK

TIM15_BKIN

I2C2_SCL

I2C2_SDA

46/128

STM32F072x8 STM32F072xB

Table 17. Alternate functions selected through GPIOC_AFR registers for port C

Pin name AF0 AF1

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

PC4

PC5

PC6

PC7

PC0

PC1

PC2

PC3

EVENTOUT

TSC_G3_IO1

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

USART4_TX

USART4_RX

USART4_CK

SPI2_MISO, I2S2_MCK

SPI2_MOSI, I2S2_SD

USART3_TX

USART3_RX

USART3_TX

USART3_RX

USART3_CK

Table 18. Alternate functions selected through GPIOD_AFR registers for port D

Pin name AF0 AF1

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

CAN_RX

CAN_TX

TIM3_ETR

USART2_CTS

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

USART3_TX

USART3_RX

USART3_CK

USART3_CTS

USART3_RTS

CRS_SYNC

SPI2_NSS, I2S2_WS

SPI2_SCK, I2S2_CK

USART3_RTS

SPI2_MISO, I2S2_MCK

SPI2_MOSI, I2S2_SD

TSC_G8_IO1

TSC_G8_IO2

TSC_G8_IO3

TSC_G8_IO4

DS9826 Rev 6

STM32F072x8 STM32F072xB

Table 19. Alternate functions selected through GPIOE_AFR registers for port E

Pin name AF0 AF1

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PE4

PE5

PE6

PE7

PE0

PE1

PE2

PE3

TIM16_CH1

TIM17_CH1

TIM3_ETR

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

EVENTOUT

TSC_G7_IO1

TSC_G7_IO2

TSC_G7_IO3

TSC_G7_IO4

SPI1_NSS, I2S1_WS

SPI1_SCK, I2S1_CK

SPI1_MISO, I2S1_MCK

SPI1_MOSI, I2S1_SD

Pin name

PF0

PF1

PF2

PF3

PF6

PF9

PF10

Table 20. Alternate functions available on port F

CRS_SYNC

EVENTOUT

TIM15_CH1

TIM15_CH2

DS9826 Rev 6 47/128

Electrical characteristics STM32F072x8 STM32F072xB

6.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3 σ ).

Unless otherwise specified, typical data are based on T

A are given only as design guidelines and are not tested.

= 25 °C, V

= V

DDA

= 3.3 V. They

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2 σ ).

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 11

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 12 .

Figure 11. Pin loading conditions Figure 12. Pin input voltage

MCU pin MCU pin

C = 50 pF

48/128

MS19210V1

DS9826 Rev 6

MS19211V1

STM32F072x8 STM32F072xB

6.1.6 Power supply scheme

Figure 13. Power supply scheme

Electrical characteristics

BAT

1.65 – 3.6 V

3 x V

Power switch

Regulator

DDIO1

OUT

3 x 100 nF

+1 x 4.7 μF

GPIOs

3 x V

DDIO2

100 nF

+4.7 μF

10 nF

+1 μF

DDA

DDIO2

GPIOs

DDIO2

OUT

DDA

SSA

REF+

REF-

ADC/

DAC

Backup circuitry

(LSE, RTC,

Backup registers)

CORE

IO logic

Kernel logic

(CPU, Digital

& Memories)

IO logic

Analog:

(RCs, PLL, …)

MSv32190V1

Caution: Each power supply pair (V

, V

DDA

SSA

etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DS9826 Rev 6 49/128

Electrical characteristics STM32F072x8 STM32F072xB

Figure 14. Current consumption measurement scheme

DD_VBAT

VBAT

IDD

VDD

VDDIO2

IDDA

VDDA

MS31999V2

50/128 DS9826 Rev 6

STM32F072x8 STM32F072xB

6.2 Absolute maximum ratings

Electrical characteristics

Stresses above the absolute maximum ratings listed in

Table 21: Voltage characteristics

Table 22: Current characteristics

and

Table 23: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 21. Voltage characteristics

(1)

Ratings Min Max Unit

–V

DDIO2

–V

DDA

–V

DDA

BAT

–V

(2)

External main supply voltage

External I/O supply voltage

External analog supply voltage

Allowed voltage difference for V

> V

DDA

External backup supply voltage

Input voltage on FT and FTf pins

Input voltage on TTa pins

BOOT0

- 0.3

4.0

0.4

4.0

DDIOx

+ 4.0

(3)

4.0

9.0

ESD(HBM)

Input voltage on any other pin

| ∆ V

DDx

| Variations between different V

DD power pins

SSx

- V

Variations between all the different ground pins

Electrostatic discharge voltage

(human body model)

- 0.3

4.0

50 see

Section 6.3.12: Electrical sensitivity characteristics

1. All main power (V , V ) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. V

maximum must always be respected. Refer to

Table 22: Current characteristics for the maximum

allowed injected current values.

3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is enabled, the maximum limit is 4 V.

V mV

DS9826 Rev 6 51/128

Electrical characteristics STM32F072x8 STM32F072xB

Symbol

Table 22. Current characteristics

Ratings Max.

Unit

Σ I

VDD

Σ I

VSS

VDD(PIN)

VSS(PIN)

Total current into sum of all VDD power lines (source)

Total current out of sum of all VSS ground lines (sink)

Maximum current into each VDD power pin (source)

Maximum current out of each VSS ground pin (sink)

(1)

120

-120

100

-100

Output current sunk by any I/O and control pin 25

IO(PIN)

Output current source by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins

(2)

Total output current sourced by sum of all I/Os and control pins

(2)

-25

Σ I

IO(PIN)

-80 mA

Total output current sourced by sum of all I/Os supplied by VDDIO2

Injected current on B, FT and FTf pins

-40

-5/+0 (4)

INJ(PIN)

(3)

Injected current on TC and RST pin

Injected current on TTa pins

(5)

Total injected current (sum of all I/O and control pins)

(6)

± 5

Σ I

INJ(PIN)

± 25

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. A positive injection is induced by V

exceeded. Refer to

> V

DDIOx

while a negative injection is induced by V < V

. I

INJ(PIN)

must never be

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. On these I/Os, a positive injection is induced by V

device. See note below

Table 59: ADC accuracy

> V

DDA

. Negative injection disturbs the analog performance of the

6. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).

Σ I

INJ(PIN)

is the absolute sum of the positive and

Symbol

STG

Table 23. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

52/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

6.3.1 General operating conditions

Symbol

Table 24. General operating conditions

Parameter Conditions Min Max Unit

V f f

HCLK

PCLK

DDIO2

DDA

BAT

Internal AHB clock frequency

Internal APB clock frequency

Standard operating voltage

I/O supply voltage

Must not be supplied if V

DD is not present

Analog operating voltage

(ADC and DAC not used)

Analog operating voltage

(ADC and DAC used)

Backup operating voltage

Must have a potential equal to or higher than V

I/O input voltage

TC and RST I/O

TTa I/O

FT and FTf I/O

BOOT0

UFBGA100

LQFP100

Power dissipation at T for suffix 6 or T suffix 7

(2)

= 85 °C

= 105 °C for

UFBGA64

LQFP64

LQFP48

UFQFPN48

Ambient temperature for the suffix 6 version

WLCSP49

Maximum power dissipation

Low power dissipation

(3)

Ambient temperature for the suffix 7 version

Junction temperature range

Maximum power dissipation

Low power dissipation

(3)

Suffix 6 version

Suffix 7 version

2.0

1.65

2.4

1.65

–0.3

–40

3.6

DDIOx

+0.3

DDA

+0.3

(1)

5.5

(1)

5.5

364

476

308

455

370

625

408

–40 105

–40 125

–40 105

–40 125

MHz

V mW

°C

1. For operation with a voltage higher than V

DDIOx

+ 0.3 V, the internal pull-up resistor must be disabled.

2. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

. See

Section 7.8: Thermal characteristics

3. In low power dissipation state, T

Thermal characteristics

can be extended to this range as long as T

does not exceed T

Jmax

(see

Section 7.8:

DS9826 Rev 6 53/128

Electrical characteristics STM32F072x8 STM32F072xB

6.3.3

The parameters given in

Table 25 are derived from tests performed under the ambient

temperature condition summarized in

Table 24 .

Symbol t

VDD t

VDDA

Table 25. Operating conditions at power-up / power-down

Parameter Conditions Min Max

rise time rate

fall time rate

DDA

rise time rate

DDA

fall time rate

∞

Unit

µs/V

Embedded reset and power control block characteristics

The parameters given in

Table 26 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 24: General operating conditions

Table 26. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

POR/PDR

(1)

Power on/power down reset threshold

Falling edge

Rising edge

(2) 1.80

1.84

(3)

1.88

1.92

1.96

(3)

2.00

PDRhyst t

RSTTEMPO

(4)

PDR hysteresis

Reset temporization -

1.50

2.50

4.50

1. The PDR detector monitors V monitors only V

and also V

DDA

(if kept enabled in the option bytes). The POR detector

2. The product behavior is guaranteed by design down to the minimum V

POR/PDR

value.

3. Data based on characterization results, not tested in production.

4. Guaranteed by design, not tested in production.

mV ms

Symbol

PVD0

PVD1

PVD2

PVD3

Table 27. Programmable voltage detector characteristics

Parameter Conditions Min Typ Max

PVD threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

2.28

2.18

2.38

2.28

2.1

2.19

2.09

2.18

2.26

2.08

2.16

2.28

2.37

2.18

2.27

2.38

2.48

2.28

2.38

2.48

2.58

2.38

2.48

Unit

54/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 27. Programmable voltage detector characteristics (continued)

Symbol Parameter Conditions Min Typ Max

PVD4

PVD5

PVD6

PVD7

PVD threshold 4

PVD threshold 5

PVD threshold 6

PVD threshold 7

PVDhyst

(1)

DD(PVD)

PVD hysteresis

PVD current consumption

1. Guaranteed by design, not tested in production.

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

2.66

2.56

2.76

2.66

2.47

2.37

2.57

2.47

2.58

2.69

2.48

2.59

2.68

2.79

2.58

2.69

2.78

2.68

2.88

2.78

2.9

2.8

2.9

100 -

0.15

0.26

(1)

Unit

V mV

µA

6.3.5

The parameters given in

Table 28 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 24: General operating conditions

Symbol

Table 28. Embedded internal reference voltage

Parameter Conditions Min Typ Max Unit

∆ t t

REFINT

START

S_vrefint

REFINT

Internal reference voltage –40 °C < T

< +105 °C

ADC_IN17 buffer startup time

ADC sampling time when reading the internal reference voltage

Internal reference voltage spread over the temperature range

DDA

= 3 V

Coeff

Temperature coefficient

1. Guaranteed by design, not tested in production.

1.2

1.23

1.25

(1)

- 100

(1)

µs

µs mV

100

(1) ppm/°C

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 14: Current consumption measurement scheme

DS9826 Rev 6 55/128

Electrical characteristics STM32F072x8 STM32F072xB

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the f

HCLK

frequency:

– 0 wait state and Prefetch OFF from 0 to 24 MHz

– 1 wait state and Prefetch ON above 24 MHz

• When the peripherals are enabled f

PCLK

= f

HCLK

The parameters given in

Table 29 to

Table 31 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions

Table 29. Typical and maximum current consumption from V

supply at V

= 3.6 V

All peripherals enabled All peripherals disabled

Conditions f

HCLK

Max @ T

(1)

Max @ T

(1)

Typ Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

Unit

HSI48

HSE bypass,

PLL on

HSE bypass,

PLL off

HSI clock,

PLL on

48 MHz 24.3

48 MHz 24.1

32 MHz 16.0

24 MHz 12.3

8 MHz 4.52

1 MHz 1.25

48 MHz 24.1

32 MHz 16.1

24 MHz 12.4

HSI clock,

PLL off

8 MHz 4.52

1.39

27.1

18.2

14.0

26.9

26.8

18.3

13.7

5.25

1.58

27.6

18.9

14.4

27.2

27.0

18.6

14.3

5.28

5.35

1.87

27.8

19.3

14.8

27.9

27.7

19.2

14.7

5.61

13.1

14.8

13.0

14.6

8.76

9.56

7.36

7.94

2.89

3.17

0.93

1.06

12.9

14.7

8.82

9.69

7.31

7.92

2.87

3.16

1.15

14.9

9.83

8.34

14.9

14.8

9.73

8.37

3.26

3.25

1.34

15.5

10.7

8.75

15.5

15.4

10.6

8.81

3.34

3.33

56/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 29. Typical and maximum current consumption from V

supply at V

= 3.6 V (continued)

All peripherals enabled All peripherals disabled

Conditions f

HCLK

Max @ T

(1)

Max @ T

(1)

Unit

Typ Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

HSI48

HSE bypass,

PLL on

HSE bypass,

PLL off

HSI clock,

PLL on

48 MHz 23.1

25.4

48 MHz 23.0

25.3

(2)

32 MHz 15.4

24 MHz 11.4

8 MHz 4.21

17.3

12.9

4.6

1 MHz 0.78

48 MHz 23.1

32 MHz 15.4

24 MHz 11.5

0.9

24.5

17.4

13.0

0.92

25.0

17.7

13.6

25.8

26.6

25.7

26.5

(2)

17.8

13.5

4.89

18.3

13.7

5.25

1.15

25.2

18.2

13.9

12.8

13.5

12.6 13.3

(2)

7.96

8.92

6.48

8.04

2.07

2.3

0.36

0.48

12.6

13.7

8.05

8.85

6.49

8.06

0.59

13.9

9.16

8.21

13.7

13.9

13.5

13.8

(2)

9.17

8.23

2.35

9.73

8.41

2.94

0.82

14.0

9.94

8.47

HSI clock,

PLL off

HSI48

HSE bypass,

PLL on

HSE bypass,

PLL off

HSI clock,

PLL on

8 MHz 4.34

4.75

48 MHz 15.1

16.6

48 MHz 15.0

16.5

(2)

32 MHz 9.9

11.4

24 MHz 7.43

8 MHz 2.83

1 MHz 0.42

48 MHz 15.0

32 MHz 9.93

24 MHz 7.53

8.17

3.09

0.54

17.2

11.3

8.45

5.03

5.41

16.8

17.5

16.7

17.3

(2)

11.6

11.9

8.71

3.26

0.55

17.3

11.6

8.87

8.82

3.66

0.67

17.9

11.7

8.95

2.11

2.36

3.08

3.43

2.93 3.28

(2)

2.0

2.24

1.63

1.82

0.76

0.88

0.28

0.39

3.04

3.37

2.11

2.35

1.64

1.83

2.38

2.98

3.56

3.61

3.41

3.46

(2)

2.32

2.49

1.88

0.91

0.41

3.41

2.44

1.9

0.93

0.43

3.46

2.65

1.93

HSI clock,

PLL off

8 MHz 2.95

3.24

3.41

3.8

0.8

0.92

0.94

0.97

1. Data based on characterization results, not tested in production unless otherwise specified.

2. Data based on characterization results and tested in production (using one common test limit for sum of I

and I

DDA

DS9826 Rev 6 57/128

Electrical characteristics STM32F072x8 STM32F072xB

Symbol

Table 30. Typical and maximum current consumption from the V

DDA

supply

DDA

= 2.4 V V

DDA

= 3.6 V

Parameter

Conditions

(1) f

HCLK

Typ

Max @ T

(2)

Typ

Max @ T

(2)

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

Unit

DDA

Supply current in

Run or

Sleep mode, code executing from

Flash memory or RAM

HSI48

HSE bypass,

PLL on

HSE bypass,

PLL off

HSI clock,

PLL on

48 MHz 311 326

48 MHz 152 170

(3)

32 MHz

8 MHz

1 MHz

105

24 MHz 81.9

2.7

121

95.9

3.8

48 MHz 223 244

32 MHz 176 195

24 MHz 154 171

334

178 182

126

99.5

4.3

255

203

178

343

(3)

128

4.6

260

206

181

322 337 345

165 184

(3)

196

354

200

(3)

113 129 136 138

101 88.7

102 107

4.6

3.6

4.7

5.2

3.6

4.7

5.2

245 265 279

193 212 221

168 185 192

108

5.5

284

224

195

µA

HSI clock,

PLL off

8 MHz 74.2

83.4

86.4

87.3

83.4

92.5

95.3

96.6

1. Current consumption from the V in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, I the frequency.

DDA

supply is independent of whether the digital peripherals are enabled or disabled, being

DDA

is independent from

2. Data based on characterization results, not tested in production unless otherwise specified.

3. Data based on characterization results and tested in production (using one common test limit for sum of I

and I

DDA

58/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol

Table 31. Typical and maximum consumption in Stop and Standby modes

Typ @V

= V

DDA

) Max

(1)

Parameter

Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

85 °C

105 °C

Unit

DDA

Supply current in

Stop mode

Regulator in run mode, all oscillators OFF

Regulator in lowpower mode, all oscillators OFF

Supply current in

Standby mode

LSI ON and IWDG

LSI OFF and IWDG

OFF

Supply current in

Stop mode

Supply current in

Standby mode

Supply current in

Stop mode

Supply current in

Standby mode

Regulator in run mode, all oscillators

OFF

Regulator in low-power mode, all oscillators

OFF

LSI ON and

IWDG ON

LSI OFF and

IWDG OFF

Regulator in run mode, all oscillators

OFF

Regulator in low-power mode, all oscillators

OFF

LSI ON and

IWDG ON

LSI OFF and

IWDG OFF

15.4

15.5

15.6

15.7

15.8

15.9

(2)

3.2

0.8

0.6

2.1

2.5

1.9

1.3

1.7

1.2

3.3

1.0

0.7

2.2

2.7

2.1

1.3

1.8

1.2

3.4

1.1

0.9

2.3

2.8

2.2

1.4

1.9

1.2

3.5

1.2

0.9

2.5

3.0

2.3

1.4

2.0

1.3

3.6

1.3

1.0

2.6

3.2

2.5

1.5

2.1

1.3

3.7

1.4

1.1

2.8

3.5

2.6

1.5

2.2

1.4

(2)

2.1

3.5

(2)

2.6

3.6

3.1

4.6

(2)

1. Data based on characterization results, not tested in production unless otherwise specified.

2. Data based on characterization results and tested in production (using one common test limit for sum of I

and I

DDA

µA

DS9826 Rev 6 59/128

Electrical characteristics STM32F072x8 STM32F072xB

Table 32. Typical and maximum current consumption from the V

BAT

supply

Typ @ V

BAT

Max (1)

Symbol Parameter Conditions

25 °C

85 °C

105 °C

Unit

DD_VBAT

RTC domain supply current

LSE & RTC ON; “Xtal mode”: lower driving capability;

LSEDRV[1:0] = '00'

LSE & RTC ON; “Xtal mode” higher driving capability;

LSEDRV[1:0] = '11'

0.5

0.8

0.6

0.9

1. Data based on characterization results, not tested in production.

0.7

1.1

0.8

1.2

1.1

1.4

1.2

1.6

1.3

1.7

2.1

2.3

2.8

µA

Typical current consumption

The MCU is placed under the following conditions:

• V

= V

DDA

= 3.3 V

• All I/O pins are in analog input configuration

• The Flash memory access time is adjusted to f

HCLK

frequency:

– 0 wait state and Prefetch OFF from 0 to 24 MHz

– 1 wait state and Prefetch ON above 24 MHz

• When the peripherals are enabled, f

PCLK

= f

HCLK

• PLL is used for frequencies greater than 8 MHz

• AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and

500 kHz respectively

60/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 33. Typical current consumption, code executing from Flash memory,

running from HSE 8 MHz crystal

Typical consumption in

Run mode

Typical consumption in

Sleep mode

Symbol Parameter f

HCLK

Unit

Peripherals enabled

Peripherals disabled

Peripherals enabled

Peripherals disabled

DDA

48 MHz

36 MHz

32 MHz

Current consumption from V

DD supply

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

48 MHz

36 MHz

32 MHz

Current consumption from V

DDA supply

24 MHz

16 MHz

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

24.1

18.3

16.5

12.9

8.9

4.8

3.1

2.1

1.6

1.3

163.3

124.3

111.9

87.1

62.5

2.5

13.5

10.5

9.6

7.6

5.3

3.1

2.1

1.6

1.3

1.2

14.6

11.1

10.0

7.8

5.5

3.1

2.2

1.6

1.4

1.2

2.2

1.7

1.2

1.1

3.5

2.9

2.7

1.0

μ A

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 53: I/O static characteristics

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt

DS9826 Rev 6 61/128

Electrical characteristics STM32F072x8 STM32F072xB trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 35: Peripheral current consumption ), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

= V

DDIOx

×

C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

DDIOx

is the I/O supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

+ C

is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

62/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol

Table 34. Switching output I/O current consumption

Parameter Conditions

(1)

I/O toggling frequency (f

)

I/O current consumption

DDIOx

= 3.3 V

C =C

INT

DDIOx

= 3.3 V

EXT

= 0 pF

C = C

INT

+ C

EXT

+ C

DDIOx

= 3.3 V

EXT

= 10 pF

C = C

INT

+ C

EXT

+ C

DDIOx

= 3.3 V

EXT

= 22 pF

C = C

INT

+ C

EXT

+ C

DDIOx

= 3.3 V

EXT

= 33 pF

C = C

INT

+ C

EXT

+ C

DDIOx

= 3.3 V

EXT

= 47 pF

C = C

INT

+ C

EXT

+ C

C = C int

DDIOx

= 2.4 V

EXT

= 47 pF

C = C

INT

+ C

EXT

+ C

C = C int

4 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

48 MHz

4 MHz

8 MHz

16 MHz

24 MHz

16 MHz

24 MHz

4 MHz

8 MHz

16 MHz

24 MHz

4 MHz

8 MHz

16 MHz

4 MHz

8 MHz

16 MHz

24 MHz

1. C

= 7 pF (estimated value).

Typ

0.07

2.188

0.32

0.64

1.25

2.23

4.442

0.49

0.94

0.18

0.37

0.76

1.39

0.15

0.31

0.53

0.92

3.24

5.02

0.81

1.7

2.38

3.99

0.64

1.25

3.67

0.66

1.43

2.45

4.97

Unit mA

DS9826 Rev 6 63/128

Electrical characteristics STM32F072x8 STM32F072xB

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in

Table 35 . The MCU is placed

under the following conditions:

• All I/O pins are in analog mode

• All peripherals are disabled unless otherwise mentioned

• The given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

•

Ambient operating temperature and supply voltage conditions summarized in Table 21:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 35 . The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

AHB

Table 35. Peripheral current consumption

Peripheral Typical consumption at 25 °C

BusMatrix

(1)

CRC

DMA

Flash memory interface

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

SRAM

TSC

All AHB peripherals

2.3

1.9

2.2

1.2

0.9

5.0

52.6

2.2

1.6

5.7

13.0

8.2

8.5

Unit

µA/MHz

64/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

APB

Table 35. Peripheral current consumption (continued)

Peripheral Typical consumption at 25 °C

APB-Bridge

(2)

2.8

ADC (3) 4.1

CAN

CEC

CRS

DAC

(3)

12.4

1.5

0.8

4.7

DEBUG (MCU debug feature)

I2C1

I2C2

PWR

0.1

3.9

4.0

1.3

SPI1

SPI2

SYSCFG & COMP

TIM1

TIM2

TIM3

TIM6

TIM7

8.7

8.5

1.7

14.9

15.5

11.4

2.5

2.3

TIM14

TIM15

TIM16

TIM17

USART1

USART2

USART3

USART4

USB

WWDG

All APB peripherals

5.4

7.2

1.4

182

5.3

9.1

6.6

6.8

17.0

16.7

Unit

µA/MHz

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.

3. The power consumption of the analog part (I

DDA

) of peripherals such as ADC, DAC, Comparators, is not included. Refer to the tables of characteristics in the subsequent sections.

DS9826 Rev 6 65/128

Electrical characteristics STM32F072x8 STM32F072xB

6.3.6 Wakeup time from low-power mode

The wakeup times given in

Table 36 are the latency between the event and the execution of

the first user instruction. The device goes in low-power mode after the WFE (Wait For

Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture.

The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.

During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.

The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.

The wakeup source from Standby mode is the WKUP1 pin (PA0).

All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions .

Symbol Parameter

Table 36. Low-power mode wakeup timings

Typ @V

DD =

DDA

Conditions

= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V

Max Unit t

WUSTOP

Wakeup from Stop mode

Regulator in run mode

Regulator in low power mode t

WUSTANDBY t

WUSLEEP

Wakeup from

Standby mode

Wakeup from Sleep mode

3.2

7.0

60.4

3.1

5.8

55.6

2.9

5.2

53.5

2.9

4.9

4 SYSCLK cycles

2.8

4.6

µs

66/128

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol f

HSE_ext

HSEH

HSEL t w(HSEH) t w(HSEL) t r(HSE) t f(HSE)

Table 37. High-speed external user clock characteristics

Parameter

(1)

User external clock source frequency

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

Min

0.7 V

DDIOx

Typ

Max

DDIOx

0.3 V

DDIOx

Unit

MHz

V ns

DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

1. Guaranteed by design, not tested in production.

Figure 15. High-speed external clock source AC timing diagram tw(HSEH)

VHSEH

VHSEL

90%

10% tr(HSE)

THSE tf(HSE) tw(HSEL) t

MS19214V2

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14

. However,

Symbol

Table 38. Low-speed external user clock characteristics

Parameter

(1) f

LSE_ext

LSEH

LSEL t w(LSEH) t w(LSEL) t r(LSE) t f(LSE)

User external clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

1. Guaranteed by design, not tested in production.

Min

0.7 V

DDIOx

450

Typ

32.768

Max

1000

DDIOx

0.3 V

DDIOx

Unit kHz

V ns

Figure 16. Low-speed external clock source AC timing diagram tw(LSEH)

VLSEH

VLSEL

90%

10% tr(LSE)

TLSE tf(LSE) tw(LSEL) t

MS19215V2

DS9826 Rev 6 67/128

Electrical characteristics

Note:

STM32F072x8 STM32F072xB

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 39 . In the

application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Symbol

Table 39. HSE oscillator characteristics

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit f

OSC_IN

Oscillator frequency

Feedback resistor

HSE current consumption

During startup

(3)

= 3.3 V,

Rm = 30 Ω ,

CL = 10 pF@8 MHz

= 3.3 V,

Rm = 45 Ω ,

CL = 10 pF@8 MHz

= 3.3 V,

Rm = 30 Ω ,

CL = 5 pF@32 MHz

= 3.3 V,

Rm = 30 Ω ,

CL = 10 pF@32 MHz

200

0.4

0.5

0.8

8.5

MHz k Ω mA

= 3.3 V,

Rm = 30 Ω ,

CL = 20 pF@32 MHz

1.5

g m t

SU(HSE)

(4)

Oscillator transconductance

Startup time

Startup

is stabilized

2 -

mA/V ms

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design, not tested in production.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE) startup time

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 17

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

68/128 DS9826 Rev 6

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Figure 17. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

OSC_IN

8 MHz resonator

EXT

(1) OSC_OUT

Bias controlled gain f

HSE

MS19876V1

1. R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in

Table 40 . In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 40. LSE oscillator characteristics (f

LSE

= 32.768 kHz)

Parameter Conditions

(1)

Min

(2)

Typ Max

(2)

Unit

LSE current consumption low drive capability medium-low drive capability medium-high drive capability -

0.5

0.9

1.3

µA g m

Oscillator transconductance high drive capability low drive capability medium-low drive capability medium-high drive capability

1.6

µA/V high drive capability 25 t

SU(LSE)

(3)

Startup time V

DDIOx is stabilized 2 -

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

2. Guaranteed by design, not tested in production.

3. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer s

DS9826 Rev 6 69/128

Electrical characteristics

Note:

STM32F072x8 STM32F072xB

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

Figure 18. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

OSC32_IN f

LSE

32.768 kHz resonator

Drive programmable amplifier

OSC32_OUT

Note:

6.3.8

MS30253V2

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

Internal clock source characteristics

The parameters given in

Table 41 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 24: General operating conditions

. The provided curves are characterization results, not tested in production.

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High-speed internal (HSI) RC oscillator

Symbol

Table 41. HSI oscillator characteristics

(1)

Parameter Conditions f

HSI

TRIM

DuCy

ACC

(HSI)

HSI

Frequency

HSI user trimming step

Duty cycle

Accuracy of the HSI oscillator

= -40 to 105°C

= -10 to 85°C

= 0 to 85°C

= 0 to 70°C

= 0 to 55°C

= 25°C (4)

I t su(HSI)

DDA(HSI)

HSI oscillator startup time

HSI oscillator power consumption

1. V

DDA

= 3.3 V, T

= -40 to 105°C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

4. Factory calibrated, parts not soldered.

Min

45 (2)

-2.8

(3)

-1.9

(3)

-1.9

(3)

-1.3

(3)

-1

(3)

-1

(2)

Typ

Max

(2)

55 (2)

3.8

(3)

2.3

(3)

(2)

100

(2)

Unit

MHz

µs

µA

Figure 19. HSI oscillator accuracy characterization results for soldered parts

MAX

MIN

-40

-1%

-2%

-3%

-4%

-20 0 20 40 60 80 100 120

MS30985V4

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Electrical characteristics STM32F072x8 STM32F072xB

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

Symbol

Table 42. HSI14 oscillator characteristics

(1)

Parameter Conditions Min f

HSI14

TRIM

DuCy

ACC

(HSI14)

HSI14

Frequency

HSI14 user-trimming step

Duty cycle

Accuracy of the HSI14 oscillator (factory calibrated)

(2)

= –40 to 105 °C –4.2

(3)

= –10 to 85 °C –3.2

(3)

= 0 to 70 °C –2.5

(3)

= 25 °C –1

(2)

I t su(HSI14)

DDA(HSI14)

HSI14 oscillator startup time

HSI14 oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

Typ

100 150

(2)

Max Unit

(2)

55 (2)

5.1

(3)

3.1

(3)

2.3

(3)

(2)

MHz

µs

µA

Figure 20. HSI14 oscillator accuracy characterization results

MAX

MIN

-40

-4%

-5%

-20 0 20 40 60 80 100 120

MS30986V2

72/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

High-speed internal 48 MHz (HSI48) RC oscillator

Symbol

Table 43. HSI48 oscillator characteristics

(1)

Parameter Conditions Min f

HSI48

TRIM

Frequency

HSI48 user-trimming step

DuCy

(HSI48)

Duty cycle

ACC

HSI48

Accuracy of the HSI48 oscillator (factory calibrated)

0.09

(2)

45 (2)

= –40 to 105 °C -4.9

(3)

= –10 to 85 °C -4.1

(3)

= 0 to 70 °C -3.8

(3)

= 25 °C -2.8

I t su(HSI48)

DDA(HSI48)

HSI48 oscillator startup time

HSI48 oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

Typ

312

0.14

Max

0.2

(2)

55 (2)

4.7

(3)

3.7

(3)

3.4

(3)

2.9

(2)

350

(2)

Unit

MHz

µs

µA

-40

-4%

-5%

Figure 21. HSI48 oscillator accuracy characterization results

MAX

MIN

-20 0 20 40 60 80 100 120

MS34206V1

DS9826 Rev 6 73/128

Electrical characteristics STM32F072x8 STM32F072xB

Low-speed internal (LSI) RC oscillator

Symbol

Table 44. LSI oscillator characteristics

(1)

Parameter Min f

LSI t su(LSI)

(2)

DDA(LSI)

(2)

Frequency 30

LSI oscillator startup time

LSI oscillator power consumption

1. V

DDA

= 3.3 V, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

Typ

0.75

Max

1.2

Unit kHz

µs

µA

The parameters given in

Table 45 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 24: General operating conditions

Table 45. PLL characteristics

Value

Symbol Parameter Unit

Min Typ Max f

PLL_IN

PLL input clock

(1)

PLL input clock duty cycle

(2)

40 (2)

(2)

8.0

(2)

MHz

% f

PLL_OUT t

LOCK

Jitter

PLL

PLL multiplier output clock

PLL lock time

Cycle-to-cycle jitter -

200

(2)

300

(2)

MHz

1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by f

PLL_OUT

2. Guaranteed by design, not tested in production.

µs ps

74/128

Flash memory

The characteristics are given at T

= –40 to 105 °C unless otherwise specified.

Symbol

Table 46. Flash memory characteristics

Parameter Conditions t

I prog t

ERASE t

16-bit programming time T

= - 40 to +105 °C

Page (2 KB) erase time T

= - 40 to +105 °C

Mass erase time T

= - 40 to +105 °C

Write mode

Supply current

Erase mode

1. Guaranteed by design, not tested in production.

Min

Typ Max

(1)

53.5

Unit

µs ms ms mA mA

DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol

Table 47. Flash memory endurance and data retention

Parameter Conditions

N t

END

RET

Endurance

Data retention

= –40 to +105 °C

1 kcycle

(2)

at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

10 kcycle (2) at T

= 55 °C

1. Data based on characterization results, not tested in production.

2. Cycling performed over the whole temperature range.

Min

(1)

Unit kcycle

Year

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

and

A device reset allows normal operations to be resumed.

The test results are given in Table 48

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

Table 48. EMS characteristics

Parameter Conditions

Level/

Class

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

= 3.3 V, LQFP100, T

= +25 °C, f

HCLK

= 48 MHz, conforming to IEC 61000-4-2

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

= 3.3 V, LQFP100, T

= +25°C, f

HCLK

= 48 MHz, conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

DS9826 Rev 6 75/128

Electrical characteristics STM32F072x8 STM32F072xB

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 49. EMI characteristics

Symbol Parameter

EMI

Conditions

Monitored frequency band

Peak level

= 3.6 V, T

A compliant with

IEC 61967-2

= 25 °C,

LQFP100 package

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

EMI Level

Max vs. [f

HSE

HCLK

]

8/48 MHz

-2

Unit dBµV

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the standards stated in the following table.

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STM32F072x8 STM32F072xB Electrical characteristics

Symbol Ratings

Table 50. ESD absolute maximum ratings

Conditions Packages Class

Maximum value

(1)

Unit

ESD(HBM)

Electrostatic discharge voltage

(human body model)

= +25 °C, conforming to

ANSI/ESDA/JEDEC JS-001

All

ESD(CDM)

Electrostatic discharge voltage

(charge device model)

= +25 °C, conforming to

ANSI/ESDA/JEDEC JS-002

WLCSP49

All others

1. Data based on characterization results, not tested in production.

C2a

2000

250

500

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

Parameter

Table 51. Electrical sensitivities

Conditions

Static latch-up class T

= +105 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

DDIOx product operation. However, in order to give an indication of the robustness of the

(for standard, 3.3 V-capable I/O pins) should be avoided during normal microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in

Table 52 .

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

DS9826 Rev 6 77/128

Electrical characteristics STM32F072x8 STM32F072xB

Symbol

INJ

Table 52. I/O current injection susceptibility

Description

Functional susceptibility

Negative injection

Positive injection

Unit

Injected current on BOOT0 and PF1 pins

Injected current on PC0 pin

Injected current on PA11 and PA12 pins with induced leakage current on adjacent pins less than -1 mA

Injected current on all other FT and FTf pins

Injected current on all other TTa, TC and RST pins

–0

–5

+5 mA

Symbol

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 53 are derived from tests

performed under the conditions summarized in Table 24: General operating conditions

. All

I/Os are designed as CMOS- and TTL-compliant (except BOOT0).

Parameter

Low level input voltage

High level input voltage

V hys

Schmitt trigger hysteresis

Table 53. I/O static characteristics

Conditions Min

TC and TTa I/O

FT and FTf I/O

BOOT0

All I/Os except

BOOT0 pin

TC and TTa I/O

FT and FTf I/O

BOOT0

All I/Os except

BOOT0 pin

TC and TTa I/O

FT and FTf I/O

BOOT0

0.445 V

DDIOx

+0.398

(1)

0.5 V

DDIOx

+0.2

(1)

0.2 V

DDIOx

+0.95

(1)

0.7 V

DDIOx

200

(1)

100 (1)

300

(1)

Typ

Max

0.3 V

DDIOx

+0.07

(1)

0.475 V

DDIOx

–0.2

(1)

0.3 V

DDIOx

–0.3

(1)

Unit

0.3 V

DDIOx

V mV

78/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol

I lkg

Parameter

Input leakage current

(2)

Weak pull-up equivalent resistor

(3)

Table 53. I/O static characteristics (continued)

Conditions Min Typ

TC, FT and FTf I/O

TTa in digital mode

≤ V

DDIOx

TTa in digital mode

DDIOx

≤ V

DDA

TTa in analog mode

≤ V

DDA

FT and FTf I/O

DDIOx

≤ V

≤ 5 V

= V

25 40

Max

± 0.1

± 0.2

Unit

µA k Ω

Weak pull-down equivalent resistor

(3)

= - V

DDIOx

25 40 55 k Ω

I/O pin capacitance 5 -

1. Data based on design simulation only. Not tested in production.

2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 52:

I/O current injection susceptibility

3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 22

for standard I/Os, and in

Figure 23

for

5 V-tolerant I/Os. The following curves are design simulation results, not tested in production.

DS9826 Rev 6 79/128

Electrical characteristics STM32F072x8 STM32F072xB

Figure 22. TC and TTa I/O input characteristics

2.5

(V)

1.5

0.5

1.6

TESTED RANGE

TTL standard requirement

IHmin

= 0.7 V

IHmin

DDIOx

(CMOS standard requirement)

= 0.445 V

DDIOx

+ 0.398

UNDEFINED INPUT RANGE

ILmax

= 0.3 V DDIOx

+ 0.07

ILmax

= 0.3 V DDIOx

(CMOS standard requirement)

TTL standard requirement

TESTED RANGE

1.8

2.0

2.2

2.4

2.6

DDIOx

(V)

2.8

3.0

3.2

Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics

3.4

3.6

MSv32130V4

2.5

(V)

1.5

TESTED RANGE

0.5

1.6

TTL standard requirement

IHmin

= 0.7 V

DDIOx

(CMOS standard requirement)

UNDEFINED INPUT RANGE

IHmin

= 0.5 V

DDIOx

+ 0.2

ILmax

= 0.475 V

DDIOx

- 0.2

TTL standard requirement

ILmax

= 0.3 V DDIOx

(CMOS standard requirement)

TESTED RANGE

1.8

2.0

2.2

2.4

2.6

DDIOx

(V)

2.8

3.0

3.2

3.4

3.6

MSv32131V4

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STM32F072x8 STM32F072xB Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

• The sum of the currents sourced by all the I/Os on V

DDIOx consumption of the MCU sourced on V

Σ I

VDD

, plus the maximum

, cannot exceed the absolute maximum rating

(see Table 21: Voltage characteristics ).

• The sum of the currents sunk by all the I/Os on V

, plus the maximum consumption of the MCU sunk on V

, cannot exceed the absolute maximum rating

Table 21: Voltage characteristics

Σ I

VSS

(see

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions . All I/Os are CMOS- and TTL-compliant (FT, TTa or

TC unless otherwise specified).

Symbol

Table 54. Output voltage characteristics (1)

Parameter Conditions Min Max Unit

(3)

(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

| = 8 mA

DDIOx

≥ 2.7 V

TTL port (2)

| = 8 mA

DDIOx

≥ 2.7 V

| = 20 mA

DDIOx

≥ 2.7 V

| = 6 mA

DDIOx

≥ 2 V

| = 4 mA

DDIOx

–0.4

2.4

DDIOx

–1.3

DDIOx

–0.4

DDIOx

–0.4

0.4

1.3

0.4

OLFm+

(3)

Output low level voltage for an FTf I/O pin in

Fm+ mode

| = 20 mA

DDIOx

≥ 2.7 V

| = 10 mA -

0.4

1. The I

current sourced or sunk by the device must always respect the absolute maximum rating specified in

Table 21:

, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings Σ I

IO.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Data based on characterization results. Not tested in production.

4. Data based on characterization results. Not tested in production.

DS9826 Rev 6 81/128

Electrical characteristics STM32F072x8 STM32F072xB

OSPEEDRy

[1:0] value

(1)

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 24

and

Table 55 , respectively. Unless otherwise specified, the parameters given are derived from

tests performed under the ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions .

Table 55. I/O AC characteristics (1)(2)

Symbol Parameter Conditions Min Max Unit x0

01 f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out

Maximum frequency

(3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

= 50 pF, V

DDIOx

≥ 2 V

= 50 pF, V

DDIOx

< 2 V

= 50 pF, V

DDIOx

≥ 2 V

= 50 pF, V

DDIOx

< 2 V

MHz ns

11 f max(IO)out

Maximum frequency

(3) t f(IO)out t r(IO)out

Output fall time

Output rise time

= 30 pF, V

DDIOx

≥ 2.7 V

= 50 pF, V

DDIOx

≥ 2.7 V

= 50 pF, 2 V ≤ V

DDIOx

< 2.7 V

= 50 pF, V

DDIOx

< 2 V

= 30 pF, V

DDIOx

≥ 2.7 V

= 50 pF, V

DDIOx

≥ 2.7 V

= 50 pF, 2 V ≤ V

DDIOx

< 2.7 V

= 50 pF, V

DDIOx

< 2 V

= 30 pF, V

DDIOx

≥ 2.7 V

= 50 pF, V

DDIOx

≥ 2.7 V

= 50 pF, 2 V ≤ V

DDIOx

< 2.7 V

= 50 pF, V

DDIOx

< 2 V

62.5

125

MHz ns

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STM32F072x8 STM32F072xB Electrical characteristics

Table 55. I/O AC characteristics (1)(2) (continued)

OSPEEDRy

[1:0] value

(1)

Symbol Parameter Conditions Min Max Unit

Fm+ configuration

(4)

f max(IO)out t f(IO)out t r(IO)out f max(IO)out t f(IO)out t r(IO)out t

EXTIpw

Maximum frequency (3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

Pulse width of external signals detected by the

EXTI controller

= 50 pF, V

DDIOx

≥ 2 V

DDIOx

< 2 V

0.5

MHz

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design, not tested in production.

3. The maximum frequency is defined in

Figure 24

4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration.

MHz ns ns

10%

Figure 24. I/O AC characteristics definition

90% 10%

50% 50%

90% t r(IO)out t f(IO)out

T and if the duty cycle is (45-55%)

3 when loaded by C (see the table I/O AC characteristics definition )

MS32132V3

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions .

Symbol

IL(NRST)

IH(NRST)

Table 56. NRST pin characteristics

Parameter

NRST input low level voltage

NRST input high level voltage

Conditions

Min

0.445 V

+0.398

(1)

Typ

Max

0.3 V

+0.07

(1)

Unit

DS9826 Rev 6 83/128

Electrical characteristics STM32F072x8 STM32F072xB

Symbol

Table 56. NRST pin characteristics (continued)

Parameter Conditions Min Typ Max Unit

V hys(NRST)

NRST Schmitt trigger voltage hysteresis

200 -

Weak pull-up equivalent resistor

(2)

= V

25 40 55

F(NRST)

NF(NRST)

NRST input filtered pulse

NRST input not filtered pulse

2.7 < V

< 3.6

2.0 < V

< 3.6

300

500

(3)

100

(1)

1. Data based on design simulation only. Not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).

3. Data based on design simulation only. Not tested in production.

mV k Ω ns ns

Figure 25. Recommended NRST pin protection

External reset circuit

(1)

0.1 μF

NRST

(2)

Filter

Internal reset

MS19878V3

1. The external capacitor protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 56: NRST pin characteristics

. Otherwise the reset will not be taken into account by the device.

Note:

Unless otherwise specified, the parameters given in

Table 57 are derived from tests

performed under the conditions summarized in Table 24: General operating conditions

It is recommended to perform a calibration after each power-up.

Symbol

DDA

DDA (ADC) f

ADC f

(2)

Table 57. ADC characteristics

Parameter

Analog supply voltage for

ADC ON

Current consumption of the ADC (1)

ADC clock frequency

Sampling rate

Conditions

DDA

= 3.3 V

12-bit resolution

Min

2.4

0.6

0.043

Typ

0.9

Max

3.6

Unit

V mA

MHz

84/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol

Table 57. ADC characteristics (continued)

Parameter Conditions Min Typ Max Unit f

TRIG

(2) External trigger frequency f

ADC

= 14 MHz,

12-bit resolution

823 kHz

AIN

(2)

Conversion voltage range

External input impedance

See Equation 1 and

Table 58 for details

DDA

1/f

ADC k

Ω

ADC

(2)

ADC

(2)

Sampling switch resistance

Internal sample and hold capacitor

8 k Ω pF t

CAL

(2)(3) Calibration time f

ADC

= 14 MHz

5.9

µs

1/f

ADC

LATENCY

(2)(4)

Jitter t t t t latr

(2)

ADC

(2)

STAB

(2)

CONV

(2)

ADC_DR register ready latency

ADC clock = HSI14

ADC clock = PCLK/2

ADC clock = PCLK/4

1.5 ADC cycles + 2 f

PCLK

cycles

4.5

8.5

1.5 ADC cycles + 3 f

PCLK

cycles

Trigger conversion latency f

ADC

= f

PCLK

/2 = 14 MHz f

ADC

= f

PCLK f

ADC

= f

PCLK

/4 = 12 MHz f

ADC

= f

PCLK

/4 f

ADC

= f

HSI14

= 14 MHz

ADC jitter on trigger conversion f

ADC

= f

HSI14

Sampling time f

ADC

= 14 MHz

Stabilization time

Total conversion time

(including sampling time)

ADC

= 14 MHz,

12-bit resolution

0.179

0.107

1.5

0.196

0.219

10.5

0.250

17.1

239.5

14 to 252 (t

for sampling +12.5 for successive approximation)

PCLK cycle f

PCLK cycle

µs

1/f

PCLK

µs

1/f

HSI14

µs

1/f

ADC

1/f

ADC

1/f

µs

ADC

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I on I

should be taken into account.

DDA

and 60 µA

2. Guaranteed by design, not tested in production.

3. Specified value includes only ADC timing. It does not include the latency of the register access.

4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.

DS9826 Rev 6 85/128

Electrical characteristics STM32F072x8 STM32F072xB

Equation 1: R

AIN

max formula

AIN

< f

----------------------------------------------------------------

ADC

× C

ADC

× ln ( 2 )

– R

ADC

The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

T s

(cycles)

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

1. Guaranteed by design, not tested in production.

Table 58. R

AIN

max for f

ADC

= 14 MHz t

(µs)

0.11

0.54

0.96

2.04

2.96

3.96

5.11

17.1

AIN

max (k Ω )

(1)

0.4

5.9

11.4

25.2

37.2

Symbol Parameter

Table 59. ADC accuracy (1)(2)(3)

Test conditions

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f f f f

T f

PCLK f

ADC

= 48 MHz,

= 14 MHz, R

AIN

< 10 k Ω

DDA

= 2.7 V to 3.6 V

= - 40 to 105 °C

PCLK

ADC

= 14 MHz, R

DDA

PCLK

ADC

DDA

= 48 MHz,

= 14 MHz, R

AIN

< 10 k Ω

= 2.4 V to 3.6 V

= 25 °C

AIN

< 10 k Ω

= 3 V to 3.6 V

= 25 °C

1. ADC DC accuracy values are measured after internal calibration.

86/128 DS9826 Rev 6

Typ

±0.7

±1.2

±3.3

±1.9

±2.8

±0.7

±1.2

±0.8

±3.3

±1.9

±2.8

±1.3

±1

±0.5

±0.7

Max

(4)

±1.3

±1.7

±4

±2.8

±3

±1.3

±1.7

±1.5

±4

±2.8

±3

±2

±1.5

±1

Unit

LSB

STM32F072x8 STM32F072xB Electrical characteristics

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

Section 6.3.14

does not affect the ADC

3. Better performance may be achieved in restricted V

DDA

, frequency and temperature ranges.

4. Data based on characterization results, not tested in production.

Figure 26. ADC accuracy characteristics

SSA

4095

4094

4093

E O

1 LSB

IDEAL

1 2 3 4 5 6

(2)

(3)

(1)

4093 4094 4095 4096

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

= total unajusted error : maximum deviation

between the actual and ideal transfer curves.

= offset error : maximum deviation

between the first actual transition and

the first ideal one.

= gain error : deviation between the last

ideal transition and the last actual one.

= differential linearity error : maximum

deviation between actual steps and the ideal ones.

= integral linearity error : maximum deviation

between any actual transition and the end point

correlation line.

DDA

MS19880V2

Figure 27. Typical connection diagram using the ADC

DDA

AIN

(1)

AINx

C parasitic

(2) V

L ±1 μA

Sample and hold ADC converter

ADC

12-bit converter

ADC

MS33900V2

1. Refer to Table 57: ADC characteristics

for the values of R

AIN

, R

ADC

and C

ADC

2. C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 this, f

ADC pF). A high C

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 13: Power supply scheme

. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip.

DS9826 Rev 6 87/128

Electrical characteristics STM32F072x8 STM32F072xB

Symbol

DDA

LOAD

(1)

LOAD

(1)

Parameter

Analog supply voltage for

DAC ON

Table 60. DAC characteristics

Min Typ Max Unit

2.4

3.6 V

Resistive load with buffer

Impedance output with buffer OFF

Capacitive load

DAC_OUT min

(1)

Lower DAC_OUT voltage with buffer ON

DAC_OUT max (1)

Higher DAC_OUT voltage with buffer ON

DAC_OUT min

(1)

Lower DAC_OUT voltage with buffer OFF

DAC_OUT max

(1)

Higher DAC_OUT voltage with buffer OFF

0.2 -

0.5

DDA

– 0.2

k Ω Load connected to V

SSA k Ω Load connected to V

DDA k Ω

When the buffer is OFF, the

Minimum resistive load between

DAC_OUT and V

to have a

1% accuracy is 1.5 M Ω pF

Maximum capacitive load at

DAC_OUT pin (when the buffer is ON).

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code (0x0E0) to (0xF1C) at

DDA

= 3.6 V and (0x155) and

(0xEAB) at V

DDA

= 2.4 V mV

DDA

– 1LSB V

Comments

It gives the maximum output excursion of the DAC.

DDA

(1)

DAC DC current consumption in quiescent mode

(2)

600

700

µA

With no load, middle code

(0x800) on the input

With no load, worst code

(0xF1C) on the input

DNL

(3)

INL

(3)

Differential non linearity

Difference between two consecutive code-1LSB)

Integral non linearity

(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)

±0.5

±2

±1

±4

LSB

Given for the DAC in 10-bit configuration

LSB

Given for the DAC in 12-bit configuration

LSB

Given for the DAC in 10-bit configuration

LSB

Given for the DAC in 12-bit configuration

Offset

(3)

Offset error

(difference between measured value at Code

(0x800) and the ideal value

= V

DDA

/2) -

±10

±3

±12 mV

LSB

Given for the DAC in 10-bit at

DDA

= 3.6 V

Given for the DAC in 12-bit at

DDA

= 3.6 V

88/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol

Table 60. DAC characteristics (continued)

Parameter Min Typ Max Unit Comments

Gain error

(3)

Gain error ±0.5

Given for the DAC in 12-bit configuration t

SETTLING

(3) t

Update rate

(3)

WAKEUP

(3)

PSRR+

(1)

Settling time (full scale: for a

10-bit input code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±1LSB

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1LSB)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

Power supply rejection ratio

(to V

DDA

) (static DC measurement

6.5

–67 –40

µs C

MS/s C

µs dB

LOAD

≤ 50 pF, R

LOAD

≥ 5 k Ω input code between lowest and highest possible ones.

No , C

LOAD

≥

5 k

= 50 pF

1. Guaranteed by design, not tested in production.

2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved.

3. Data based on characterization results, not tested in production.

Ω

Figure 28. 12-bit buffered / non-buffered DAC

Buffered/Non-buffered DAC

Buffer

(1)

12-bit digital to analog converter

DAC_OUTx

MS39009V1

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

DS9826 Rev 6 89/128

Electrical characteristics STM32F072x8 STM32F072xB

Symbol

DDA

SC t

S_SC t

START t

V offset dV offset

/dT

DD(COMP)

Parameter

Table 61. Comparator characteristics

Conditions

Analog supply voltage

Comparator input voltage range

REFINT voltage

scaler offset

COMP current consumption

REFINT time

scaler startup time from power down

Comparator startup

Propagation delay for

200 mV step with

100 mV overdrive

Propagation delay for full range step with

100 mV overdrive

Comparator offset error

Offset error temperature coefficient

First V

REFINT power on

scaler activation after device

Next activations

Startup time to reach propagation delay specification

Ultra-low power mode

Low power mode

Medium power mode

High speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Ultra-low power mode

Low power mode

Medium power mode

High speed mode

DDA

≥ 2.7 V

DDA

< 2.7 V

Ultra-low power mode

Low power mode

Medium power mode

High speed mode

Min (1) Typ Max (1)

3.6

0 V

DDA

±5

1000

(2)

0.2

0.7

0.3

4.5

1.5

0.6

100

100 240

0.7

0.3

2.1

1.2

90 180

110 300

±4 ±10

1.2

±10

1.5

100

Unit

mV ms

µs

µs ns

µs ns mV

µV/°C

µA

90/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol

Table 61. Comparator characteristics (continued)

Parameter Conditions Min (1) Typ Max (1)

V hys

No hysteresis

(COMPxHYST[1:0]=00)

High hysteresis

(COMPxHYST[1:0]=11)

Comparator hysteresis

Low hysteresis

(COMPxHYST[1:0]=01)

Medium hysteresis

(COMPxHYST[1:0]=10)

High speed mode

All other power modes

High speed mode

All other power modes

High speed mode

All other power modes

1. Data based on characterization results, not tested in production.

2. For more details and conditions see

Figure 29: Maximum V

REFINT

scaler startup time from power down

Unit mV

1000

Figure 29. Maximum V

REFINT

scaler startup time from power down

2.0V ≤ V

DDA

2.4V ≤ V

DDA

3.0V ≤ V

DDA

< 2.4V

< 3.0V

< 3.6V

100

-40 -20 0 20 40

Temperature (°C)

60 80 100

DS9826 Rev 6 91/128

Electrical characteristics STM32F072x8 STM32F072xB

6.3.19 Temperature sensor characteristics t t

Symbol

(1)

Avg_Slope

START

(1)

S_temp

(1)

Table 62. TS characteristics

Parameter

SENSE

linearity with temperature

Average slope

Voltage at 30 °C (± 5 °C)

(2)

ADC_IN16 buffer startup time

ADC sampling time when reading the temperature

Min

4.0

1.34

Typ

± 1

4.3

1.43

Max

± 2

4.6

1.52

1. Guaranteed by design, not tested in production.

2. Measured at V = 3.3 V ± 10 mV. The V

Temperature sensor calibration values

ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:

Unit

°C mV/°C

µs

6.3.20 V

BAT monitoring characteristics

Symbol

Table 63. V

BAT

monitoring characteristics

Parameter Min

R Resistor bridge for V

BAT

(1) t

S_vbat

(1)

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1. Guaranteed by design, not tested in production.

–1

Typ

2 x 50

Max

Unit k Ω

µs

92/128

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol t res(TIM) f

EXT

Parameter

Table 64. TIMx characteristics

Conditions Min

Timer resolution time

Timer external clock frequency on CH1 to

CH4 t

MAX_COUNT

16-bit timer maximum period

32-bit counter maximum period

TIMxCLK

= 48 MHz

TIMxCLK

= 48 MHz

TIMxCLK

= 48 MHz

TIMxCLK

= 48 MHz

Typ

20.8

TIMxCLK

1365

89.48

Max

Unit t

TIMxCLK ns

MHz

MHz t

TIMxCLK

µs t

TIMxCLK s

DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 65. IWDG min/max timeout period at 40 kHz (LSI) (1)

Prescaler divider PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

/16

/32

/64

/128

/256

6 or 7

0.1

0.2

0.4

0.8

1.6

3.2

6.4

409.6

819.2

1638.4

3276.8

6553.6

13107.2

26214.4

1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler

Table 66. WWDG min/max timeout value at 48 MHz (PCLK)

WDGTB Min timeout value Max timeout value

0.0853

0.1706

0.3413

0.6826

5.4613

10.9226

21.8453

43.6906

Unit ms

I

C interface characteristics

The I

C interface meets the timings requirements of the I

C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I 2 C timings requirements are guaranteed by design when the I2Cx peripheral is properly configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIOx

is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to

Section 6.3.14: I/O port characteristics for the I

2 C I/Os characteristics.

All I 2 C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

DS9826 Rev 6 93/128

Electrical characteristics STM32F072x8 STM32F072xB

Symbol

Table 67. I 2 C analog filter characteristics (1)

Parameter t

Maximum width of spikes that are suppressed by the analog filter

1. Guaranteed by design, not tested in production.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Min

(2)

Max

260

(3)

Unit ns

SPI/I

S characteristics

Unless otherwise specified, the parameters given in

Table 68 for SPI or in

Table 69 for I

S are derived from tests performed under the ambient temperature, f

PCLKx

frequency and

supply voltage conditions summarized in Table 24: General operating conditions

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I

S).

Symbol Parameter

Table 68. SPI characteristics

(1)

Conditions Min Max Unit

1/t t t f

SCK c(SCK) t r(SCK) t f(SCK) t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) su(SI) h(MI) t h(SI) t a(SO)

(2) t dis(SO)

(3) t t v(SO) t v(MO) t h(SO) h(MO)

DuCy(SCK)

SPI clock frequency

Master mode

Slave mode

SPI clock rise and fall time

NSS setup time

NSS hold time

SCK high and low time

Capacitive load: C = 15 pF

Slave mode

Master mode, f

PCLK presc = 4

= 36 MHz,

Master mode

Data input setup time

Data input hold time

Slave mode

Master mode

Slave mode

Data output access time Slave mode, f

PCLK

= 20 MHz

Data output disable time Slave mode

Data output valid time Slave mode (after enable edge)

Data output valid time

Data output hold time

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

SPI slave input clock duty cycle

Slave mode

4Tpclk

2Tpclk + 10

Tpclk/2 -2

11.5

3Tpclk

22.5

Tpclk/2 + 1

MHz ns ns

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

94/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Figure 30. SPI timing diagram - slave mode and CPHA = 0

NSS input t su(NSS) t w(SCKH) t c(SCK) t r(SCK) t h(NSS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t w(SCKL)

First bit OUT t h(SI) t v(SO) t h(SO)

Next bits OUT t f(SCK)

Last bit OUT t dis(SO) t su(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

Figure 31. SPI timing diagram - slave mode and CPHA = 1

NSS input t su(NSS) t w(SCKH) t c(SCK) t f(SCK) t h(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO output

MOSI input t a(SO) t w(SCKL) t v(SO) t su(SI)

First bit OUT t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

MSv41659V1

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

DS9826 Rev 6 95/128

Electrical characteristics STM32F072x8 STM32F072xB

Figure 32. SPI timing diagram - master mode

NSS input

High tc(SCK)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

B I T1 OUT th(MO)

1. Measurement points are done at CMOS levels: 0.3 V

and 0.7 V

Symbol f

1/t c(CK) t r(CK) t f(CK) t w(CKH) t w(CKL) t v(WS) t h(WS) t su(WS) t h(WS)

DuCy(SCK)

Parameter

Table 69. I

S characteristics

(1)

Conditions

S clock frequency

Master mode (data: 16 bits, Audio frequency = 48 kHz)

Slave mode

S clock rise time

S clock fall time

S clock high time

I 2 S clock low time

WS valid time

WS hold time

WS setup time

WS hold time

S slave input clock duty cycle

Capacitive load C

= 15 pF

Master f

PCLK

= 16 MHz, audio frequency = 48 kHz

Master mode

Slave mode

Slave mode tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136c

Min

1.597

306

312

Max

1.601

6.5

Unit

MHz ns

96/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol

Table 69. I 2 S characteristics (1) (continued)

Parameter Conditions t su(SD_MR) t su(SD_SR) t h(SD_MR)

(2) t h(SD_SR)

(2) t v(SD_MT)

(2) t v(SD_ST)

(2) t h(SD_MT) t h(SD_ST)

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master receiver

Slave receiver

Master receiver

Slave receiver

Master transmitter

Slave transmitter

Master transmitter

Slave transmitter

1. Data based on design simulation and/or characterization results, not tested in production.

2. Depends on f

PCLK

. For example, if f

PCLK

= 8 MHz, then T

PCLK

= 1/f

PLCLK

= 125 ns.

Figure 33. I 2 S slave timing diagram (Philips protocol) tc(CK)

Min

0.5

Max

CPOL = 0

Unit ns

CPOL = 1 tw(CKH) tw(CKL) th(WS)

WS input

SDtransmit tsu(WS)

LSB transmit(2) tsu(SD_SR)

LSB receive(2)

MSB transmit

MSB receive tv(SD_ST)

Bitn transmit th(SD_SR)

Bitn receive th(SD_ST)

LSB receive SDreceive

MSv39721V1

1. Measurement points are done at CMOS levels: 0.3 × V

DDIOx and 0.7 × V

DDIOx

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DS9826 Rev 6 97/128

Electrical characteristics STM32F072x8 STM32F072xB

Figure 34. I 2 S master timing diagram (Philips protocol)

90%

10% tf(CK) tr(CK) tc(CK)

CPOL = 0

CPOL = 1 tv(WS)

WS output tw(CKH)

SDtransmit

SDreceive tw(CKL) th(WS) tv(SD_MT)

LSB transmit(2) tsu(SD_MR)

LSB receive(2)

MSB transmit

MSB receive

Bitn transmit th(SD_MR)

Bitn receive th(SD_MT)

LSB transmit

LSB receive

MSv39720V1

1. Data based on characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

98/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

USB characteristics

The STM32F072x8/xB USB interface is fully compliant with the USB specification version

2.0 and is USB-IF certified (for Full-speed device operation).

Symbol

Table 70. USB electrical characteristics

Parameter Conditions Min.

Typ Max.

Unit t

DDIO2

STARTUP

(2)

PUI

PUR

USB transceiver operating voltage

USB transceiver startup time

Embedded USB_DP pull-up value during idle

Embedded USB_DP pull-up value during reception

3.0

(1)

1.1

2.0

1.26

2.26

3.6

1.0

1.5

2.6

µs k

Ω

DRV

(2)

Output driver impedance

(3)

Driving high and low

28 40 44

1. The STM32F072x8/xB USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V voltage range.

2. Guaranteed by design, not tested in production.

3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver.

Ω

CAN (controller area network) interface

Refer to Section 6.3.14: I/O port characteristics

for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX).

DS9826 Rev 6 99/128

Package information STM32F072x8 STM32F072xB

7.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

UFBGA100 package information

UFBGA100 is a 100-ball, 7 × 7 mm, 0.50 mm pitch, ultra-fine-profile ball grid array package.

Figure 35. UFBGA100 package outline

Z Seating plane ddd Z

A3 A2 e

A1 A

A1 ball identifier

A1 ball index area

12 e

BOTTOM VIEW

Øb (100 balls)

Ø eee

M Z Y X

Ø fff M Z

TOP VIEW

A0C2_ME_V5

1. Drawing is not to scale.

Symbol

Min.

A -

A1 -

A2 -

A3 -

Table 71. UFBGA100 package mechanical data millimeters inches

(1)

Typ.

Max.

Min.

0.110 -

0.450 -

0.130

Typ.

Max.

0.0177

0.0051

0.0236

0.0043

0.0094

0.0126 -

100/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

Symbol

Table 71. UFBGA100 package mechanical data (continued) millimeters inches (1)

Min.

Typ.

Max.

Min.

Typ.

Max.

0.2165 -

e 0.500

Z ddd eee -

fff -

0.750

0.080

0.150

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.2165 -

0.0295

Figure 36. Recommended footprint for UFBGA100 package

0.0031

0.0059

0.0020

Dpad

Dsm

A0C2_FP_V1

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

Table 72. UFBGA100 recommended PCB design rules

Dimension Recommended values

0.5

0.280 mm

0.370 mm typ. (depends on the solder mask registration tolerance)

0.280 mm

Between 0.100 mm and 0.125 mm

DS9826 Rev 6 101/128

124

Package information STM32F072x8 STM32F072xB

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 37. UFBGA100 package marking example

Product identification (1)

STM32F

072VBH6

Date code

Pin 1 identification

Y WW

Revision code

MS35585V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

102/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

LQFP100 is a100-pin, 14 × 14 mm low-profile quad flat package.

Figure 38. LQFP100 package outline

SEATING PLANE

C c

0.25 mm

GAUGE PLANE ccc C

L K

75 51

100

PIN 1

IDENTIFICATION

1 25 e c

A2 b

1. Drawing is not to scale.

Table 73. LQPF100 package mechanical data millimeters inches

(1)

Symbol

Min

0.050

1.350

0.170

0.090

15.800

13.800

15.800

Typ

1.400

0.220

16.000

14.000

12.000

16.000

Max

1.600

0.150

1.450

0.270

0.200

16.200

14.200

16.200

Min

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

0.6220

Typ

0.0551

0.0087

0.6299

0.5512

0.4724

0.6299

1L_ME_V5

Max

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

0.6378

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124

Package information STM32F072x8 STM32F072xB

Table 73. LQPF100 package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 k ccc

E3 e

13.800

0.450

0.0°

14.000

12.000

0.500

0.600

1.000

3.5°

14.200

0.750

7.0°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.5433

0.0177

0.0°

Typ

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

Figure 39. Recommended footprint for LQFP100 package

75 51

Max

0.5591

0.0295

7.0°

0.0031

76 50

0.5

0.3

16.7

14.3

100

12.3

16.7

1.2

1. Dimensions are expressed in millimeters.

ai14906c

104/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 40. LQFP100 package marking example

STM32F072

VBT6 R

Product identification

(1)

Revision code

Date code

Y WW

Pin 1 identification

MS35586V1

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124

Package information

7.3 UFBGA64 package information

STM32F072x8 STM32F072xB

UFBGA64 is a 64-ball, 5 × 5 mm, 0.5 mm pitch ultra-fine-profile ball grid array package.

Z Seating plane

A3 A2 e

Figure 41. UFBGA64 package outline

F ddd Z

A1 A

A1 ball identifier

A1 ball index area

106/128

D1 D e

8 1

BOTTOM VIEW

Øb (64 balls)

Ø eee fff

Z Y X

TOP VIEW

A4 b

E1 e

1. Drawing is not to scale.

Table 74. UFBGA64 package mechanical data millimeters inches

(1)

Symbol

Min

0.460

0.050

0.400

0.080

0.270

0.170

4.850

3.450

4.850

3.450

0.700

Typ

0.530

0.080

0.450

0.130

0.320

0.280

5.000

3.500

5.000

3.500

0.500

0.750

Max

0.600

0.110

0.500

0.180

0.370

0.330

5.150

3.550

5.150

3.550

0.800

Min

0.0181

0.0020

0.0157

0.0031

0.0106

0.0067

0.1909

0.1358

0.1909

0.1358

0.0276

Typ

0.0209

0.0031

0.0177

0.0051

0.0126

0.0110

0.1969

0.1378

0.1969

0.1378

0.0197

0.0295

A019_ME_V1

Max

0.0236

0.0043

0.0197

0.0071

0.0146

0.0130

0.2028

0.1398

0.2028

0.1398

0.0315

DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

Table 74. UFBGA64 package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

A ddd eee fff

0.460

0.530

0.600

0.080

0.150

0.050

0.0181

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Typ

0.0209

Max

0.0236

0.0031

0.0059

0.0020

Figure 42. Recommended footprint for UFBGA64 package

Dpad

Dsm

A019_FP_V2

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

Pad trace width

Table 75. UFBGA64 recommended PCB design rules

Dimension Recommended values

0.5

0.280 mm

0.370 mm typ. (depends on the soldermask registration tolerance)

0.280 mm

Between 0.100 mm and 0.125 mm

0.100 mm

DS9826 Rev 6 107/128

124

Package information STM32F072x8 STM32F072xB

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 43. UFBGA64 package marking example

Product identification (1)

ES72RBH6

Date code

Y WW

Revision code

Ball 1 identification

MS35587V1

108/128 DS9826 Rev 6

STM32F072x8 STM32F072xB

7.4 LQFP64 package information

LQFP64 is a 64-pin, 10 × 10 mm low-profile quad flat package.

SEATING PLANE

Figure 44. LQFP64 package outline

Package information

0.25 mm

GAUGE PLANE ccc C

K D

D3 L1

48 33

32 b

64 17

PIN 1

IDENTIFICATION

1 e

16 c

A2 b

1. Drawing is not to scale.

Table 76. LQFP64 package mechanical data millimeters inches

(1)

Symbol

Min

0.050

1.350

0.170

0.090

Typ

1.400

0.220

12.000

10.000

7.500

12.000

10.000

Max

1.600

0.150

1.450

0.270

0.200

Min

0.0020

0.0531

0.0067

0.0035

Typ

0.0551

0.0087

0.4724

0.3937

0.2953

0.4724

0.3937

5W_ME_V3

Max

0.0630

0.0059

0.0571

0.0106

0.0079

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124

Package information STM32F072x8 STM32F072xB

Table 76. LQFP64 package mechanical data (continued) millimeters inches (1)

Symbol

Min Typ Max Min

L1 ccc

E3 e

0°

0.450

7.500

0.500

3.5°

0.600

1.000

7°

0.750

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0°

0.0177

Typ

0.2953

0.0197

3.5°

0.0236

0.0394

Figure 45. Recommended footprint for LQFP64 package

Max

7°

0.0295

0.0031

0.5

0.3

12.7

10.3

1.2

7.8

12.7

16 ai14909c

1. Dimensions are expressed in millimeters.

110/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 46. LQFP64 package marking example

Revision code

Product identification (1)

STM32F072

RBT6

Y WW

Date code

Pin 1 identification

MS35588V1

DS9826 Rev 6 111/128

124

Package information

7.5 WLCSP49 package information

STM32F072x8 STM32F072xB

WLCSP49 is a 49-ball, 3.277 × 3.109 mm, 0.4 mm pitch wafer-level chip-scale package.

G e

F e1

Figure 47. WLCSP49 package outline

A1 ball location e2 E bbb Z

Detail A

Side view

A3 e

Bump side

Front view

Bump eee Z

A1 orientation reference

E aaa

(4X)

Wafer back side

1. Drawing is not to scale.

Detail A

(rotated 90 °)

Seating plane

A0XL_ME_V1

112/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

Table 77. WLCSP49 package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ

G aaa e e1 e2

A3 (2) b

(3)

E bbb ccc ddd eee

0.525

0.220

3.242

3.074

0.555

0.175

0.380

0.025

0.250

3.277

3.109

0.400

2.400

0.4385

0.3545

0.585

0.280

3.312

3.144

0.100

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0207

0.0087

0.1276

0.1210

0.0173

0.0140

0.0219

0.0069

0.0150

0.0010

0.0098

0.1290

0.1224

0.0157

0.0945

Max

0.0039

0.0020

0.0230

0.0110

0.1304

0.1238

DS9826 Rev 6 113/128

124

Package information STM32F072x8 STM32F072xB

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 48. WLCSP49 package marking example

Pin 1 identification

Product identification

(1)

F072CBY

Date code

Y WW R

Revision code

MS35591V1

114/128 DS9826 Rev 6

STM32F072x8 STM32F072xB

7.6 LQFP48 package information

LQFP48 is a 48-pin, 7 × 7 mm low-profile quad flat package.

SEATING

PLANE

Figure 49. LQFP48 package outline

Package information ccc C b

0.25 mm

GAUGE PLANE

PIN 1

IDENTIFICATION

1. Drawing is not to scale.

12 e

5B_ME_V2

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124

Package information STM32F072x8 STM32F072xB

Table 78. LQFP48 package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min e

E3 k ccc b c

0.050

1.350

0.170

0.090

8.800

6.800

8.800

6.800

0.450

0°

1.400

0.220

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

1.600

0.150

1.450

0.270

0.200

9.200

7.200

9.200

7.200

0.750

7°

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.3465

0.2677

0.0177

0°

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

Typ

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

0.0551

0.0087

0.3543

0.2756

Figure 50. Recommended footprint for LQFP48 package

0.50

1.20

0.30

36 25

Max

0.3622

0.2835

0.0295

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

0.20

7.30

9.70

5.80

7.30

1 12

1.20

5.80

9.70

ai14911d

1. Dimensions are expressed in millimeters.

116/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 51. LQFP48 package marking example

Product identification (1)

STM32

F072CBT6

Date code

Pin 1 identification

Y WW

Revision code

MS35589V1

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124

Package information

7.7 UFQFPN48 package information

STM32F072x8 STM32F072xB

UFQFPN48 is a 48-lead, 7 × 7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.

Pin 1 identifier laser marking area

Figure 52. UFQFPN48 package outline

E E

Y e b

Detail Y ddd

Seating plane

Exposed pad area

C 0.500x45° pin1 corner

Detail Z

R 0.125 typ.

A0B9_ME_V3

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground.

118/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

Table 79. UFQFPN48 package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min

T b e ddd

0.500

0.000

6.900

5.500

0.300

0.200

0.550

0.020

7.000

5.600

0.400

0.152

0.250

0.500

0.600

0.050

7.100

5.700

0.500

0.300

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

0.2717

0.2165

0.0118

0.0079

Typ

0.0217

0.0008

0.2756

0.2205

0.0157

0.0060

0.0098

0.0197

Figure 53. Recommended footprint for UFQFPN48 package

Max

0.0236

0.0020

0.2795

0.2244

0.0197

0.0118

0.0031

7.30

6.20

48 37

7.30

6.20

0.20

0.30

0.55

5.60

5.80

1. Dimensions are expressed in millimeters.

5.60

0.50

0.75

5.80

A0B9_FP_V2

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124

Package information STM32F072x8 STM32F072xB

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

Figure 54. UFQFPN48 package marking example

Product identification

(1)

STM32F

072CBU6

Date code

Y WW

Pin 1 identification

Revision code

MS35590V1

120/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

The maximum chip junction temperature (T

Table 24: General operating conditions .

max) must never exceed the values given in

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

max = T

max + (P

max x Θ

)

Where:

• T

max is the maximum ambient temperature in °C,

• Θ

is the package junction-to-ambient thermal resistance, in °C/W,

• P

max is the sum of P

INT

max and P

I/O max (P

max = P

INT

max + P

I/O max),

• P

INT

max is the product of I internal power.

DD and V

, expressed in Watts. This is the maximum chip

I/O

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (V

× I

) + Σ ((V

DDIOx

– V

) × I

), taking into account the actual V

OL application.

/ I

and V

/ I

OH of the I/Os at low and high level in the

Symbol

Table 80. Package thermal characteristics

Parameter

Thermal resistance junction-ambient

UFBGA100 - 7 × 7 mm

Thermal resistance junction-ambient

LQFP100 - 14 × 14 mm

Thermal resistance junction-ambient

UFBGA64 - 5 × 5 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 × 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP48 - 7 × 7 mm

Thermal resistance junction-ambient

UFQFPN48 - 7 × 7 mm

Thermal resistance junction-ambient

WLCSP49 - 0.4 mm pitch

Value

Unit

°C/W

7.8.2

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8: Ordering information .

DS9826 Rev 6 121/128

124

Package information

Note:

STM32F072x8 STM32F072xB

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F072x8/xB at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum temperature T

Amax

= 82 °C (measured according to JESD51-2), I

DDmax

= 50 mA, V

DD with I

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with I

= 8 mA, V

= 0.4 V and maximum 8 I/Os used at the same time in output at low level

= 20 mA, V

= 1.3 V

INTmax

= 50 mA × 3.5 V= 175 mW

IOmax

= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

This gives: P

INTmax

= 175 mW and P

IOmax

= 272 mW:

Dmax

= 175 + 272 = 447 mW

Using the values obtained in Table 80

Jmax

is calculated as follows:

– For LQFP64, 45 °C/W

Jmax

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C

This is within the range of the suffix 6 version parts (–40 < T

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Section 8: Ordering information

With this given P

Dmax

we can find the T

Amax

allowed for a given device temperature range

(order code suffix 6 or 7).

Suffix 6: T

Amax

= T

Jmax

- (45°C/W × 447 mW) = 105-20.115 = 84.885 °C

Suffix 7: T

Amax

= T

Jmax

- (45°C/W × 447 mW) = 125-20.115 = 104.885 °C

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high temperatures with a low dissipation, as long as junction temperature T

J range.

remains within the specified

Assuming the following application conditions:

Maximum temperature T

Amax

20 mA, V

= 8 mA, V

= 0.4 V

= 100 °C (measured according to JESD51-2), I

DDmax

= 3.5 V, maximum 20 I/Os used at the same time in output at low level with

INTmax

= 20 mA × 3.5 V= 70 mW

IOmax

= 20 × 8 mA × 0.4 V = 64 mW

This gives: P

INTmax

= 70 mW and P

IOmax

= 64 mW:

Dmax

= 70 + 64 = 134 mW

Thus: P

Dmax

= 134 mW

122/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Package information

Using the values obtained in Table 80

Jmax

is calculated as follows:

– For LQFP64, 45 °C/W

Jmax

= 100 °C + (45 °C/W × 134 mW) = 100 °C + 6.03 °C = 106.03 °C

This is above the range of the suffix 6 version parts (–40 < T

< 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Section 8: Ordering information

) unless we reduce the power dissipation in order to be able to use suffix 6 parts.

Refer to Figure 55 to select the required temperature range (suffix 6 or 7) according to your

temperature or power requirements.

Figure 55. LQFP64 P

max versus T

700

600

500

400

300

200

100

65 75 85 95 105 115 125 135

(°C)

Suffix 6

Suffix 7

MSv32143V1

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124

Ordering information STM32F072x8 STM32F072xB

Example :

Device family

STM32 = Arm-based 32-bit microcontroller

Product type

F = General-purpose

Sub-family

072 = STM32F072xx

Pin count

C = 48/49 pins

R = 64 pins

V = 100 pins

User code memory size

8 = 64 Kbyte

B = 128 Kbyte

Package

H = UFBGA

T = LQFP

U = UFQFPN

Y = WLCSP

Temperature range

6 = –40 to 85 °C

7 = –40 to 105 °C

STM32 F 072 R 8 T 6 x

Options xxx = code ID of programmed parts (includes packing type)

TR = tape and reel packing blank = tray packing

For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office.

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STM32F072x8 STM32F072xB Revision history

Date

13-Jan-2014

21-Feb-2014

18-Sep-2015

Table 81. Document revision history

Revision Changes

Initial release.

Updated “Reset and power management“ data in Features .

Updated t voltage.

S_vrefint in Table: Embedded internal reference

Updated V

HSEH

and V

HSEL

in Table: High-speed external user clock characteristics.

Updated V

LSEH

and V

LSEL

in Table: Low-speed external user clock characteristics.

Updated t

S_temp in Table: TS characteristics.

Updated t

S_vbat in Table: VBAT monitoring characteristics .

Updated Section: I

C interface characteristics .

Updated Figure: UFBGA100 package top view and Figure:

WLCSP49 package top view .

Modified value of t s_sc and removed row V

Comparator characteristics.

in Table:

Section 2: Description:

– Figure 1: Block diagram - AF number corrected

– UFBGA64 package added

Section 3: Functional overview :

– Table 7: Timer feature comparison - added number of complementary outputs for TIM1, 15, 16 and TIM17

Section 4: Pinouts and pin descriptions : UFBGA64 added

Section 5: Memory mapping :

– Figure 10: STM32F072xB memory map updated

Section 6: Electrical characteristics :

– Table 21: Voltage characteristics and Table 22: Current characteristics updated

– Table 24: General operating conditions - footnote for V

– Table 28: Embedded internal reference voltage - t

START parameter added

– Table 31: Typical and maximum consumption in Stop and

Standby modes updated

– Merger of tables 33 and 34 into Table 33: Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal

– Table 37: High-speed external user clock characteristics: replaced V

with V

DDIOX

– Table 38: Low-speed external user clock characteristics and Table 40: LSE oscillator characteristics (f

LSE kHz): replaced V

with V

DDIOX

= 32.768

– Table 41: HSI oscillator characteristics and Figure 19: HSI oscillator accuracy characterization results for soldered parts updated

DS9826 Rev 6 125/128

127

Revision history

Date

18-Sep-2015

17-Dec-2015

STM32F072x8 STM32F072xB

Table 81. Document revision history (continued)

Revision Changes

3 (continued)

– Table 42: HSI14 oscillator characteristics: changed the min value for ACC

HSI14

– Table 46: Flash memory characteristics: removed V prog

– Table 49: EMI characteristics updated

– Table 50: ESD absolute maximum ratings updated

– Table 57: ADC characteristics - updated some parameter values, test conditions and added footnotes

(3)

and

(4)

– Table 60: DAC characteristics - I

DDA current consumption) updated

max value (DAC DC

– Table 61: Comparator characteristics: changed the description and values for t

S_SC

parameter

– Table 62: TS characteristics: changed the min value for t

S-temp

– Table 63: VBAT monitoring characteristics: changed the typical value for R parameter

– Table 69: I

S characteristics: updated the min value for data input hold time (master and slave receiver)

Section 7: Package information:

– information generally updated, UFBGA64 added

Section 8: Part numbering: UFBGA64 added

Section 2: Description :

–

Figure 1: Block diagram

updated

Section 3: Functional overview :

–

Figure 2: Clock tree updated

Section 5: Pinouts and pin descriptions

– Package pinout figures updated (look and feel)

–

Figure 10: WLCSP49 package pinout

- now presented in top view

Section 4: Memory mapping :

– added information on STM32F072x8 difference versus

STM32F072xB map in

Figure 3

–

Table 28: Embedded internal reference voltage : removed

-40°-to-85° condition for V

REFINT and associated note

Section 6: Electrical characteristics

–

Table 61: Comparator characteristics - min value for V

DDA replaced with V

–

Figure 29: Maximum V

REFINT power down added

scaler startup time from

–

Table 53: I/O static characteristics - note removed

–

Table 69: I

S characteristics

: table reorganized

Section 8: Ordering information

– added tray packing to options

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STM32F072x8 STM32F072xB

Date

10-Jan-2017

03-Sep-2019

Revision history

Table 81. Document revision history (continued)

Revision Changes

Section 6: Electrical characteristics

–

Table 40: LSE oscillator characteristics (f

LSE

= 32.768 kHz)

- information on configuring different drive capabilities removed. See the corresponding reference manual.

–

Table 28: Embedded internal reference voltage - V

REFINT values

–

Table 60: DAC characteristics - min. R

LOAD

to V

DDA

defined

–

Figure 30: SPI timing diagram - slave mode and CPHA = 0 and Figure 31: SPI timing diagram - slave mode and CPHA

= 1 enhanced and corrected

Section 8: Ordering information

– The name of the section changed from the previous “Part numbering”

Section 6: Electrical characteristics

–

Table 50: ESD absolute maximum ratings

- information on test standards and classes modified.

– Memory and peripheral mapping moved before pinout information

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STM32F072x8 STM32F072xB

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