STM32F072x8 STM32F072xB Functional overview
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate withTIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and independent DMA request generation.
Their counters can be frozen in debug mode.
3.14.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
3.14.5 System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode.
This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:
• a 24-bit down counter
• autoreload capability
• maskable system interrupt generation when the counter reaches 0
• programmable clock source (HCLK or HCLK/8)
The RTC and the five backup registers are supplied through a switch that takes power either on V
DD
supply when present or through the V
BAT
pin. The backup registers are five 32-bit registers used to store 20 bytes of user application data when V
DD
power is not present.
They are not reset by a system or power reset, or at wake up from Standby mode.
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Functional overview STM32F072x8 STM32F072xB
The RTC is an independent BCD timer/counter. Its main features are the following:
• calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format
• automatic correction for 28, 29 (leap year), 30, and 31 day of the month
• programmable alarm with wake up from Stop and Standby mode capability
• Periodic wakeup unit with programmable resolution and period.
• on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize the RTC with a master clock
• digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy
• Three anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection
• timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection
• reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision
The RTC clock sources can be:
• a 32.768 kHz external crystal
• a resonator or oscillator
• the internal low-power RC oscillator (typical frequency of 40 kHz)
• the high-speed external clock divided by 32
circuit interface (I
2
C)
Up to two I 2 C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode
Plus (up to 1 Mbit/s) with 20 mA output drive on most of the associated I/Os.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). They also include programmable analog and digital noise filters.
Table 8. Comparison of I 2 C analog and digital filters
Aspect
Pulse width of suppressed spikes
Benefits
Drawbacks
Analog filter
≥ 50 ns
Available in Stop mode
Variations depending on temperature, voltage, process
Digital filter
Programmable length from 1 to 15
I2Cx peripheral clocks
–Extra filtering capability vs.
standard requirements
–Stable length
Wakeup from Stop on address match is not available when digital filter is enabled.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
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