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STAC2942B
Datasheet
HF/VHF/UHF RF power N-channel MOSFET
1
1
2
Pin
1
2
3
3
3
STAC780-4B
Pin connection
Connection
Drain
Source (bottom side)
Gate
Features
Order code
STAC2942BW
Frequency
175 MHz
V
DD
50 V
P
OUT
350 W
• Gold metallization
• Excellent thermal stability
• Common source push-pull configuration
• P
OUT
= 350 W min. with 21 dB gain at 175 MHz
• In compliance with the 2002/95/EC European directive
• ST air-cavity STAC packaging technology
Gain
21 dB
Efficiency
60 %
Description
The STAC2942B is a gold metallized N-channel MOS field-effect RF power transistor, intended for use in 50 V DC large signal applications up to 250 MHz.
Product status link
STAC2942B
Product summary
Order code STAC2942BW
Marking
Package
Packing
Base / Bulk qty
STAC2942
STAC780-4B
Box
20 / 80
DS6158 - Rev 8 - April 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1
1.1
1.2
1.3
STAC2942B
Electrical data
Electrical data
Maximum ratings
Table 1. Absolute maximum ratings (T
CASE
= 25 °C)
Symbol
V
(BR)DSS
V
DRG
V
GS
I
D
P
DISS
T
J
T
STG
1. T
J
= 150 °C
Drain source voltage
Drain-gate voltage (R
GS
= 1 MΩ)
Gate-source voltage
Drain current
Power dissipation
Parameter
Maximum operating junction temperature
Storage temperature range
Thermal data
Value
130
130
±20
40
625
200
-65 to +150
Symbol
R thJC
Junction-case thermal resistance
Table 2. Thermal data
Parameter
ESD protection characteristics
Symbol
HBM
Table 3. ESD protection
Test Methodology
Human Body Model (per JESD22-A114)
Value
0.28
Unit
°C/W
Class
2
Unit
V
V
V
A
W
°C
°C
DS6158 - Rev 8 page 2/16
2
2.1
2.2
Electrical characteristics
( T
CASE
= +25 °C, unless otherwise specified)
Static
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(Q)
V
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
Dynamic
Table 4. Static (per side)
Drain - Source Breakdown voltage
Parameter Test conditions
V
GS
= 0 V, I
DS
= 100 mA,
T
J
= 150 °C
Zero gate voltage drain
Leakage Current
Gate - Source leakage current
Gate quiescent voltage
Drain - Source on voltage
Forward transconductance
Input capacitance
Ouput capacitance
Reverse transfer capacitance
V
GS
= 0 V, V
DS
= 50 V
V
GS
= 20 V, V
DS
= 0 V
V
DS
= 10 V, I
D
= 250 mA
V
GS
= 10 V, I
D
= 10 A
V
DS
= 10 V, I
D
= 5 A
V
DS
= 50 V, f = 1 MHz
Min.
130
1.5
5
Symbol
P
OUT ŋ
D
VSWR
Parameter
Output power
Drain efficiency
Load mismatch
Table 5. Dynamic
Test conditions
P
IN
= 4 W
P
IN
= 4 W
P
OUT
= 350 W, all phases angles
Min.
350
60
Typ.
Max.
2.5
425
202
12
100
250
4.0
3
Unit
V
μA nA
V
V
S pF pF pF
Typ.
450
75
Max.
-
-
5:1
Unit
W
%
1. F = 175 MHz, V
DD
= 50 V, I
DQ
= 2 X 250 mA.
STAC2942B
Electrical characteristics
DS6158 - Rev 8 page 3/16
3
Impedance
Figure 1. Current conventions
STAC2942B
Impedance
Note:
Freq. (MHz)
175
Table 6. Impedance data
Z
IN
(Ω)
2.0 - j2.0
Measured gate-to-gate and drain-to-drain, respectively, balanced configuration.
GADG170720191138MT
Z
DL
(Ω)
3.5 + j 5.2
DS6158 - Rev 8 page 4/16
STAC2942B
Typical performance
4
Typical performance
Figure 2. Capacitances versus drain supply voltage
AM00556v1
1000
900
800
700
600
500
400
300
200
100
0
0 10
F = 1 MHz
Ciss
Crss
Coss
A M 0 0 5 5 6 v 1 . s v g
20 30 40
Supply voltage (V)
50 60
Figure 4. Output power versus gate voltage
250
200
150
100
50
0
-1
500
450
400
350
300
F = 175 MHz
Pin = 2.4 W
I
V
DD
DQ
= 50 V
= 2 x 250 mA
-0.5
T
T
T case case case
0
= + 25 °C
= + 80 °C
= - 20 °C
0.5
1 1.5
Gate voltage (V)
2 2.5
AM00558v1
3 3.5
Figure 6. Output power vs input power and case temperature
AM00560v1
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0 2 4
F = 175 MHz
I
V
DD
DQ
= 50 V
= 2 x 250 mA
T case
= +25 °C
T case
= +80 °C
T case
6 8 10
Input Power (W)
12 14 16
Figure 3. Output power versus drain supply voltage
AM00557v1
600
550
500
450
400
350
300
250
200
150
100
50
0
20
F = 175 MHz, I
DQ
= 2 x 250 mA
Pin = 1.25 W
Pin = 5 W
Pin = 2.5 W
30 40
Supply voltage (V)
50 60
Figure 5. Output power versus input power
AM00559v1
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0 2 4
V
DD
= 50 V
V
DD
= 40 V
F = 175 MHz
I
DQ
= 2 x 250 mA
T case
= + 25 °C
6 8
Input power (W)
10 12 14 16
Figure 7. Efficiency vs output power and case temperature
AM00561v1
100
90
80
70
60
50
40
30
20
10
0
0 100
F = 175 MHz
I
V
DD
DQ
= 50 V
= 2 x 250 mA
T case
= +25 °C
T case
= +80 °C
T case
200 300 400
Output power (W)
500 600 700
DS6158 - Rev 8 page 5/16
DS6158 - Rev 8
Figure 8. Power gain vs output power and case temperature
23
22
21
AM00562v1
20
19
18
17
I
F = 175 MHz
V
DD
DQ
= 50 V
= 2 x 250 mA
16
15
14
T case
= +25 °C
T case
= +80 °C
T case
13
0 50 100 150 200 250 300 350 400 450 500 550 600 650
Output power (W)
Figure 9. Safe operating area
Tcase = +25°C / Tj = +200°C
1000
100
10
DC
10 mS
1 mS
1
Drain supply voltage - Vdd (V)
0.15
0 10
0.05
0.30
0.25
0.20
Figure 10. Transient thermal impedance
1 0 0 0
AM07221v1
1.E-04 1.E-03 1.E-02 1.E-01
Rectangula r powe r pulse width (s)
1.E+00
AM07222v1
STAC2942B
Typical performance page 6/16
DS6158 - Rev 8
Figure 11. Transient thermal model
R
R 7
R =0.0156223 O hm
C
C 8
C =0.0025604 F
R
R 8
R =.04686695 O hm
C
C 7
C =0.0025604 F
R
R 6
R =.1309871 O hm
C
C 6
C =0.0377893 F
R
R 5
R =.0865236 O hm
C
C 5
C =0.2418993 F
AM06109v1
STAC2942B
Typical performance page 7/16
5
5.1
STAC2942B
Test circuit
Test circuit
Electrical schematic and BOM
+Vgg FB3
C23
B1
FB1
+Vgg FB4
C22
Figure 12. 175 MHz test circuit schematic (production test circuit)
B C
A
A
B
B
B
A A
C
C
A A
C
TRANSMISSION LINE DIMENSIONS
A
A
0.056" SPACE DIMENSION TABLE
DIM
A
B
C
IN
0.430
0.950
2.500
MM
10.92
24.13
63.50
FB6
C21
R2
C25
R4
C2
T1
T1
FB2
C1
FB2
R1
C20
R3
C24
C5
R5
R6
C6
D.U.T.
C9
C10 C11
C12
C13
C15
T2
FB5
CORE
LI
T2
C19
C18
C17
C16
C14
C28
B2
C29
50V
NOTES:
1. DIMENSIONS AT COMPONENT SYMBOLS ARE REFERENCE FOR COMPONENT PLACEMENT. SEE SHEET 1.
2. GAP BETWEEN GROUND & TRANSMISSION LINES IS 0.056[1.42] TYP
AM00528v1
DS6158 - Rev 8 page 8/16
DS6158 - Rev 8
STAC2942B
Electrical schematic and BOM
Table 7. 175 MHz test circuit component list
Component
C1, C2, C14,
C15, C24, C25
C5
C6
C9, C10
C11, C12, C13
C16, C18
C17, C19, C20, C21
C22, C23
C28
C29
R1, R2, R5, R6
R3, R4
B1
B2
T1
T2
L1
FB1,FB5
FB2, FB6
FB3, FB4
PCB
Description
1200 pF ATC 700B chip capacitor
75 pF ATC 100B chip capacitor
ST406 variable capacitor
47 pF ATC 100B chip capacitor
43 pF ATC 100B chip capacitor
470 pF ATC 100B chip capacitor
10,000 pF ATC 200B chip capacitor
0.1 μF 200 V chip capacitor
10 μF 100 V electrolytic capacitor
0.8 - 8 pF variable capacitor
430 Ω, 1/2 W chip resistor
270 Ω 1/2 W axial lead resistor
RG-316 50 Ω 11.8" through ferrite toroid
RG-142 50 Ω 11.8"
4:1, RG-316 25 Ω, 5.9", 2 turns thru ferrite core
1:4, 25 Ω semi-rigid cable, OD .141", 5.9"
λ/4 inductor, RG-142 50 Ω, 11.8", 3 turns thru ferrite toroid
Ferrite toroid
Multi-aperture core
Surface mount ferrite bead
Rogers ultralam 2000, Er 2.55, .060" page 9/16
5.2
Test circuit layout
Figure 13. Test circuit
STAC2942B
Test circuit layout
DS6158 - Rev 8 page 10/16
6
6.1
STAC2942B
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
STAC780-4B package information
Figure 14. STAC780-4B package outline
DS6158 - Rev 8
DM00481937 rev.2
page 11/16
DS6158 - Rev 8
Symbol
R2 r s
Θ
CH1
CH2
M
M p q
R1
H
I
J
F
G
K
L
A
A1
B
C
D
E
Table 8. STAC780-4B mechanical data
Milimeters
Typ
1.52
4.83
9.52
27.69
3.20
3.43
3.30
7.14
Min
3.76
5.03
4.57
9.65
17.78
33.88
0.13
0.97
1.45
0.64
1.52
1.52
0.51
3.25
3.51
3.38
7.21
10°
2.03
1.52
STAC2942B
STAC780-4B package information
1.70
5.33
9.78
28.19
3.30
3.58
3.45
7.29
Max
3.86
5.13
5.08
9.91
18.08
34.19
0.18
1.14
page 12/16
6.2
STAC2942B
Marking information
Marking information
B
PACKAGE FACE :
Figure 15. Marking information
TOP
A
C
F
D
G
E
H I
LEGEND
Marking Composition Field
ARKING
LOGO
C - Assy Pl
(PP)
D - BE Sequenc
(LLL)
E - Diffusion Traceability Plant
(WX)
F - COUNTRY OF ORIGIN
(MAX CHAR ALLOWED = 3)
G - Test & Finishing Plant
(TF)
H - Assy Year
(Y)
I - Assy Week
(WW)
DS6158 - Rev 8 page 13/16
STAC2942B
Revision history
Date
20-Mar-2009
16-Apr-2010
12-Aug-2011
05-Sep-2011
11-Oct-2011
17-Jan-2012
27-Jan-2014
03-Apr-2020
Version
1
2
3
4
5
6
7
8
Table 9. Document revision history
First release.
Added Figure 10, Figure 11 and Figure 12.
Changes
Update figures on coverpage and Section 6: Package mechanical data.
Inserted Section 7: Marking, packing and shipping specifications.
Update L and M dimensions Table 8 on page 13.
Updated order code in Table 1: Device summary and Table 9: Packing and shipping specifications.
Updated Table 10: Marking specifications and Figure 16: Marking layout.
Modified document title.
Updated Table 5: Dynamic new “load mismatch” has been inserted.
Modified pin labeling in Figure 1: Pin connection.
Updated package information. Added Section 1.3 ESD protection characteristics .
DS6158 - Rev 8 page 14/16
STAC2942B
Contents
Contents
DS6158 - Rev 8 page 15/16
STAC2942B
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS6158 - Rev 8 page 16/16
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