STMicroelectronics STL38DN6F7AG Datasheet
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STL38DN6F7AG
Datasheet
Automotive-grade N-channel 60 V, 24 mΩ typ., 10 A STripFET™ F7
Power MOSFET in a PowerFLAT™ 5x6 double island package
Drain on rear side
1 S2
2 G2
3 S1
4 G1
D2
D1
6
5
8
7
NG14G22D1D2RSS13S21
Product status
STL38DN6F7AG
Device summary
Order code STL38DN6F7AG
Marking
Package
Packing
38DN6F7
PowerFLAT™ 5x6 double island
Tape and reel
Features
Order code
STL38DN6F7AG
V
DS
60 V
• AEC-Q101 qualified
• Among the lowest R
DS(on)
on the market
• Excellent FoM (figure of merit)
• Low C rss
/C iss
ratio for EMI immunity
• High avalanche ruggedness
R
DS(on)
max.
27 mΩ
I
D
10 A
Applications
• Switching applications
Description
This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching.
DS12506 - Rev 1 - March 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STL38DN6F7AG
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter
V
DS
V
GS
I
D
I
D
T
J
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
Drain current (continuous) at T
C
C
= 25 °C
= 100 °C
I
DM
Drain current (pulsed)
P
TOT
I
AV
Total dissipation at T
C
= 25 °C
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
E
AS
T stg
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AV
, V
DD
= 40 V)
Storage temperature range
Operation junction temperature range
Value
60
±20
10
10
40
57.7
10
50
-55 to 175
1. Drain current is limited by package, the current capability of the silicon is 33 A at 25 °C and 23 A at 100 °C.
2. Pulse width limited by safe operating area
A
A
W
A mJ
Unit
V
V
A
°C
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s
Value
2.6
32
Unit
°C/W
DS12506 - Rev 1 page 2/15
2
STL38DN6F7AG
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 3. On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
I
Test conditions
D
= 250 μA, V
GS
= 0 V
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 60 V
V
GS
= 0 V, V
DS
= 60 V,
T
C
= 125 °C
V
R
I
GSS
GS(th)
DS(on)
Gate-body leakage current
Gate threshold voltage
Static drain-source on-resistance
V
V
V
1. Defined by design, not subject to production test.
GS
DS
GS
= 20 V, V
DS
= V
GS
, I
D
= 10 V, I
D
= 0 V
= 250 μA
= 5 A
Min.
60
2
Symbol
C iss
C oss
C rss
Q g
Q gs
Q gd
Table 4. Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Test conditions
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 30 V, I
D
= 10 A,
V
GS
= 0 to 10 V
(see
Figure 13. Test circuit for gate charge behavior )
Min.
-
-
-
-
-
-
Typ.
24
Typ.
380
320
7.9
7.9
2.9
2.4
Max.
1
100
100
4
27
Max.
-
-
-
-
-
-
Unit pF pF pF nC nC nC
Unit
V
µA
µA nA
V mΩ
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 5. Switching times
Test conditions
V
DD
= 30 V, I
D
= 5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform )
Min.
-
-
-
-
Typ.
12
9
16
5
Max.
-
-
-
-
Unit ns ns ns ns
Symbol
V
SD
Parameter
Forward on voltage
Table 6. Source-drain diode
Test conditions
I
SD
= 10 A, V
GS
= 0 V
Min.
-
Typ.
Max.
1.3
Unit
V
DS12506 - Rev 1 page 3/15
STL38DN6F7AG
Electrical characteristics
Symbol
I t rr
Q rr
RRM
Parameter
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
I
SD
= 10 A, di/dt = 100 A/µs
V
DD
= 48 V
(see
Figure 14. Test circuit for inductive load switching and diode recovery times )
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Min.
-
-
-
Typ.
21.5
8.5
0.8
Max.
Unit ns nC
A
DS12506 - Rev 1 page 4/15
STL38DN6F7AG
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A)
GIPG210320180951SOA
Operation in this area is limited by R
DS(on)
10 1 t p
=100 µs t p
=1 ms t p
=10 ms
10 0
T
T
J
≤175 °C
C
=25 °C single pulse
10 0 10 1
10 -1
10 -1
V
DS
(V)
I
D
(A)
Figure 3. Output characteristics
GIPG210320180948OCH
V
GS
= 8, 9, 10 V
30
V
GS
=7 V
20
V
GS
=6 V
10
0
0 1 2 3 4 5
V
GS
=5 V
6 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
10
V
DS
= 30 V
I
D
= 10 A
GIPG210320180950QVG
8
6
4
2
0
0 1 2 3 4 5 6 7 8 Q g
(nC)
K
Figure 2. Thermal impedance
GIPG210320180950ZTH
10 -1
0.02
0.05
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
I
D
(A)
Figure 4. Transfer characteristics
GIPG210320180949TCH
V
DS
= 2 V
30
20
10
0
0 2 4 6 8 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(mΩ)
GIPG210320180944RID
V
GS
= 10 V
26.5
25.5
24.5
0 2 4 6 8 10 I
D
(A)
DS12506 - Rev 1 page 5/15
STL38DN6F7AG
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GIPG210320180949CVR
C
ISS
C
OSS
10 2 f = 1 MHz
10 1
0 10 20 30 40 50 60
C
RSS
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
1.75
V
GS
I
D
= 10 V
= 10 A
GIPG210320180945RON
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
1.1
I
D
= 250 μA
GIPG210320180947VTH
1.0
0.9
0.8
0.7
0.6
0.5
-75 -25 25 75 125 175 T j
(℃)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GIPG210320180947BDV
I
D
= 1 mA
1.02
1.25
1.00
0.75
0.98
0.25
-75 -25 25 75 125 175 T j
(℃)
0.96
-75 -25 25 75 125 175 T j
(℃)
Figure 11. Source- drain diode forward characteristics
V
SD
(V)
1.1
GIPG210320180948SDF
1.0
T
J
= -55 ℃
0.9
0.8
0.7
0.6
0.5
0 2 4
T
J
= 25 ℃
T
J
= 175 ℃
6 8 10 I
SD
(A)
DS12506 - Rev 1 page 6/15
STL38DN6F7AG
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 13. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 15. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 16. Unclamped inductive waveform
V (BR)DSS
V
D
I DM
I D
V DD V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
Figure 17. Switching time waveform
0 t d(on) t on t r
90%
10%
V
GS
V
DS
90% t d(off) t off t f
90%
10%
0
10%
AM01473v1
DS12506 - Rev 1 page 7/15
4
4.1
STL38DN6F7AG
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
PowerFLAT™ 5x6 double island WF type R package information
Figure 18. PowerFLAT™ 5x6 double island WF type R package outline
DS12506 - Rev 1
8256945_r16_typeR-WF page 8/15
DS12506 - Rev 1
STL38DN6F7AG
PowerFLAT™ 5x6 double island WF type R package information
Dim.
E6
E7
E8
E9
E10
K
L
L1
θ
E
E2
E3
E4
E5
D2
D3
D4
D5
D6
D7 e
A
A1
A2 b
C
D
Table 7. PowerFLAT™ 5x6 double island WF type R mechanical data mm
Typ.
Min.
0.80
0.02
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
1.68
6.00
5.20
4.20
5.00
0.40
0.30
1.27
6.40
0.20
0.85
0.55
4.00
3.55
6.20
3.50
2.35
0.40
0.08
1.275
0.725
0.175
0°
0.325
1.00
4.20
3.70
0.825
0.275
Max.
1.00
0.05
0.45
1.15
0.75
4.40
3.85
6.60
3.70
2.55
0.60
0.28
1.575
0.925
0.375
12°
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
1.98
page 9/15
DS12506 - Rev 1
STL38DN6F7AG
PowerFLAT™ 5x6 double island WF type R package information
Figure 19. PowerFLAT™ 5x6 double island recommended footprint (dimensions are in mm)
8256945_FP_std_R16 page 10/15
4.2
STL38DN6F7AG
PowerFLAT™ 5x6 WF packing information
PowerFLAT™ 5x6 WF packing information
T
0.30 0.05
Figure 20. PowerFLAT™ 5x6 WF tape (dimensions are in mm)
Do
+ 0.1
1.50
0.0
P2
2.0
0.05(I)
Y
Po
4.0 0.1(II)
D1
1.50 MIN
E1
1.75 0.1
R0.30
MAX
Ko (1.20±0.1)
SECTION Y-Y
P1(8.00±0.1)
Y
Ao(6.70±0.1)
(I)
(II)
(III)
Measured from centreline of sprocket hole to centreline of pocket.
Cumulative tolerance of 10 sprocket holes is ± 0.20 .
Measured from centreline of sprocket hole to centreline of pocket.
Base and bulk qua ntity 3000 pcs
8234350_TapeWF_rev_C
Pin 1 identification
Figure 21. PowerFLAT™ 5x6 package orientation in carrier tape
DS12506 - Rev 1 page 11/15
STL38DN6F7AG
PowerFLAT™ 5x6 WF packing information
Figure 22. PowerFLAT™ 5x6 reel (dimensions are in mm)
DS12506 - Rev 1 page 12/15
Revision history
Date
21-Mar-2018
Revision
1
Table 8. Document revision history
Changes
Initial release. The document status is production data.
STL38DN6F7AG
DS12506 - Rev 1 page 13/15
STL38DN6F7AG
Contents
Contents
DS12506 - Rev 1 page 14/15
STL38DN6F7AG
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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© 2018 STMicroelectronics – All rights reserved
DS12506 - Rev 1 page 15/15
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