STL110N4F7AG
Automotive-grade Nchannel 40 V, 3.3 mΩ typ., 108 A
STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on)
max I
D
STL110N4F7AG 40 V 4.0 mΩ 108 A
AEC-Q101 qualified
Among the lowest R
DS(on)
on the market
Excellent FoM (figure of merit)
Low C rss
/C iss
ratio for EMI immunity
High avalanche ruggedness
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching.
Order code
STL110N4F7AG
Table 1: Device summary
Marking Package
110N4F7 PowerFLAT TM 5x6
Packaging
Tape and reel
October 2017 DocID030194 Rev 3
This is information on a product in full production.
1/14 www.st.com
Contents
Contents
STL110N4F7AG
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 5
3 Test circuits ..................................................................................... 7
4 Package information ....................................................................... 8
4.1
4.2
PowerFLAT™ 5x6 package information ............................................ 8
PowerFLAT™ 5x6 packing information ........................................... 11
5 Revision history ............................................................................ 13
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STL110N4F7AG
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
DS
Drain-source voltage
V
GS
I
D
(1)
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
I
I
D
(1)
DM
(2)
Drain current (continuous) at T
Drain current (pulsed)
P
TOT
(1)
Total dissipation at T
C
= 25 °C
C
= 100 °C
I
AS
Single pulse avalanche current
(pulse width limited by maximum junction temperature)
E
AS
T stg
T j
Single pulse avalanche energy (T j
= 25 °C, I
D
= I
AS
, V
DD
= 25 V)
Storage temperature range
Operating junction temperature range
Electrical ratings
Value
40
±20
108
69
432
94
24
130
Unit
V
V
A
A
A
W
A mJ
-55 to 175 °C
Notes:
(1)
Drain current is limited by package, the current capability of the silicon is 178 A at 25 °C
(2)
Pulse width limited by safe operating area.
Symbol
Table 3: Thermal data
Parameter Value
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
1.6
31
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s
Unit
°C/W
°C/W
DocID030194 Rev 3 3/14
Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified).
Symbol Parameter
Table 4: On /off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current V
GS
= 0 V, V
DS
= 40 V
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
V
GS
= 20 V, V
DS
= 0V
V
DS
= V
GS
, I
D
= 250 μA
R
DS(on)
Static drain-source on-resistance V
GS
= 10 V, I
D
= 54 A
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 25 V, f = 1 MHz, V
GS
= 0 V
V
DD
= 20 V, I
D
= 108 A,
V
GS
= 0 to 10 V (see Figure 14:
"Test circuit for gate charge behavior" )
Symbol Parameter
Table 6: Switching times
Test conditions t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time
V
DD
= 20 V, I
D
= 54 A, R
G
= 4.7 Ω,
V
GS
= 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" )
t f
Fall time
Symbol Parameter
V
SD
(1)
Forward on voltage t rr
Reverse recovery time
Table 7: Source-drain diode
Test conditions
I
SD
= 54 A, V
GS
= 0 V
I
Q rr
RRM
Reverse recovery charge
Reverse recovery current
I
D
= 54 A, di/dt = 100 A/µs
V
DD
= 32 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Notes:
(1)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
STL110N4F7AG
Min. Typ. Max. Unit
40 V
1 µA
100 nA
2
3.3
4 V
4.0 mΩ
Min. Typ. Max. Unit
-
-
1150
420
-
- pF pF
-
-
-
-
34
15
8
3.2
-
-
-
- pF nC nC nC
Min. Typ. Max. Unit
-
-
-
-
18
85
27
16
-
-
-
- ns ns ns ns
Min. Typ. Max. Unit
-
- 36
1.2 V ns
- 34 nC
- 1.8 A
4/14 DocID030194 Rev 3
STL110N4F7AG
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
Electrical characteristics
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
DocID030194 Rev 3 5/14
Electrical characteristics
Figure 8: Capacitance variations
STL110N4F7AG
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Source-drain diode forward characteristics
6/14 DocID030194 Rev 3
STL110N4F7AG
3 Test circuits
Figure 13: Test circuit for resistive load switching times
Test circuits
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
DocID030194 Rev 3 7/14
Package information
4
4.1
Package information
STL110N4F7AG
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
PowerFLAT™ 5x6 package information
Figure 19
: PowerFLAT™ 5x6 WF type C package outline
8/14 DocID030194 Rev 3
8231817_WF_typeC_r15
STL110N4F7AG
Dim.
D4
D5
D6 e
E
E2
E3
C
D
D2
D3
A
A1
A2 b
E4
E5
E6
E7
E9
E10
K
L
L1
θ
Package information
Table 8: PowerFLAT™ 5x6 WF type C mechanical data mm
Min. Typ. Max.
0.80
0.02
0.25
1.00
0.05
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
6.00
5.20
4.20
5.00
0.40
0.30
1.27
6.40
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
6.20
3.50
2.35
0.40
0.08
0.20
0.85
4.00
3.55
1.05
0.90
0.175
0°
0.325
1.00
4.20
3.70
1.00
0.275
6.60
3.70
2.55
0.60
0.28
0.45
1.15
4.40
3.85
1.35
1.10
0.375
12°
DocID030194 Rev 3 9/14
Package information STL110N4F7AG
Figure 20
: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_rev15
10/14 DocID030194 Rev 3
STL110N4F7AG
4.2 PowerFLAT™ 5x6 packing information
Package information
Figure 21
: PowerFLAT™ 5x6 WF tape (dimensions are in mm)
Figure 22
: PowerFLAT™ 5x6 package orientation in carrier tape
DocID030194 Rev 3 11/14
Package information
Figure 23
: PowerFLAT™ 5x6 reel (dimensions are in mm)
STL110N4F7AG
12/14 DocID030194 Rev 3
STL110N4F7AG
5
Revision history
Revision history
Date Revision
Table 9: Document revision history
Changes
04-Jan-2017
11-Jan-2017
03-Oct-2017
1
2
3
First release
Updated information on cover page.
Updated title and features in cover page.
Updated Figure 2: "Safe operating area" and Figure 3: "Thermal impedance" .
Updated Section 4: "Package information" .
Minor text changes.
DocID030194 Rev 3 13/14
STL110N4F7AG
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14/14 DocID030194 Rev 3
