STMicroelectronics STL64N4F7AG Datasheet
विज्ञापन
विज्ञापन
STL64N4F7AG
Datasheet
Automotive-grade 40 V, 7.0 mΩ typ., 64 A, STripFET™ F7
Power MOSFET in a PowerFLAT™ 5x6 package
G(4)
Features
Order code
STL64N4F7AG
V
DS
40 V
R
DS(on)
max.
8.5 mΩ
I
D
64 A
D(5, 6, 7, 8)
S(1, 2, 3)
1
2
3
4
PowerFLAT™ 5x6
8 7 6 5
1 2 3 4
Top View
NG4D5678S123
• AEC-Q101 qualified
• Among the lowest R
DS(on)
on the market
• Excellent FoM (figure of merit)
• Low C rss
/C iss
ratio for EMI immunity
• High avalanche ruggedness
• Wettable flank package
Applications
• Switching applications
Description
This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching.
Product status link
STL64N4F7AG
Product summary
Order code STL64N4F7AG
Marking
Package
Packing
64N4F7
PowerFLAT™ 5x6
Tape and reel
DS12596 - Rev 2 - June 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STL64N4F7AG
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
DS
V
GS
Drain-source voltage
Gate-source voltage
Parameter
I
D
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed) I
DM
P
TOT
T j
T stg
Total dissipation at T
C
= 25 °C
Operating junction temperature range
Storage temperature range
1. Pulse width limited by safe operating area
Table 2. Thermal data
Symbol Parameter
R thj-pcb
R thj-case
Thermal resistance junction-pcb
Thermal resistance junction-case
1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s.
Value
40
±20
64
40.3
256
65
-55 to 175
Unit
V
V
A
A
A
W
°C
Value
32
2.3
Unit
°C/W
°C/W
DS12596 - Rev 2 page 2/15
2
STL64N4F7AG
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Table 3. On-/off-states
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
Zero gate voltage drain current V
GS
= 0 V, V
DS
= 40 V
Gate-body leakage current
Gate threshold voltage
V
GS
= 20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 μA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 32 A
Min.
40
2
Typ.
Max.
7.0
1
100
4
8.5
Unit
V
µA nA
V mΩ
Symbol
C iss
C oss
C rss
Q g
Q gs
Q gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Table 4. Dynamic
V
DS
Test conditions
= 25 V, f = 1 MHz, V
GS
= 0 V
V
DD
= 20 V, I
D
= 64 A,
V
GS
= 0 to 10 V
(see
Figure 13. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
Typ.
637
240
26
9.8
3.8
3.1
Max.
-
-
-
-
-
-
Unit pF pF pF nC nC nC
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 5. Switching times
Test conditions
V
DD
= 20 V, I
D
= 32 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 12. Test circuit for resistive load switching times and
Figure 17. Switching time waveform
)
Min.
-
-
-
-
Typ.
18.8
102.6
21.4
13.3
Max.
-
-
-
-
Unit ns ns ns ns
Symbol
V
SD
t rr
Q rr
I
RRM
Parameter
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 6. Source-drain diode
Test conditions
I
SD
= 64 A, V
GS
= 0 V
I
D
= 64 A, di/dt = 100 A/µs
V
DD
= 32 V (see Figure 14. Test circuit for inductive load switching and diode recovery times
)
Min.
-
-
-
-
Typ.
Max.
1.3
27.5
17.3
1.4
Unit
V ns nC
A
DS12596 - Rev 2 page 3/15
STL64N4F7AG
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
I
D
(A) Operation in this area is limited by R
DS(on)
GADG240520181056SOA
10 2 t p
=10 µs t p
=100 µs
10 1
Single pulse,
T
C
= 25 °C,
T
J
≤ 175 °C
10 0 t p
=1 ms t p
=10 ms
10 -1
10 -1 10 0 10 1
V
DS
(V)
I
D
(A)
100
Figure 3. Output characteristics
GADG220520181214OCH
V
GS
= 10 V
V
GS
= 9 V
V
GS
= 8 V
80
V
GS
= 7 V
60
V
GS
= 6 V
40
V
GS
= 5 V 20
0
0 1 2 3 4 5 V
DS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
GADG280520180949QVG
6
4
10
8
2
0
0 2
V
DS
= 20 V
I
D
= 64 A
4 6 8 10 Q g
(nC)
Figure 2. Thermal impedance
K
δ = 0.5
GADG240520181056ZTH
δ = 0.2
10 -1
δ = 0.1
δ = 0.05
δ = 0.02
δ = 0.01
Single pulse
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
I
D
(A)
100
Figure 4. Transfer characteristics
GADG220520181214TCH
T
J
= -55 °C
80
60
40
V
DS
= 5 V
T
J
= 25 °C
20
0
3 4 5 6 7
T
J
= 175 °C
8 V
GS
(V)
Figure 6. Static drain-source on-resistance
R
DS(on)
(mΩ)
9
GADG240520181056RID
8
7
V
GS
= 10 V
6
5
4
0 10 20 30 40 50 60 I
D
(A)
DS12596 - Rev 2 page 4/15
STL64N4F7AG
Electrical characteristics (curves)
C
(pF)
Figure 7. Capacitance variations
GADG220520181215CVR f = 1MHz
10 3
C
ISS
C
OSS
10 2
10 1
0 10 20 30 40
C
RSS
V
DS
(V)
Figure 8. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
GADG280520180958RON
2
1.5
V
GS
= 10 V
I
D
= 32 A
1
0.5
0
-75 -25 25 75 125 175 T j
(°C)
Figure 9. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GADG220520181216BDV
1.08
I
D
= 1 mA
1.04
1.00
0.96
0.92
-75 -25 25 75 125 175 T j
(°C)
Figure 10. Normalized gate-threshold voltage vs temperature
V
GS(th)
(norm.)
1.1
GADG220520181216VTH
I
D
= 250 µA 1.0
0.9
0.8
0.7
0.6
0.5
-75 -25 25 75 125 175 T j
(°C)
Figure 11. Source-drain diode forward characteristics
V
SD
(V)
GADG220520181216SDF
1.0
T
J
= -50 °C
0.9
T
J
= 25 °C
0.8
0.7
T
J
= 150 °C
0.6
0.5
5 10 15 20 25 30 35 40 I
SD
(A)
DS12596 - Rev 2 page 5/15
STL64N4F7AG
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 13. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 15. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
3.3
µF
S
+
1000
µF
V
DD
AM01470v1
Figure 16. Unclamped inductive waveform
V (BR)DSS
V D
I
DM
I D
V DD V DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 17. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS12596 - Rev 2 page 6/15
4
STL64N4F7AG
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS12596 - Rev 2 page 7/15
4.1
STL64N4F7AG
PowerFLAT™ 5x6 WF type C package information
PowerFLAT™ 5x6 WF type C package information
Figure 18. PowerFLAT™ 5x6 WF type C package outline
DS12596 - Rev 2
8231817_WF_typeC_r16 page 8/15
DS12596 - Rev 2
Dim.
L1
θ
K
L
E7
E9
E10
E2
E3
E4
E5
E6 e
E
D2
D3
D4
D5
D6
A
A1
A2 b
C
D
STL64N4F7AG
PowerFLAT™ 5x6 WF type C package information
Table 7. PowerFLAT™ 5x6 WF type C mechanical data mm
Typ.
Min.
0.80
0.02
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
6.00
5.20
4.20
5.00
0.40
0.30
1.27
6.40
0.08
0.20
0.85
4.00
3.55
6.20
3.50
2.35
0.40
1.05
0.90
0.175
0°
0.325
1.00
4.20
3.70
1.00
0.275
Max.
1.00
0.05
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
0.28
0.45
1.15
4.40
3.85
6.60
3.70
2.55
0.60
1.35
1.10
0.375
12° page 9/15
DS12596 - Rev 2
STL64N4F7AG
PowerFLAT™ 5x6 WF type C package information
Figure 19. PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_rev16 page 10/15
4.2
STL64N4F7AG
PowerFLAT™ 5x6 WF packing information
PowerFLAT™ 5x6 WF packing information
T
0.30 0.05
Figure 20. PowerFLAT™ 5x6 WF tape (dimensions are in mm)
Do
+ 0.1
1.50
0.0
P2
2.0
0.05(I)
Y
Po
4.0 0.1(II)
D1
1.50 MIN
E1
1.75 0.1
R0.30
MAX
Ko (1.20±0.1)
SECTION Y-Y
P1(8.00±0.1)
Y
Ao(6.70±0.1)
(I)
(II)
(III)
Measured from centreline of sprocket hole to centreline of pocket.
Cumulative tolerance of 10 sprocket holes is ± 0.20 .
Measured from centreline of sprocket hole to centreline of pocket.
Base and bulk qua ntity 3000 pcs
8234350_TapeWF_rev_C
Pin 1 identification
Figure 21. PowerFLAT™ 5x6 package orientation in carrier tape
DS12596 - Rev 2 page 11/15
STL64N4F7AG
PowerFLAT™ 5x6 WF packing information
PART NO.
Figure 22. PowerFLAT™ 5x6 reel (dimensions are in mm)
R0.60
W3
11.9/15.4
1.90
2.50
W2
18.4 (max)
R25.00
∅ 4.00
ØN
178(±2.0)
∅ 2.50
77 ESD LOGO
W1
12.4 (+2/-0)
06
PS
128
ØA
Ø21.2
R1.10
∅ 13.00
CORE DETAIL
All dimensions are in millimeters
A
330 (+0/-4.0)
8234350_Reel_rev_C
DS12596 - Rev 2 page 12/15
Revision history
Date
30-May-2018
27-Jun-2018
Table 8. Document revision history
Version
1
2
Changes
Initial release
Updated title and features in cover page.
STL64N4F7AG
DS12596 - Rev 2 page 13/15
STL64N4F7AG
Contents
Contents
DS12596 - Rev 2 page 14/15
STL64N4F7AG
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12596 - Rev 2 page 15/15
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