STD9N80K5
Datasheet
N-channel 800 V, 0.73 Ω typ., 7 A MDmesh™ K5 Power MOSFET in a DPAK package
G ( 1 )
TAB
DPAK
1
2 3
D (2 , TAB )
AM15572V1
Features
Order code
STD9N80K5
V
DS
800 V
R
DS(on) max.
0.90 Ω
• Industry’s lowest RDS(on) x area
• Industry’s best figure of merit (FoM)
• Ultra-low gate charge
• 100% avalanche tested
• Zener-protected
I
D
7 A
P
TOT
110 W
Applications
• Switching applications
Description
This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency.
Product status
STD9N80K5
Product summary
Order code STD9N80K5
Marking
Package
Packing
9N80K5
DPAK
Tape and reel
DS11297 - Rev 3 - November 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STD9N80K5
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter
V
GS
I
D
I
D
I
D
(1)
P
TOT dv/dt
(2)
Gate-source voltage
Drain current (continuous) at T
Drain current (continuous) at T
Drain current (pulsed)
Total power dissipation at T
C
C
C
= 25 °C
= 100 °C
= 25 °C dv/dt
(3)
T stg
T j
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 7 A, di/dt ≤ 100 A/µs; V
DS( peak)
< V
(BR)DSS
; V
DD
= 640 V
3. V
DS
≤ 640 V
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Parameter
Thermal resistance junction-case
Thermal resistance junction-pcb
1. When mounted on FR-4 board of 1 inch², 2 oz Cu
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
; V
DD
= 50 V)
Value
±30
7
4.4
28
110
4.5
50
- 55 to 150
Unit
V
A
A
A
W
V/ns
V/ns
°C
Value
1.14
50
Unit
°C/W
°C/W
Value Unit
2.4
A
200 mJ
DS11297 - Rev 3 page 2/19
2
STD9N80K5
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified
Table 4. On/off states
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter
Drain-source breakdown voltage
Zero gate voltage Drain current
Gate-body leakage current
Gate threshold voltage
Static drain-source on-resistance
1. Defined by design, not subject to production test.
Test conditions
V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 800 V
V
GS
= 0 V, V
DS
= 800 V, T
C
= 125 °C (1)
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
=100 µA
V
GS
= 10 V, I
D
= 3.5 A
Min.
Typ.
Max.
Unit
800
1
V
µA
50 µA
3 4
±10 µA
5
0.73
0.90
V
Ω
Table 5. Dynamic
Symbol
R g
Q g
Q gs
Q gd
Parameter
C iss
C oss
C rss
C o(tr)
(1)
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent capacitance time related
C o(er)
(2)
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
V
DS
DS
= 100 V, f = 1 MHz, V
= 0 to 640 V, V f = 1 MHz , I
V
DD
V
GS
See (
D
= 0 A
= 640 V, I
D
= 0 to 10 V
Test conditions
GS
= 7 A
GS
= 0 V
= 0 V
Figure 15. Test circuit for gate charge behavior
)
Min. Typ. Max. Unit
-
-
-
-
-
-
-
-
-
340
37
0.65
61
22
7
12
3.8
6.7
-
-
-
-
-
-
-
-
-
1. C o(tr)
is a constant capacitance value that gives the same charging time as C oss
while V
DS
is rising from 0 to 80% V
DSS
.
2. C o(er)
is a constant capacitance value that gives the same stored energy as C oss
while V
DS
is rising from 0 to 80% V
DSS pF pF pF pF pF
Ω nC nC nC
Symbol t d(on) t r
Parameter
Turn-on delay time
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 6. Switching times
Test conditions
V
DD
= 400 V, I
D
=3.5 A, R
G
= 4.7 Ω
V
GS
= 10 V
See ( Figure 14. Test circuit for resistive load switching times and
Figure 19. Switching time waveform )
Min. Typ. Max. Unit
11 ns
5.7
65.3
-
-
13.6
ns ns ns
DS11297 - Rev 3 page 3/19
DS11297 - Rev 3
STD9N80K5
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
Parameter
Source-drain current
I
SDM
(1)
Source-drain current (pulsed)
V
SD
(2)
I t
Q rr rr
RRM
Test conditions
Forward on voltage I
SD
= 7 A, V
GS
= 0 V
Reverse recovery time
Reverse recovery charge
I
SD
= 7 A, di/dt = 100 A/µs,V
DD
= 60 V
See Figure 16. Test circuit for inductive load switching and diode recovery times
Reverse recovery current
I t
Q rr rr
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 7 A, di/dt = 100 A/µs V
See Figure 16. Test circuit for inductive load switching and diode recovery times
DD
= 60 V, T j
= 150 °C
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
V
(BR)GSO
Table 8. Gate-source Zener diode
Parameter
Gate-source breakdown voltage
Test conditions
I
GS
= ±1 mA, I
D
= 0 A
Min. Typ. Max. Unit
7 A
28 A
-
292
1.5
V ns
2.66
18.2
477
µC
A ns
3.91
16.4
µC
A
Min.
Typ.
Max.
Unit
±30 V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
page 4/19
STD9N80K5
STD9N80K5_Electrical characteristics curves
2.1
STD9N80K5_Electrical characteristics curves
Figure 1. Safe operating area
I
D
(A)
GIPD280120161003SOA
Operation in this area is limited by R
DS(on)
10 1
10 0 t p
= 10µs t p
= 100µs t p
= 1ms t p
= 10ms
10 -1
10 -2
10 -1 10 0
T
T j
≤150 °C c
= 25°C single pulse
10 1 10 2 10 3
V
DS
(V)
K
Figure 2. Thermal impedance
GC20460
10 0
10 -1
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
4
2
0
0
8
6
I
D
(A)
12
Figure 3. Output characteristics
GIPG101115VK82FOCH
V
GS
= 11 V
V
GS
= 10 V V
GS
= 9 V
10
4 8
V
GS
= 8 V
12
V
GS
= 7 V
V
GS
= 6 V
16 V
DS
(V)
4
2
0
4
8
6
Figure 4. Transfer characteristics
I
D
(A)
12
V
DS
=20 V
GIPG101115VK82FTCH
10
5 6 7 8 9 V
GS
(V)
Figure 5. Gate charge vs gate-source voltage
V
GS
(V)
12
10
V
DS
GIPG101115VK82FQVG V
DS
(V)
V
DD
I
D
= 640 V
= 3.5 A
600
500
8
6
4
2
0
0 2 4 6 8
400
300
10 12
200
100
Q
0 g
(nC)
Figure 6. Static drain-source on-resistance
R
DS(on)
(Ω)
0.97
V
GS
= 10 V
GIPG101115VK82FRID
0.89
0.81
0.73
0.65
0.57
0 1 2 3 4 5 6 I
D
(A)
DS11297 - Rev 3 page 5/19
STD9N80K5
STD9N80K5_Electrical characteristics curves
C
(pF)
Figure 7. Capacitance variations
GIPG101115VK82FCVR
10 3
C
ISS
10 2
10 1
C
OSS
C
RSS
10 0
10 -1
10 -1 f = 1 MHz
10 0 10 1 10 2
V
DS
(V)
Figure 9. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.6
V
GS
= 10 V
GIPG101115VK82FRON
2.2
1.8
1.4
1
0.6
0.2
-75 -25 25 75 125 T j
(°C)
Figure 11. Output capacitance stored energy
E
OSS
(µJ)
6
GIPG101115VK82FEOS
3
2
5
4
1
0
0 100 200 300 400 500 600 700 V
DS
(V)
Figure 8. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GIPG101115VK82FVTH
I
D
= 100 µA
1.2
1.0
0.8
0.6
0.4
-75 -25 25 75 125 T j
(°C)
Figure 10. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
1.12
I
D
= 1 mA
GIPG101115VK82FBDV
1.08
1.04
1.0
0.96
0.92
0.88
-75 -25 25 75 125 T j
(°C)
Figure 12. Source-drain diode forward characteristics
V
SD
(V)
1.0
GIPG101115VK82FSDF
T j
= -50 °C
0.9
T j
= 25 °C
0.8
0.7
0.6
0.5
1 2 3 4
T j
= 150 °C
5 6 7 I
SD
(A)
DS11297 - Rev 3 page 6/19
STD9N80K5
STD9N80K5_Electrical characteristics curves
Figure 13. Maximum avalanche energy vs starting T
J
E
AS
(mJ)
200
GIPG101115VK82FEAS
160
120
80
40
0
-75
Single pulse,
I
D
=2.4 A, V
DD
=50 V
-25 25 75 125 T
J
(°C)
DS11297 - Rev 3 page 7/19
STD9N80K5
Test circuits
3
Test circuits
Figure 14. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 16. Test circuit for inductive load switching and diode recovery times
Figure 15. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 17. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
3.3
µF
S
+
1000
µF
V
DD
AM01470v1
Figure 18. Unclamped inductive waveform
V (BR)DSS
V D
I
DM
I D
V DD V DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 19. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS11297 - Rev 3 page 8/19
4
STD9N80K5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS11297 - Rev 3 page 9/19
4.1
STD9N80K5
DPAK (TO-252) type A2 package information
DPAK (TO-252) type A2 package information
Figure 20. DPAK (TO-252) type A2 package outline
DS11297 - Rev 3
0068772_type-A2_rev25 page 10/19
DS11297 - Rev 3
Dim.
c2
D
D1
E
E1 e e1
A
A1
A2 b b4 c
L2
L4
R
V2
H
L
L1
STD9N80K5
DPAK (TO-252) type A2 package information
Table 9. DPAK (TO-252) type A2 mechanical data mm
Typ.
9.35
1.00
2.60
0.65
0.60
4.95
6.40
5.10
2.159
4.445
0.64
5.20
0.45
0.48
6.00
Min.
2.20
0.90
0.03
5.10
5.20
2.286
4.572
2.80
0.80
0.20
0°
10.10
1.50
3.00
0.95
1.00
5.25
6.60
5.30
2.413
4.699
0.90
5.40
0.60
0.60
6.20
Max.
2.40
1.10
0.23
8° page 11/19
4.2
STD9N80K5
DPAK (TO-252) type C2 package information
DPAK (TO-252) type C2 package information
Figure 21. DPAK (TO-252) type C2 package outline
DS11297 - Rev 3
0068772_C2_25 page 12/19
DS11297 - Rev 3
Dim.
L
L1
L2
L3
L4
L6
θ1
θ2
V2 c2
D
D1
E
E1 e
H
A
A1
A2 b b4 c
STD9N80K5
DPAK (TO-252) type C2 package information
Table 10. DPAK (TO-252) type C2 mechanical data
0.72
5.13
0.47
0.47
6.00
Min.
2.20
0.90
0.00
5.10
6.50
5.20
2.186
9.80
1.40
mm
Typ.
2.30
1.01
5.33
6.10
6.60
2.286
10.10
1.50
2.90 REF
0.90
0.60
5°
5°
0°
0.51 BSC
0.80
1.80 BSC
7°
7°
1.00
9°
9°
8°
0.85
5.46
0.60
0.60
6.20
Max.
2.38
1.10
0.10
5.60
6.70
5.50
2.386
10.40
1.70
1.25
page 13/19
STD9N80K5
DPAK (TO-252) type C2 package information
Figure 22. DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_25
DS11297 - Rev 3 page 14/19
4.3
DPAK (TO-252) packing information
Figure 23. DPAK (TO-252) tape outline
T
Top cover tape
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
STD9N80K5
DPAK (TO-252) packing information
F
E
W
User direction of feed
R
Bending radius
AM08852v1
DS11297 - Rev 3 page 15/19
DS11297 - Rev 3
Dim.
D1
E
F
K0
P0
A0
B0
B1
D
P1
P2
R
T
W
A
D
B
Figure 24. DPAK (TO-252) reel outline
STD9N80K5
DPAK (TO-252) packing information
T
40mm min. access hole at slot location
C
N
G measured at hub
Full radius
Tape slot in core for tape start
2.5mm min.width
AM06038v1
2.55
3.9
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
Table 11. DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
C
D
A
B
G
N
T
Min.
1.5
12.8
20.2
16.4
50 1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
mm
Max.
330
13.2
18.4
22.4
2500
2500 page 16/19
STD9N80K5
Revision history
Table 12. Document revision history
Date
20-Oct-2015
Revision Changes
1 First release.
28-Jan-2016
12-Nov-2018
2
3
Document status promoted from preliminary to production data.
Updated DPAK (TO-252) type A2 package information.
Inserted Section 2 Electrical characteristics
.
Minor text changes.
Updated , ,
Table 5. Dynamic and
Table 7. Source-drain diode
. Added
Section 4.2 DPAK (TO-252) type C2 package information
.
DS11297 - Rev 3 page 17/19
STD9N80K5
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
STD9N80K5_Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1
DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DS11297 - Rev 3 page 18/19
STD9N80K5
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS11297 - Rev 3 page 19/19
