STD10NM65N
Datasheet
N-channel 650 V, 0.43 Ω typ., 9 A MDmesh™ II Power MOSFET in a DPAK package
TAB
DPAK
1
2 3
D(2, TAB)
G(1)
S(3)
AM01475v1_noZen
Features
Order code
V
DS
@
T jmax.
STD10NM65N 710 V
• 100% avalanche tested
• Low input capacitance and gate charge
• Low gate input resistance
R
DS(on)
max.
0.48 Ω
I
D
9 A
Applications
• Switching applications
Description
This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
Product status
STD10NM65N
Product summary
Order code STD10NM65N
Marking
Package
Packing
10NM65N
DPAK
Tape and reel
DS5566 - Rev 4 - May 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STD10NM65N
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
DS
V
GS
I
D
I
D
I
DM
(1)
P
TOT dv/dt
(2)
dv/dt
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
Parameter
= 25 °C
= 100 °C
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
Drain-source voltage slope (V
DD
= 520 V, I
D
= 9 A, V
GS
= 10 V)
Operating junction temperature range T j
T stg
Storage temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 9 A, di/dt ≤ 400 A/μs, V
DSpeak
≤ V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
.
Table 2. Thermal data
Symbol
R thj-case
Thermal resistance junction-case
R thj-pcb
(1)
Thermal resistance junction-pcb
Parameter
1. When mounted on 1inch² FR-4, 2 Oz copper board.
Symbol
I
AS
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive (pulse width limited by T j
Max)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AS
, V
DD
= 50 V)
Value
650
±25
9
5.7
36
90
15
25
-55 to 150
Unit
V
V
A
A
A
W
V/ns
°C
Value
1.39
50
Unit
°C/W
°C/W
Value
2.5
200
Unit
A mJ
DS5566 - Rev 4 page 2/18
2
STD10NM65N
Electrical characteristics
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 4. On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
I
D
= 1 mA, V
Test conditions
GS
= 0 V
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 650 V
V
GS
= 0 V, V
DS
= 650 V, T
C
= 125 °C
(1)
V
R
I
GSS
GS(th)
DS(on)
Gate body leakage current
Gate threshold voltage
Static drain-source on resistance
V
V
V
DS
DS
GS
= 0 V, V
GS
= V
GS
, I
D
= 10 V, I
1. Defined by design, not subject to production test.
D
= ±20 V
= 250 µA
= 4.5 A
Min.
650
2
Typ.
Max.
3
0.43
1
100
±100
4
0.48
nA
V
Ω
Unit
V
µA
µA
Table 5. Dynamic
Symbol
C iss
C oss
Parameter
Input capacitance
Output capacitance
Test conditions Min.
Typ.
850
53
Max.
Unit
V
DS
= 50 V, f = 1 MHz, V
GS
= 0 V pF
C rss
C oss eq.
(1)
Reverse transfer capacitance
Equivalent output capacitance
V
DS
= 0 to 520 V, V
GS
= 0 V -
4
90 pF
Q g
Q gs
Q gd
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 520 V, I
D
(see Figure 13. Test circuit for gate charge behavior
)
= 9 A, V
GS
= 0 to 10 V
-
25
4
14
nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss to 80% V
DSS
.
when V
DS
increases from 0
Symbol t d(on) t r t d(off) t f(i)
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 325 V, I
D
= 4.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform
)
Min.
-
Typ.
12
8
50
20
Max.
-
Unit ns
DS5566 - Rev 4 page 3/18
STD10NM65N
Electrical characteristics
Table 7. Source drain diode
Symbol
I
I
SD
SDM
(1)
Parameter
Source-drain current
Source-drain current
(pulsed)
Forward on voltage
Test conditions
V
SD
I
I t
Q rr rr
(2)
RRM t
Q rr rr
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 9 A, V
GS
= 0 V
I
SD
= 9 A, di/dt = 100 A/µs
V
DD
= 100 V (see Figure 14. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 9 A, di/dt = 100 A/µs
V
DD
= 100 V (see Figure 14. Test circuit for inductive load switching and diode recovery times
)
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
Min.
-
-
-
-
330
3
19
430
4
19
Typ.
Max.
9
36
1.3
Unit
A
A ns
μC
A
V ns
μC
DS5566 - Rev 4 page 4/18
STD10NM65N
Electrical characteristics curves
2.1
Electrical characteristics curves
Figure 1. Safe operating area
10
1
8
6
4
2
10
0
8
6
2
4
4
this Area is
Operation in
Limited
by Max Rds(on)
HV41670
Tj=150°C
Tc=25°C
Single pulse
100 m s
1ms
10ms
2
10
-1
8
6
4
2
10
-2
10 -1
2 4 6 8
10 0
2 4 6 8
10 1
2 4 6 8
10 2
2 4 6 8
10 3
V
DS
(V)
I
D
(A)
Figure 3. Output characterisics
HV41690
V
GS
=10V
20
6V
15
10
5
5V
0 10 20
4V
30 V
DS
(V)
Figure 5. Static drain-source on resistance
HV41760
R
DS(on)
(Ω)
0.6
V
GS
=10V
0.5
0.4
0.3
0.2
0 2 4 6 8
K
Figure 2. Thermal impedance
GC20460
10 0
10 -1
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
I
D
(A)
Figure 4. Transfer characteristics
HV41695
V
DS
=20V
20
15
10
5
0 2 4 6 8 V
GS
(V)
Figure 6. Gate charge vs gate-source voltage
HV41720
V
GS
(V)
12
I
D
=9A
9
6
3
0 5 10 15 20 25
Qg(nC)
DS5566 - Rev 4 page 5/18
STD10NM65N
Electrical characteristics curves
Figure 7. Capacitance variations
C (pF)
4
10
3
8
6
4
2
10
2
8
6
4
2
10
1
8
6
4
2
2
10
0
10 -1
2 4 6 8
10 0
2 4 6 8
10 1
2 4 6 8
10 2
HV41730
Ciss
Coss
Crss
Figure 9. Normalized on resistance vs temperature
HV41750
R
DS(on)
(norm)
2.5
V
GS
=10V
I
D
=4.5A
2.0
1.5
1.0
0.5
0
-100 -50 0 50 100 150 T
J
( °C)
Figure 8. Normalized gate threshold voltage vs temperature
HV41740
V
GS(th)
(norm)
1.1
I
D =250µA
1.0
0.9
0.8
0.7
0.6
-100 -50 0 50 100 150 T
J
(°C)
Figure 10. Source-drain diode forward characteristic
HV27230
V
SD
(V)
0.9
T
J
=-50 °C
25 °C
0.8
150 °C
0.7
0.6
0.5
0.4
0 2 4 6 8 10 I
SD
(A)
Figure 11. Normalized V
(BR)DSS
vs temperature
HV41700
V
(BR)DSS
(norm) V
GS
=0
I
D
=1mA
1.1
1.05
1.0
0.95
0.90
-50 0 50 100 T
J
(°C)
DS5566 - Rev 4 page 6/18
STD10NM65N
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 13. Test circuit for gate charge behavior
V
GS pulse width
2200
μF
+
1 kΩ
12 V
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 15. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 16. Unclamped inductive waveform
V
(BR)DSS
V
D
I DM
I D
V
DD V DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
Figure 17. Switching time waveform
0 t d(on) t on t r
90%
10%
V
GS
V
DS
90% t d(off) t off t f
90%
10%
0 10%
AM01473v1
DS5566 - Rev 4 page 7/18
4
STD10NM65N
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS5566 - Rev 4 page 8/18
4.1
STD10NM65N
DPAK (TO-252) type A2 package information
DPAK (TO-252) type A2 package information
Figure 18. DPAK (TO-252) type A2 package outline
DS5566 - Rev 4
0068772_type-A2_rev25 page 9/18
DS5566 - Rev 4
Dim.
c2
D
D1
E
E1 e e1
A
A1
A2 b b4 c
L2
L4
R
V2
H
L
L1
STD10NM65N
DPAK (TO-252) type A2 package information
Table 8. DPAK (TO-252) type A2 mechanical data mm
Typ.
9.35
1.00
2.60
0.65
0.60
4.95
6.40
5.10
2.159
4.445
0.64
5.20
0.45
0.48
6.00
Min.
2.20
0.90
0.03
5.10
5.20
2.286
4.572
2.80
0.80
0.20
0°
10.10
1.50
3.00
0.95
1.00
5.25
6.60
5.30
2.413
4.699
0.90
5.40
0.60
0.60
6.20
Max.
2.40
1.10
0.23
8° page 10/18
4.2
STD10NM65N
DPAK (TO-252) type C2 package information
DPAK (TO-252) type C2 package information
Figure 19. DPAK (TO-252) type C2 package outline
DS5566 - Rev 4
0068772_C2_25 page 11/18
DS5566 - Rev 4
Dim.
L
L1
L2
L3
L4
L6
θ1
θ2
V2 c2
D
D1
E
E1 e
H
A
A1
A2 b b4 c
STD10NM65N
DPAK (TO-252) type C2 package information
Table 9. DPAK (TO-252) type C2 mechanical data
0.72
5.13
0.47
0.47
6.00
Min.
2.20
0.90
0.00
5.10
6.50
5.20
2.186
9.80
1.40
mm
Typ.
2.30
1.01
5.33
6.10
6.60
2.286
10.10
1.50
2.90 REF
0.90
0.60
5°
5°
0°
0.51 BSC
0.80
1.80 BSC
7°
7°
1.00
9°
9°
8°
0.85
5.46
0.60
0.60
6.20
Max.
2.38
1.10
0.10
5.60
6.70
5.50
2.386
10.40
1.70
1.25
page 12/18
DS5566 - Rev 4
STD10NM65N
DPAK (TO-252) type C2 package information
Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_25 page 13/18
4.3
DPAK (TO-252) packing information
Figure 21. DPAK (TO-252) tape outline
T
Top cover tape
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
STD10NM65N
DPAK (TO-252) packing information
F
E
W
User direction of feed
R
Bending radius
AM08852v1
DS5566 - Rev 4 page 14/18
DS5566 - Rev 4
Dim.
D1
E
F
K0
P0
A0
B0
B1
D
P1
P2
R
T
W
A
D
B
Figure 22. DPAK (TO-252) reel outline
STD10NM65N
DPAK (TO-252) packing information
T
40mm min. access hole at slot location
C
N
G measured at hub
Full radius
Tape slot in core for tape start
2.5mm min.width
AM06038v1
2.55
3.9
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
Table 10. DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
C
D
A
B
G
N
T
Min.
1.5
12.8
20.2
16.4
50 1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
mm
Max.
330
13.2
18.4
22.4
2500
2500 page 15/18
STD10NM65N
Revision history
Date
26-Oct-2007
07-Feb-2008
14-Oct-2008
16-May-2018 4
Table 11. Document revision history
Version
1
2
3
Changes
Initial release.
Document status promoted from preliminary data to datasheet.
Table 4: Avalanche characteristics has been corrected.
The part numbers STF10NM65N, STP10NM65N and STU10NM65N have been moved to a separate datasheet.
Removed maturity status indication from cover page. The document status is production data.
Updated features and description in cover page, Section 1 Electrical ratings ,
Section 2 Electrical characteristics ,
Section 2.1 Electrical characteristics curves and
Section 4 Package information
.
Minor text changes.
DS5566 - Rev 4 page 16/18
STD10NM65N
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DS5566 - Rev 4 page 17/18
STD10NM65N
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
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Purchasers’ products.
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS5566 - Rev 4 page 18/18
