STMicroelectronics STL42P4LLF6 Datasheet
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STL42P4LLF6
Datasheet
P-channel 40 V, 15.5 mΩ typ., 42 A STripFET F6 DeepGATE Power MOSFET in a PowerFLAT 5x6 package
PowerFLAT 5x6
D(5, 6, 7, 8)
G(4)
S(1, 2, 3)
AM01475v4
Features
Order code
STL42P4LLF6
V
DS
40 V
• Very low on-resistance
• Very low gate charge
• High avalanche ruggedness
• Low gate drive power loss
R
DS(on)
max.
18 mΩ
I
D
42 A
P
TOT
75 W
Applications
• Switching applications
Description
This device is a P-channel Power MOSFET developed using the STripFET F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low R
DS(on)
in all packages.
Product status link
STL42P4LLF6
Product summary
Order code
Marking
Package
Packing
STL42P4LLF6
42P4LLF6
PowerFLAT 5x6
Tape and reel
DS10066 - Rev 3 - February 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
STL42P4LLF6
Electrical ratings
1
Note:
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
DS
V
GS
Drain-source voltage
Parameter
I
D
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed) I
DM
I
D
Drain current (continuous) at T pcb
= 25 °C
Drain current (continuous) at T pcb
= 100 °C
Drain current (pulsed) I
DM
P
TOT
P
TOT
T stg
T
J
Total power dissipation at T
Total power dissipation at T
Storage temperature
C
= 25 °C pcb
= 25 °C
Maximum junction temperature
1. The value is limited by R thj-case
.
2. The value is limited by R thj-pcb
.
3. Pulse width is limited by safe operating area.
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
Parameter
Thermal resistance junction-case max
Thermal resistance junction-pcb, single operation
1. When mounted on FR-4 board of 1 inch², 2oz Cu, steady state.
For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed.
Value
2.00
31.3
Value
40
±20
42
29
168
10
7.5
40
75
4.8
-55 to 175
175
Unit
°C/W
°C/W
Unit
V
V
A
A
A
A
A
A
W
W
°C
°C
DS10066 - Rev 3 page 2/17
STL42P4LLF6
Electrical characteristics
2
Note:
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Table 3. Static
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, V
DS
= 40 V
Zero gate voltage Drain current
V
GS
= 0 V, V
DS
= 40 V, T
C
= 125 °C
Gate-body leakage current V
DS
= 0 V, V
GS
= ±20 V
Gate threshold voltage
Static drain-source on-resistance
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 5 A
V
GS
= 4.5 V, I
D
= 5 A
Min.
Typ.
Max.
Unit
40
1
V
µA
1
15.5
21
10 µA
±100 nA
2.5
V
18
26 mΩ
Symbol
C iss
C oss
C rss
Q g
Q gs
Q gd
R g
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Gate input resistance
V
Table 4. Dynamic
DS
Test conditions
= 25 V, f = 1 MHz, V
GS
= 0 V
V
DD
= 20 V, I
D
= 10 A, V
GS
= 4.5 V
(see
Figure 13. Gate charge test circuit
)
I
D
= 0 A, gate DC bias = 0 V, f = 1 MHz, magnitude of alternative signal = 20 mV
-
-
-
-
Min.
Typ.
Max.
Unit
2850 pF
270 pF
180
22
9.4
7.3
-
-
-
pF nC nC nC
1.4
Ω
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Table 5. Switching times
Test conditions
V
DD
= 20 V, I
D
= 5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 12. Switching times test circuit for resistive load )
Min.
Typ.
Max.
Unit
43 ns
-
-
-
47
148
19
-
-
ns ns ns
For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed.
Symbol
V
SD
Parameter
Forward on voltage
Table 6. Source drain diode
Test conditions
V
GS
= 0 V, I
SD
= 5 A
Min.
Typ.
Max.
Unit
1.1
V
DS10066 - Rev 3 page 3/17
STL42P4LLF6
Electrical characteristics
Note:
Symbol
I t rr
Q rr
RRM
Parameter
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
I
SD
= 5 A, di/dt = 100 A/µs,
V
DD
= 32 V, T
J
= 150 °C
(see
Figure 14. Test circuit for inductive load switching and diode recovery times )
1. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
Min.
Typ.
Max.
Unit
26 ns
21 nC
1.7
A
For the P-channel Power MOSFET, current polarity of voltages and current have to be reversed.
DS10066 - Rev 3 page 4/17
STL42P4LLF6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GIPG230220151404ALS
10 2
10 1
Operation in this area limited by max. R
is
DS(on)
10 0
10 -1
10 -1 10 0
T j
≤ 175 °C
T c
= 25 °C single pulse
10 1
100 μs
1 ms
10 ms
V
DS
(V)
60
30
0
0
I
D
(A)
Figure 3. Output characteristics
V
GS
GIPG230220151029ALS
= 10, 9, 8 V
150 V
GS
= 7 V
V
GS
= 6 V
120
90
V
GS
= 5 V
2 4 6
V
GS
= 4V
V
GS
= 3V
8 V
DS
(V)
Figure 5. Normalized gate threshold voltage vs temperature
V
GS(th)
(norm.)
GIPG230220150952ALS
1.10
1.00
0.90
0.80
0.70
0.60
-75 -25 25 75 125 T j
(°C)
K
Figure 2. Thermal impedance
GIPG230220151052ALS
10 -1
10 -2
10 -5 10 -4 10 -3 10 -2 t p
(s)
60
30
0
0
I
D
(A)
Figure 4. Transfer characteristics
GIPG230220151043ALS
150
V
DS
= 9 V
120
90
2 4 6 8 V
GS
(V)
Figure 6. Normalized V
(BR)DSS
vs temperature
V
(BR)DSS
(norm.)
GIPG230220150822ALS
1.08
1.04
I
D
= 1 mA
1.00
0.96
0.92
-75 -25 25 75 125 T j
°C
DS10066 - Rev 3 page 5/17
STL42P4LLF6
Electrical characteristics (curves)
Figure 7. Static drain-source on-resistance
R
DS(on)
(mΩ)
GIPG230220151344ALS
16.5
16.0
15.5
15.0
14.5
0 3
V
GS
= 10 V
6 9 I
D
(A)
Figure 9. Gate charge vs gate-source voltage
V
GS
(V)
12
GIPG100320151458ALS
10
8
6
4
2
0
0 10 20
V
DD
= 20 V
I
D
= 36 A
30 40 50 Qg (nC )
Figure 8. Normalized on-resistance vs. temperature
R
DS(on)
(norm.)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
-75
10 3
-25
V
GS
= 10 V
25 f = 1 MHz
75
GIPG230220151002ALS
125 T j
(C)
Figure 10. Capacitance variations voltage
C
(pF)
GIPG230220151808ALS
C iss
10 2
0 8 16 24 32 40
C oss
C rss
V
DS
(V)
Figure 11. Source-drain diode forward characteristics
V
SD
(V)
GIPG230220151016ALS
1.0
T j
= -55 °C
T j
= 25°C
T j
= 175°C
0.8
0.6
0.4
5 10 15 20 25 30 35 I
SD
(A)
DS10066 - Rev 3 page 6/17
STL42P4LLF6
Test circuits
3
Test circuits
Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit
Figure 14. Test circuit for inductive load switching and diode recovery times
DS10066 - Rev 3 page 7/17
4
4.1
STL42P4LLF6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
PowerFLAT 5x6 type R package information
Figure 15. PowerFLAT 5x6 type R package outline
DS10066 - Rev 3
A0ER_8231817_Rev20 page 8/17
DS10066 - Rev 3
Dim.
E7
K
L
L1
θ
E2
E3
E4
E5
E6 e
E
D2
D3
D4
D5
D6
A
A1
A2 b
C
D
STL42P4LLF6
PowerFLAT 5x6 type R package information
5.95
3.50
2.35
0.40
0.08
0.20
0.75
1.275
0.60
0.05
0°
Table 7. PowerFLAT 5x6 type R mechanical data mm
Typ.
Min.
0.80
0.02
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
6.00
5.20
4.20
5.00
0.40
0.30
1.27
6.15
0.325
0.90
0.15
Max.
1.00
0.05
0.50
6.20
5.40
4.45
4.35
5.20
0.55
0.45
6.35
3.70
2.55
0.60
0.28
0.45
1.05
1.575
0.80
0.25
12° page 9/17
4.2
STL42P4LLF6
PowerFLAT 5x6 type R SUBCON package information
PowerFLAT 5x6 type R SUBCON package information
Figure 16. PowerFLAT 5x6 type R SUBCON package outline
DS10066 - Rev 3 page 10/17
DS10066 - Rev 3
STL42P4LLF6
PowerFLAT 5x6 type R SUBCON package information
Dim.
E5
H
K
L
L1
L2
P
θ
D1
D2 e
E
E1
E2
E4
A
A1 b b1 c
D
Table 8. PowerFLAT 5x6 type R SUBCON package mechanical data
Min.
0.90
0.35
0.21
mm
Typ.
0.95
0.02
0.40
0.30
0.25
Max.
1.00
0.45
0.06
0.51
1.10
0.51
0.06
4.80
3.91
1.17
5.90
5.70
3.34
0.15
4.90
4.01
1.27
6.00
5.75
3.44
0.25
0.16
0.61
0.61
0.13
0.34
5.10
5.00
4.11
1.37
6.10
5.80
3.54
0.35
0.26
0.71
1.00
8°
1.10
10°
0.71
0.20
0.10
1.20
12° page 11/17
DS10066 - Rev 3
STL42P4LLF6
PowerFLAT 5x6 type R SUBCON package information
Figure 17. PowerFLAT 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_simp_Rev_20 page 12/17
4.3
STL42P4LLF6
PowerFLAT 5x6 packing information
PowerFLAT 5x6 packing information
Figure 18. PowerFLAT 5x6 tape (dimensions are in mm)
Pin 1 identification
(I) Measured from centreline of sprocket hole
to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket
holes is ±0.20.
(III) Measured from centreline of sprocket
hole to centreline of pocket
Base and bulk quantity 3000 pcs
All dimensions are in millimeters
8234350_Tape_rev_C
Figure 19. PowerFLAT 5x6 package orientation in carrier tape
DS10066 - Rev 3 page 13/17
Figure 20. PowerFLAT 5x6 reel
STL42P4LLF6
PowerFLAT 5x6 packing information
DS10066 - Rev 3 page 14/17
STL42P4LLF6
Revision history
Date
28-Jan-2014
25-Feb-2015
18-Feb-2020
Revision
1
2
3
Table 9. Document revision history
Changes
Initial release.
Text edits throughout document
On cover page, updated title, description and features table
Renamed and updated Table 4: Static
Updated Table 5: Dynamic
Updated Table 6: Switching times
Updated Table 7: Source-drain diode
Added Section 2.1: Electrical characteristics (curves)
Renamed and updated Section 4.1 PowerFLAT™ 5x6 type R package information
Renamed and updated Section 5 Packing information
Updated
.
Minor text changes.
DS10066 - Rev 3 page 15/17
STL42P4LLF6
Contents
Contents
DS10066 - Rev 3 page 16/17
STL42P4LLF6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS10066 - Rev 3 page 17/17
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