STD20NF06T4
Datasheet
N-channel 60 V, 32 mΩ typ., 24 A, STripFET II
Power MOSFET in a DPAK package
TAB
DPAK
1
2 3
D(2, TAB)
G(1)
S(3)
AM01475v1_noZen
Features
Order code
STD20NF06T4
V
DS
60 V
• Exceptional dv/dt capability
• 100% avalanche tested
• Low gate charge
R
DS(on)
max.
40 mΩ
I
D
24 A
P
TOT
60 W
Applications
• Switching applications
Description
This Power MOSFET has been developed using STMicroelectronics' unique
STripFET process, which is specifically designed to minimize input capacitance and gate charge. This renders the device suitable for use as primary switch in advanced high-efficiency isolated DC-DC converters for telecom and computer applications, and applications with low gate charge driving requirements.
Product status link
STD20NF06T4
Product summary
Order code STD20NF06T4
Marking
Package
Packing
D20NF06
DPAK
Tape and reel
DS13717 - Rev 1 - May 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
STD20NF06T4
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
DS
V
DGR
V
GS
Drain-source voltage
Drain-gate voltage (R
GS
Gate-source voltage
Parameter
= 20 kΩ)
I
D
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed) I
DM
(1)
P
TOT
dv/dt (2)
E
AS
(3)
T stg
T j
Total power dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
Single pulse avalanche energy
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. I
SD
≤ 24 A, di/dt ≤ 100 A/ns, V
DD
= 80% V
(BR)DSS
3. Starting T j
= 25 °C, I
D
= 10 A, V
DD
= 45 V.
Table 2. Thermal data
Symbol
R thJC
R thJB
(1)
Parameter
Thermal resistance, junction-to-case
Thermal resistance, junction-to-board
1. When mounted on a 1-inch² FR-4, 2 Oz copper board.
Value
60
60
±20
24
17
96
60
10
300
-55 to 175
A
W
V/ns mJ
°C
Unit
V
V
V
A
Value
2.5
50
Unit
°C/W
DS13717 - Rev 1 page 2/14
2
STD20NF06T4
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified).
Table 3. Static
Symbol
V
(BR)DSS
I
DSS
Parameter
I
GSS
V
GS(th)
R
DS(on)
1. Defined by design, not subject to production test.
Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, V
DS
= 60 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
T
C
= 125 °C
(1)
= 60 V,
Gate-body leakage current V
DS
= 0 V, V
GS
= ±20 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 12 A
Min.
60
2
Typ.
Max.
Unit
V
32
1
10
±100
4
40
µA nA
V mΩ
Symbol g fs
C iss
C oss
C rss t d(on) t r t d(off) t f
Q g
Q gs
Q gd
Parameter
Forward transconductance
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Total gate charge
Gate-source charge
Gate-drain charge
Table 4. Dynamic
Test conditions
V
DS
= 25 V, I
D
= 12 A
V
DS
= 25 V, f = 1 MHz, V
V
DD
= 30 V, I
D
V
GS
)
= 10 A, R
G
= 4.7 Ω,
= 10 V (see Figure 13. Test circuit for resistive load switching times
GS
= 0 V
V
DD
= 30 V, I
D
= 20 A, V
GS
= 10 V,
R
G
= 4.7 Ω
(see
Figure 14. Test circuit for gate charge behavior
) -
-
-
-
-
-
-
Min.
-
-
-
-
-
-
-
-
-
-
-
Max.
-
-
-
-
8
23
5
7.5
10
30
30
Typ.
15
690
170
68
Unit
S pF pF pF ns ns ns ns nC
DS13717 - Rev 1 page 3/14
STD20NF06T4
Electrical characteristics
Table 5. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
I t
Q rr rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulse width is limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
Test conditions
V
GS
= 0 V, I
SD
= 24 A
I
SD
= 20 A, di/dt = 100 A/µs,
V
DD
= 30 V, T
J
= 150 °C
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
Min.
-
-
-
-
-
-
Typ.
Max.
24
96
1.5
65
150
Unit
A ns nC
A
V
4.6
A
DS13717 - Rev 1 page 4/14
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
STD20NF06T4
Electrical characteristics (curves)
Figure 2. Thermal impedance
Figure 3. Output characteristics Figure 4. Transfer characteristics
Figure 5. Transconductance Figure 6. Static drain-source on-resistance
DS13717 - Rev 1 page 5/14
Figure 7. Gate charge vs gate-source voltage
STD20NF06T4
Electrical characteristics (curves)
Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage vs temperature
Figure 10. Normalized on-resistance vs temperature
Figure 11. Source-drain diode forward characteristics Figure 12. Normalized V
(BR)DSS
vs temperature
DS13717 - Rev 1 page 6/14
STD20NF06T4
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 14. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS13717 - Rev 1 page 7/14
4
4.1
STD20NF06T4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
ACTIVE 14-Sep-2020 PAGE 5/28
DPAK (TO-252) 2 leads SMD package information
Figure 19. DPAK (TO-252) type A die pad package outline
0068772_2_leads_SMD_Rev_30
DS13717 - Rev 1
Copyright STMicroelectronics ST Restricted Unauthorized reproduction and communication strictly prohibited
NOTICE: This document may have been revised since it was printed. Check Document Management System for latest version before using or copying.
page 8/14
DS13717 - Rev 1
Dim.
L1
L2
L4
R
V2
E1 e e1
H
L c c2
D
D1
E
A
A1
A2 b b4
STD20NF06T4
DPAK (TO-252) 2 leads SMD package information
Table 6. DPAK (TO-252) type A die pad mechanical data mm
Typ.
Min.
4.60
2.159
4.445
9.35
1.00
2.60
0.65
0.60
0.45
0.48
6.00
4.95
6.40
2.20
0.90
0.03
0.64
5.20
5.10
4.70
2.286
4.572
2.80
0.80
0.20
0°
Max.
4.80
2.413
4.699
10.10
1.50
3.00
0.95
1.00
0.60
0.60
6.20
5.25
6.60
2.40
1.10
0.23
0.90
5.40
8° page 9/14
4.2
STD20NF06T4
DPAK (TO-252) 2 leads SMD max die pad package information
Dim.
e1
H
L
L1
L2
L4
R
V2
D
D1
E
E1 e
A
A1
A2 b b4 c c2
DPAK (TO-252) 2 leads SMD max die pad package information
Table 7. DPAK (TO-252) type A max die pad mechanical data mm
Typ.
0.45
0.48
6.00
4.95
6.40
5.10
2.159
Min.
2.20
0.90
0.03
0.64
5.20
4.445
9.35
1.00
2.60
0.65
0.60
5.10
5.20
2.286
4.572
2.80
0.80
0.20
0°
0.60
0.60
6.20
5.25
6.60
5.30
2.413
Max.
2.40
1.10
0.23
0.90
5.40
4.699
10.10
1.50
3.00
0.95
1.00
8°
DS13717 - Rev 1 page 10/14
STD20NF06T4
DPAK (TO-252) 2 leads SMD max die pad package information
Figure 20. DPAK (TO-252) type A recommended footprint (dimensions are in mm)
DS13717 - Rev 1
0068772_2_leads_SMD_footprint page 11/14
Revision history
Date
03-May-2021
Version
1
Table 8. Document revision history
Changes
First release.
STD20NF06T4
DS13717 - Rev 1 page 12/14
STD20NF06T4
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
DPAK (TO-252) 2 leads SMD package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
DPAK (TO-252) 2 leads SMD max die pad package information . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DS13717 - Rev 1 page 13/14
STD20NF06T4
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13717 - Rev 1 page 14/14
