STMicroelectronics STD13N60M6 Datasheet
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STD13N60M6
Datasheet
N-channel 600 V, 320 mΩ typ., 10 A, MDmesh M6 Power MOSFET in a DPAK package
G(1)
TAB
DPAK
1
2 3
D(2, TAB)
S(3)
AM01475V1
Features
Order code
STD13N60M6
V
DS
600 V
R
DS(on)
max.
380 mΩ
• Reduced switching losses
• Lower R
DS(on)
per area vs previous generation
• Low gate input resistance
• 100% avalanche tested
• Zener-protected
I
D
10 A
P
TOT
92 W
Applications
• Switching applications
• LLC converters
• Boost PFC converters
Description
The new MDmesh M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R
DS(on)
per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency.
Product status link
STD13N60M6
Product summary
Order code
Marking
Package
Packing
STD13N60M6
13N60M6
DPAK
Tape and reel
DS13028 - Rev 1 - October 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
STD13N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
I
GS
D
Parameter
Gate-source voltage
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed) I
DM
P
TOT
I
AR
E
AS
T stg
T j
Total power dissipation at T
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness case
= 25 °C
Avalanche current, repetitive or not repetitive
Single pulse avalanche energy
Storage temperature range
Operating junction temperature range
1. Pulse width is limited by safe operating area.
2. Pulse width limited by T jmax
.
3. Starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V.
4. I
SD
≤ 10 A, di/dt = 400 A/μs, V
DS(peak)
< V
(BR)DSS
, V
DD
= 400 V
5. V
DS
≤ 480 V
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
Thermal resistance junction-case
Thermal resistance junction-pcb
Parameter
1. When mounted on an 1-inch² FR-4, 2 Oz copper board.
Value
±25
10
6.4
28
92
2
140
15
100
-55 to 150
Unit
V
A
A
W
A mJ
V/ns
°C
Value
1.36
50
Unit
°C/W
DS13028 - Rev 1 page 2/16
2
STD13N60M6
Electrical characteristics
Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Table 3. Static
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 600 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 600 V,
T case
= 125 °C
Gate-body leakage current V
DS
= 0 V, V
GS
= ±25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 5 A
1. Defined by design, not subject to production test.
Min.
600
3.25
Typ.
Max.
Unit
V
4
320
1
100
±5
4.75
380
µA
µA
V mΩ
Table 4. Dynamic
Symbol
C
C iss
C oss
C rss oss eq.
R
G
Q g
Q
Q gs gd
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
Test conditions
= 100 V, f = 1 MHz, V
GS
= 0 V
V
DS
= 0 to 480 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 480 V, I
D
= 10 A,
V
GS
= 0 to 10 V
(see
Figure 14. Test circuit for gate charge behavior
)
Min.
-
-
-
-
-
-
-
-
Typ.
509
34.4
4.2
94
5.6
13
3.4
6.4
Max.
-
-
-
-
-
-
-
-
Unit pF pF
Ω nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS
increases from 0 to 80% V
DSS
.
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 5. Switching times
Test conditions
V
DD
= 300 V, I
D
= 5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 13. Test circuit for resistive load switching times and
Figure 18. Switching time waveform
)
Min.
-
-
-
-
Typ.
15.8
6.5
25.5
9.4
Max.
-
-
-
-
Unit ns
DS13028 - Rev 1 page 3/16
STD13N60M6
Electrical characteristics
Table 6. Source-drain diode
Symbol
I
SD
I
SDM
V
I
I
SD
Q rr
RRM t t rr
Q rr rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulse width is limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
Test conditions
V
GS
= 0 V, I
SD
= 10 A
I
SD
= 10 A, di/dt = 100 A/µs,
V
DD
= 60 V
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
I
SD
= 10 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C
(see
Figure 15. Test circuit for inductive load switching and diode recovery times
)
-
-
-
Min.
-
-
-
-
-
14.8
253
2
16
Typ.
Max.
10
28
1.6
182
1.35
Unit
A
A
V ns
µC
A ns
µC
A
DS13028 - Rev 1 page 4/16
STD13N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GIPD111020190919SOA
10
10
1
0
10 -1
10 -1 t p
=1µs
I
DM
by R
R
DS(on)
max.
t p
=10µs t p
=100µs t p
=1ms
10
Single pulse, TC =25°C
TJ ≤150°C, VGS =10V
0 10 1
V
(BR)DSS
10 2 t p
=10ms
V
DS
(V)
16
12
8
Figure 3. Typical output characteristics
I
D
(A)
24
GADG171220181338OCH
V
GS
= 10 V
V
GS
= 9 V
V
GS
= 8 V
20
V
GS
= 7 V
4
0
0 4 8 12
V
GS
= 6 V
16 V
DS
(V)
Figure 5. Typical gate charge characteristics
V
DS
(V)
600
500
400
Q gs
300
GADG131220181021QVG V
GS
(V)
V
DD
= 480 V, I
D
= 10 A
12
Q g 10
V
DS
Q gd
8
6
200
100
0
0 3 6 9 12 15
4
2
Q
0 g
(nC)
Figure 2. Maximum transient thermal impedance
Z thJ-C
(°C/W)
GIPD111020190920ZTH
10 0 duty = 0.5
0.4
0.3
0.2
10 -1
0.1
0.05
Single pulse
R thJ-C
= 1.36 °C/W
10 -2
10 -3
10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 t p
(s)
Figure 4. Typical transfer characteristics
I
D
(A)
24
GADG171220181338TCH
V
DS
= 18 V
20
16
12
8
4
0
4 5 6 7 8 9 V
GS
(V)
Figure 6. Typical drain-source on-resistance
R
DS(on)
(mΩ)
GADG010720191204RID
350
340
330
320
310
300
0 2
V
GS
=10 V
4 6 8 10 I
D
(A)
DS13028 - Rev 1 page 5/16
STD13N60M6
Electrical characteristics (curves)
Figure 7. Typical capacitance characteristics
C
(pF)
GADG131220181023CVR
10 3
C
ISS
10 2
10 1 f = 1 MHz
C
OSS
C
RSS
10 0
10 -1 10 0 10 1 10 2
V
DS
(V)
Figure 9. Normalized gate threshold vs temperature
V
GS(th)
(norm.)
1.1
GADG131220181021VTH
1.0
0.9
0.8
0.7
0.6
-75
I
D
= 250 µA
-25 25 75 125 T j
(°C)
Figure 8. Typical output capacitance stored energy
E
OSS
(µJ)
5
GADG131220181023EOS
4
3
2
1
0
0 100 200 300 400 500 600 V
DS
(V)
Figure 10. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.2
GADG131220181022RON
1.8
V
GS
= 10 V
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T j
(°C)
Figure 11. Normalized breakdown voltage vs temperature
V
(BR)DSS
(norm.)
1.08
GADG131220181022BDV
1.04
1.00
0.96
0.92
0.88
-75 -25 25
I
D
= 1 mA
75 125 T j
(°C)
Figure 12. Typical reverse diode forward characteristics
V
SD
(V)
1.1
GADG010720191205SDF
T
J
= -50 °C
1.0
0.9
0.8
0.7
0.6
0.5
0 2 4 6 8
T
J
= 25 °C
T
J
= 150 °C
10 I
SD
(A)
DS13028 - Rev 1 page 6/16
STD13N60M6
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF V
DD
D.U.T.
Figure 14. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
100 Ω D.U.T.
V
G
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
A A fast diode
B
B
G
+
_
R
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS13028 - Rev 1 page 7/16
4
STD13N60M6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DS13028 - Rev 1 page 8/16
4.1
STD13N60M6
DPAK (TO-252) type A2 package information
DPAK (TO-252) type A2 package information
Figure 19. DPAK (TO-252) type A2 package outline
DS13028 - Rev 1
0068772_type-A2_rev26 page 9/16
DS13028 - Rev 1
Dim.
c2
D
D1
E
E1 e e1
A
A1
A2 b b4 c
L2
L4
R
V2
H
L
L1
STD13N60M6
DPAK (TO-252) type A2 package information
Table 7. DPAK (TO-252) type A2 mechanical data mm
Typ.
9.35
1.00
2.60
0.65
0.60
4.95
6.40
5.10
2.159
4.445
0.64
5.20
0.45
0.48
6.00
Min.
2.20
0.90
0.03
5.10
5.20
2.286
4.572
2.80
0.80
0.20
0°
10.10
1.50
3.00
0.95
1.00
5.25
6.60
5.30
2.413
4.699
0.90
5.40
0.60
0.60
6.20
Max.
2.40
1.10
0.23
8° page 10/16
DS13028 - Rev 1
STD13N60M6
DPAK (TO-252) type A2 package information
Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_26 page 11/16
4.2
DPAK (TO-252) packing information
Figure 21. DPAK (TO-252) tape outline
T
Top cover tape
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
STD13N60M6
DPAK (TO-252) packing information
F
E
W
User direction of feed
R
Bending radius
AM08852v1
DS13028 - Rev 1 page 12/16
DS13028 - Rev 1
A
D
B
Figure 22. DPAK (TO-252) reel outline
STD13N60M6
DPAK (TO-252) packing information
T
40mm min. access hole at slot location
C
N
G measured at hub
Full radius
Tape slot in core for tape start
2.5mm min.width
Dim.
E
F
K0
P0
P1
P2
R
T
W
A0
B0
B1
D
D1
AM06038v1
1.5
1.5
1.65
7.4
2.55
3.9
7.9
1.9
40
0.25
15.7
Table 8. DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
N
T
D
G
A
B
C
Min.
1.5
12.8
20.2
16.4
50 1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
mm
Max.
330
13.2
18.4
22.4
2500
2500 page 13/16
Revision history
Date
17-Oct-2019
Version
1
Table 9. Document revision history
Changes
First release.
STD13N60M6
DS13028 - Rev 1 page 14/16
STD13N60M6
Contents
Contents
DS13028 - Rev 1 page 15/16
STD13N60M6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS13028 - Rev 1 page 16/16
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