STD80N240K6
Datasheet
N-channel 800 V, 197 mΩ typ., 16 A MDmesh K6 Power MOSFET in a DPAK package
G(1)
TAB
DPAK
1
2 3
D(2, TAB)
S(3)
Features
Order code
STD80N240K6
V
DS
800 V
• Worldwide best R
DS(on)
x area
• Worldwide best FOM (figure of merit)
• Ultra low gate charge
• 100% avalanche tested
• Zener-protected
R
DS(on)
max.
220 mΩ
I
D
16 A
Applications
• Flyback converter
• Adapters for tablets, notebook and AIO
• LED Lighting
AM01476v1_tab
Description
This very high voltage N-channel Power MOSFET is designed using the ultimate
MDmesh K6 technology based on 20 years STMicroelectronics experience on super junction technology. The result is the best-in-class on-resistance per area and gate charge for applications requiring superior power density and high efficiency.
Product status link
STD80N240K6
Product summary
Order code
Marking
Package
Packing
STD80N240K6
80N240K6
DPAK
Tape and reel
DS13793 - Rev 2 - February 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STD80N240K6
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
I
D
I
D
I
DM
(1)
P
TOT dv/dt
(2)
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Parameter
Total power dissipation at T
C
= 25 °C
Peak diode recovery voltage slope dv/dt
(2)
dv/dt
(3)
T stg
T
J
Peak diode recovery current slope
MOSFET dv/dt ruggedness
Storage temperature range
Operating junction temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 4 A; V
DS
(peak) = 400 V
3. V
DS
≤ 640 V
Table 2. Thermal data
Symbol
R thJC
R thJB
(1)
Parameter
Thermal resistance, junction-to-case
Thermal resistance, junction-to-board
1. When mounted on an 1-inch² FR-4, 2 Oz copper board.
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T
J
max.)
Single pulse avalanche energy (starting T
J
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
±30
16
10
35
105
5
100
120
-55 to 150
Unit
V
A
A
A
W
V/ns
A/µs
V/ns
°C
Value
1.19
50
Value
3.3
200
Unit
°C/W
°C/W
Unit
A mJ
DS13793 - Rev 2 page 2/16
2
STD80N240K6
Electrical characteristics
Electrical characteristics
T
C
= 25 °C unless otherwise specified.
Table 4. On/off-state
Symbol
V
(BR)DSS
I
DSS
Parameter
I
GSS
V
GS(th)
R
DS(on)
1. Specified by design, not tested in production.
Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 1 mA
V
GS
= 0 V, V
DS
= 800 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 800 V, T
C
= 125 °C
(1)
Gate body leakage current
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 100 µA
Static drain-source on-resistance V
GS
= 10 V, I
D
= 7 A
Min.
Typ.
Max.
Unit
800 V
1
50
µA
µA
3 3.5
±1
4
197 220
µA
V mΩ
Table 5. Dynamic
Symbol
C iss
C oss
Parameter
Input capacitance
Output capacitance
V
DS
Test conditions
= 400 V, f = 1 MHz, V
GS
= 0 V
Min.
-
-
Typ.
1350
20
Max.
-
-
Unit pF pF
C
C o(er) o(tr)
R g
Q g
Q gs
Q gd
(1)
(2)
Equivalent capacitance time related
Equivalent capacitance energy related
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V f = 1 MHz , I
V
DS
DD
= 0 to 640 V, V
(see
D
= 640 V, I
= 0 A
D
charge behavior )
GS
= 0 V
= 7 A, V
GS
= 0 to 10 V
Figure 19. Test circuit for gate
-
-
-
-
-
-
139
25
1.8
25.9
6.9
8.4
-
-
-
-
-
pF pF
Ω nC nC nC
1. C o(er) value.
is a constant capacitance value that gives the same stored energy as C oss
while V
DS
is rising from 0 V to the stated
2. C o(tr)
is a constant capacitance value that gives the same charging time as C oss
while V
DS value.
is rising from 0 V to the stated
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 400 V, I
D
=7 A, R
G
= 4.7 Ω
V
GS
= 10 V see (
Figure 17. Test circuit for resistive load switching times and
Figure 18. Switching time waveform )
Min.
Typ.
Max.
Unit
16 ns
-
-
-
5.3
47.8
12
-
-
ns ns ns
DS13793 - Rev 2 page 3/16
STD80N240K6
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
(1)
V
SD
(2)
t rr
Q rr
I
RRM t rr
I
Q rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
I
I
SD
SD
Test conditions
= 14 A, V
GS
= 0 V
= 14 A, di/dt = 100 A/µs, V
DD
(see
= 60 V
Figure 20. Test circuit for inductive load switching and diode recovery times
I
SD
= 14 A, di/dt = 100 A/µs, V
DD
= 60 V,
T
J
= 150 °C
(see
Figure 20. Test circuit for inductive load switching and diode recovery times )
)
-
-
-
-
-
Min.
Typ.
Max.
Unit
14 A
-
35
1.5
A
V
335
5.4
27.5
430
7.4
ns
µC
A ns
µC
28 A
DS13793 - Rev 2 page 4/16
STD80N240K6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
GADG190720211222SOA
I
DM
10 1
in
this area
R
DS(on)
max.
10 0
10 -1
10 -1 10 0
T
C
T
J
= 25 °C
≤ 150 °C single pulse
10 1 10 2 10 3 t p
=1 µs t p
=10 µs t p
=100 µs t p
=1 ms t p
=10 ms
V
(BR)DSS
V
DS
(V)
20
15
10
Figure 3. Typical output characteristics
I
D
(A)
30
V
GS
=7, 8, 9, 10 V
GADG240620211241OCH
25
V
GS
=6 V
5
0
0 4 8 12
V
GS
=5 V
16 V
DS
(V)
Figure 5. Typical gate charge characteristics
V
DS
(V)
600
500
400
300
Q gs
I
V
DD
D
GADG240620211243QVG
= 640 V
= 7 A
V
GS
(V)
12
Q g
V
GS
10
8
Q gd
6
200
100
0
0
V
DS
5 10 15 20 25 30
4
2
Q
0 g
(nC)
Figure 2. Maximum transient thermal impedance
Z thJC
(°C/W)
GADG190720211222ZTH
4
10 0 duty=0.5
3
2
10 -1
0.05
10 -2
R thJC
= 1.19 °C/W duty = t on
/ T
Single pulse t on
T
10 -3
10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
20
15
10
Figure 4. Typical transfer characteristics
I
D
(A)
30
V
DS
= 20 V
GADG240620211242TCH
25
5
0
4 5 6 7 V
GS
(V)
Figure 6. Typical drain-source on-resistance
R
DS(on)
(mΩ)
GADG240620211242RID
V
GS
= 10 V
210
200
190
180
0 2 4 6 8 10 12 I
D
(A)
DS13793 - Rev 2 page 5/16
STD80N240K6
Electrical characteristics (curves)
Figure 7. Typical capacitance characteristics
C
(pF)
10 4
GADG240620211244CVR
10 3
C
ISS
10 2
10 1
10 0
10 -1
10 -2
10 -1 f = 1 MHz
10 0 10 1 10 2
C
OSS
C
RSS
V
DS
(V)
Figure 9. Normalized gate threshold vs temperature
V
GS(th)
(norm.)
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
-75
I
D
= 100 μA
-25 25
GADG240620211244VTH
75 125 T j
(°C)
Figure 8. Typical output capacitance stored energy
E
OSS
(µJ)
GADG240620211245EOS
6
4
2
0
0 100 200 300 400 500 600 700 V
DS
(V)
Figure 10. Normalized on-resistance vs temperature
R
DS(on)
(norm.)
2.2
V
GS
= 10 V
GADG240620211243RON
1.8
1.4
1.0
0.6
0.2
-75 -25 25 75 125 T j
(°C)
Figure 11. Normalized breakdown voltage vs temperature
V
(BR)DSS
(norm.)
1.08
I
D
= 1 mA
GADG240620211245BDV
1.04
Figure 12. Typical reverse diode forward characteristics
V
SD
(V)
1.0
GADG240620211247SDF
T j
= -50 °C
0.9
1.00
0.8
T j
= 25 °C
0.96
0.7
T j
= 150 °C
0.92
0.88
-75 -25 25 75 125 T j
(°C)
0.6
0.5
2 4 6 8 10 12 14 I
SD
(A)
DS13793 - Rev 2 page 6/16
DS13793 - Rev 2
Figure 13. Maximum avalanche energy vs temperature
E
AS
(mJ)
200
GADG240620211246EAS
I
Single pulse
D
V
= 3.3 A
DD
=50 V
160
120
80
40
0
-75 -25 25 75 125 T
J
(°C)
STD80N240K6
Electrical characteristics (curves)
Figure 14. Typical output capacitance stored energy
E
OSS
(µJ)
GADG240620211245EOS
6
4
2
0
0 100 200 300 400 500 600 700 V
DS
(V)
Figure 15. Typical inductive load switching energy vs I
D
E
(μJ)
GADG240620211251SLI
R
G
= 4.7 Ω
Figure 16. Typical inductive load switching energy vs Rg
E
(μJ)
GADG240620211252SLG
ON
90 120
I
D
= 7 A
ON
60 80
OFF
30 40
OFF
0
0 3 6 9 12 I
D
(A)
0
0 9 18 27 36 45 R
G
(Ω) page 7/16
STD80N240K6
Test circuits
3
Test circuits
Figure 17. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 19. Test circuit for gate charge behavior
V
DD
RL
V
GS pulse width
2200
μF
+
I
G
= CONST
2.7 kΩ
47 kΩ
1 kΩ
100 Ω D.U.T.
V
G
AM01469v10
Figure 21. Unclamped inductive load test circuit
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
Figure 18. Switching time waveform
V
DS
90%
V
GS
10% t d(on) t r t d(off) t f
GADG280620211209SA
Figure 20. Test circuit for inductive load switching and diode recovery times
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
3.3
µF
S
+
1000
µF
V
DD
AM01470v1
Figure 22. Unclamped inductive waveform
V
(BR)DSS
V
D
I
DM
I
D
V
DD
V
DD
AM01472v1
DS13793 - Rev 2 page 8/16
4
4.1
STD80N240K6
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DPAK (TO-252) type A2 package information
Figure 23. DPAK (TO-252) type A2 package outline
DS13793 - Rev 2
0068772_type-A2_rev30 page 9/16
DS13793 - Rev 2
Dim.
L1
L2
L4
R
V2
E1 e e1
H
L c c2
D
D1
E
A
A1
A2 b b4
STD80N240K6
DPAK (TO-252) type A2 package information
Table 8. DPAK (TO-252) type A2 mechanical data mm
Typ.
Min.
5.10
2.159
4.445
9.35
1.00
2.60
0.65
0.60
0.45
0.48
6.00
4.95
6.40
2.20
0.90
0.03
0.64
5.20
5.10
5.20
2.286
4.572
2.80
0.80
0.20
0°
Max.
5.30
2.413
4.699
10.10
1.50
3.00
0.95
1.00
0.60
0.60
6.20
5.25
6.60
2.40
1.10
0.23
0.90
5.40
8° page 10/16
DS13793 - Rev 2
STD80N240K6
DPAK (TO-252) type A2 package information
Figure 24. DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_30 page 11/16
4.2
DPAK (TO-252) packing information
Figure 25. DPAK (TO-252) tape outline
T
Top cover tape
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
STD80N240K6
DPAK (TO-252) packing information
F
E
W
User direction of feed
R
Bending radius
AM08852v1
DS13793 - Rev 2 page 12/16
DS13793 - Rev 2
A
D
B
Figure 26. DPAK (TO-252) reel outline
STD80N240K6
DPAK (TO-252) packing information
T
40mm min. access hole at slot location
C
N
G measured at hub
Full radius
Tape slot in core for tape start
2.5mm min.width
Dim.
P2
R
T
W
K0
P0
P1
E
F
A0
B0
B1
D
D1
AM06038v1
1.5
1.5
1.65
7.4
2.55
3.9
7.9
1.9
40
0.25
15.7
Table 9. DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
C
D
G
A
B
N
T
Min.
1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
1.5
12.8
20.2
16.4
50 mm
Max.
330
13.2
18.4
22.4
2500
2500 page 13/16
Revision history
Date
22-Jul-2021
17-Feb-2022
Revision
1
2
Table 10. Document revision history
Changes
First release.
Updated Section Applications on cover page.
Updated Table 5. Dynamic
.
Updated Figure 15. Typical inductive load switching energy vs I
D
.
Updated Figure 16. Typical inductive load switching energy vs Rg .
Minor text changes.
STD80N240K6
DS13793 - Rev 2 page 14/16
STD80N240K6
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1
DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DS13793 - Rev 2 page 15/16
STD80N240K6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS13793 - Rev 2 page 16/16
