STL8DN6LF3
Datasheet
Automotive-grade dual N-channel 60 V, 22.5 mΩ typ., 7.8 A STripFET F3
Power MOSFET in a PowerFLAT 5x6 double island package
Features
Order code
STL8DN6LF3
V
DS
60 V
R
DS(on)
max.
30 mΩ
I
D
7.8 A
1 S2
2 G2
3 S1
4 G1
Drain on rear side
D2
D1
8
7
6
5
NG14G22D1D2RSS13S21
• AEC-Q101 qualified
• Logic level V
GS(th)
• 175 °C maximum junction temperature
• 100% avalanche rated
• Wettable flank package
Applications
• Switching applications
Description
This device is an N-channel Power MOSFET developed using STripFET F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance.
Product status link
STL8DN6LF3
Product summary
Order code
Marking
Package
Packing
STL8DN6LF3
8DN6LF3
PowerFLAT 5x6 double island
Tape and reel
DS8667 - Rev 7 - March 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STL8DN6LF3
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
GS
V
DS
I
I
D
(1)
I
D
D
(2)
I
DM
(2)(3)
P
TOT
P
TOT
(2)
I
AV
E
AS
(4)
T stg
T
J
Gate-source voltage
Parameter
Drain-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (continuous) at T pcb
= 25 °C
Drain current (continuous) at T pcb
= 100 °C
Drain current (pulsed)
Total power dissipation at T
C
= 25 °C
Total power dissipation at T pcb
= 25 °C
Non-repetitive avalanche current
Single pulse avalanche energy
Storage temperature range
Operating junction temperature range
1. Current is limited by bonding, with R thJC
= 2.3 °C/W; the chip is able to carry 30 A at 25 °C.
2. When mounted on an 1 inch² 2 Oz. Cu board, t < 10 s.
3. Pulse width is limited by safe operating area.
4. Starting T
J
= 25 °C, I
D
= I
AS
, V
DD
= 25 V.
Table 2. Thermal data
Symbol
R thj-case
R thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Parameter
1. When mounted on an 1 inch² 2 Oz. Cu board, t < 10 s.
20
7.8
5.5
31.2
65
Value
±20
60
20
4.3
7.8
190
-55 to 175
Value
2.3
35
Unit
°C/W
A
A
A
A
W
Unit
V
V
A
W
A mJ
°C
°C
DS8667 - Rev 7 page 2/15
2
STL8DN6LF3
Electrical characteristics
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Table 3. On/off states
Parameter Test conditions
Drain-source breakdown voltage V
GS
= 0 V, I
D
= 250 µA
Zero gate voltage drain current V
GS
= 0 V, V
DS
= 60 V
Gate-body leakage current
Gate threshold voltage
V
DS
= 0 V, V
GS
= ±20 V
V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on-resistance
V
GS
= 10 V, I
D
= 4 A
V
GS
= 5 V, I
D
= 4 A
Min.
Typ.
Max.
Unit
60
1
V
µA
1
22.5
30
±100 nA
2.5
30
44
V mΩ mΩ
Symbol
C iss
C oss
C rss
Q g
Q gs
Q gd
R
G
Parameter
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Intrinsic gate resistance
V
Table 4. Dynamic
DS
Test conditions
= 25 V, f = 1 MHz, V
GS
= 0 V
V
DD
= 30 V, I
D
= 7.8 A, V
GS
= 0 to 10 V
(see
Figure 13. Test circuit for gate charge behavior )
f = 1 MHz open drain -
-
-
-
Min.
Typ.
Max.
Unit
-
-
-
668
144
14
-
-
pF pF pF
13
2.4
3
4
-
-
-
nC nC nC
Ω
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 5. Switching times
Test conditions
V
DD
= 30 V, I
D
= 4 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 12. Test circuit for resistive load switching times
and
Figure 17. Switching time waveform )
Min.
Typ.
Max.
Unit
9 ns
-
-
-
7.7
32.5
5
-
-
ns ns ns
DS8667 - Rev 7 page 3/15
STL8DN6LF3
Electrical characteristics
Table 6. Source drain diode
Symbol
I
SD
I
SDM
V
I
SD
(2)
t
Q rr rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
V
GS
= 0 V, I
SD
= 7.8 A
I
SD
= 7.8 A, di/dt = 100 A/µs,
V
DD
= 48 V, T
J
= 150 °C
(see
Figure 14. Test circuit for inductive load switching and diode recovery times )
1. Pulse width is limited by safe operating area.
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
Min.
Typ.
Max.
Unit
7.8
A
-
31.2
1.3
A
V
-
30
35 ns nC
2.35
A
DS8667 - Rev 7 page 4/15
STL8DN6LF3
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
I
D
(A)
Figure 1. Safe operating area
AM13006v1
Tj=175°C
Tpcb=25°C
Single pulse
10
Operation in
Limited
by max R
1
0.1
0.1
1 10
10ms
V
DS
(V)
100ms
1s
15
10
5
0
0
I D
(A)
Figure 3. Output characteristics
V
GS
=10V
4V
25
AM13008v1
20
1 2 3 4
3V
V DS (V)
Figure 5. Normalized V
(BR)DSS
vs. temperature
V
(BR)DSS
(norm)
AM13010v1
I D =250 µA
1.10
1.06
1.02
0.98
0.94
0.90
-75 -25 25 75 125 T J (°C)
Figure 2. Thermal impedance
K d =0.5
0.2
10 -1
0.1
0.02
0.05
0.01
Zth_AM13007v1 pcb
10
-2
10 -3
10 -4
Single pulse
10 -3 10 -2
10 -1 10 0 10 1 t p
(s)
10
5
0
0
20
15
Figure 4. Transfer characteristics
I D
(A)
25
V DS =3V
AM13009v1
1 2 3 4 V GS (V)
Figure 6. Static drain-source on-resistance
AM13011v1
R
DS(on)
(mΩ)
V
GS
= 10 V
23
22.8
22.6
22.4
22.2
22
2 3 4 5 6 7 I
D
(A)
DS8667 - Rev 7 page 5/15
STL8DN6LF3
Electrical characteristics (curves)
Figure 7. Gate charge vs. gate-source voltage
AM13012v1
V
GS
(V)
10
V
DD
=30V
I D =7.8A
8
6
4
2
0
0 2 4 6 8 10 12 14 Q g (nC)
C
(pF)
1000
100
Figure 8. Capacitance variations
AM13013v1
Ciss
Coss
10
0 10 20 30 40 50
Crss
V DS (V)
Figure 9. Normalized gate threshold voltage vs. temperature
AM13014v1
V
GS(th)
(norm) I D =250µA
1.2
Figure 10. Normalized on-resistance vs. temperature
AM13015v1
R
DS(on)
(norm)
V GS =10V
2.0
1.6
1.0
1.2
0.8
0.8
0.6
0.4
-75 -25 25 75 125 T J (°C)
0.4
0
-75 -25 25 75 125 T
J
(°C)
Figure 11. Source-drain diode forward characteristics
AM13016v1
V
SD
(V) T
J
=-55°C
0.9
T
J
=25°C
0.8
0.7
0.6
0.5
0.4
2 3 4 5 6
T
J
=175°C
7 I
SD
(A)
DS8667 - Rev 7 page 6/15
STL8DN6LF3
Test circuits
3
Test circuits
Figure 12. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 14. Test circuit for inductive load switching and diode recovery times
Figure 13. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
I
G
= CONST
2.7 kΩ
47 kΩ
1 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 15. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
S
3.3
µF +
1000
µF
V
DD
AM01470v1
Figure 16. Unclamped inductive waveform
V (BR)DSS
V D
I DM
I D
V DD V
DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 17. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS8667 - Rev 7 page 7/15
4
4.1
STL8DN6LF3
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
PowerFLAT 5x6 double island WF type R package information
Figure 18. PowerFLAT 5x6 double island WF type R package outline
DS8667 - Rev 7
8256945_typeR-WF_R18 page 8/15
DS8667 - Rev 7
STL8DN6LF3
PowerFLAT 5x6 double island WF type R package information
Dim.
E6
E7
E8
E9
E10
K
L
L1
θ
E
E2
E3
E4
E5
D2
D3
D4
D5
D6
D7 e
A
A1
A2 b
C
D
Table 7. PowerFLAT 5x6 double island WF type R mechanical data mm
Typ.
Min.
0.80
0.02
0.25
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
1.68
6.00
5.20
4.20
5.00
0.40
0.30
1.27
6.40
0.20
0.85
0.55
4.00
3.55
6.20
3.50
2.35
0.40
0.08
1.275
0.725
0.175
0°
0.325
1.00
4.20
3.70
0.825
0.275
Max.
1.00
0.05
0.45
1.15
0.75
4.40
3.85
6.60
3.70
2.55
0.60
0.28
1.575
0.925
0.375
12°
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
1.98
page 9/15
DS8667 - Rev 7
STL8DN6LF3
PowerFLAT 5x6 double island WF type R package information
Figure 19. PowerFLAT 5x6 double island recommended footprint (dimensions are in mm)
8256945_DI_FP_smp_R18 page 10/15
4.2
STL8DN6LF3
PowerFLAT 5x6 WF packing information
PowerFLAT 5x6 WF packing information
T
0.30 0.05
Figure 20. PowerFLAT 5x6 WF tape (dimensions are in mm)
Do
+ 0.1
1.50
0.0
P2
2.0
0.05(I)
Y
Po
4.0 0.1(II)
D1
1.50 MIN
E1
1.75 0.1
R0.30
MAX
Ko (1.20±0.1)
SECTION Y-Y
P1(8.00±0.1)
Y
Ao(6.70±0.1)
(I)
(II)
(III)
Measured from centreline of sprocket hole to centreline of pocket.
Cumulative tolerance of 10 sprocket holes is ± 0.20 .
Measured from centreline of sprocket hole to centreline of pocket.
Base and bulk qua ntity 3000 pcs
Figure 21. PowerFLAT 5x6 package orientation in carrier tape
8234350_TapeWF_rev_C
Pin 1 identification
DS8667 - Rev 7 page 11/15
STL8DN6LF3
PowerFLAT 5x6 WF packing information
PART NO.
Figure 22. PowerFLAT 5x6 reel (dimensions are in mm)
R0.60
W3
11.9/15.4
1.90
2.50
W2
18.4 (max)
R25.00
∅ 4.00
ØN
178(±2.0)
∅ 2.50
77 ESD LOGO
W1
12.4 (+2/-0)
06
PS
128
ØA
Ø21.2
R1.10
∅ 13.00
CORE DETAIL
All dimensions are in millimeters
A
330 (+0/-4.0)
8234350_Reel_rev_C
DS8667 - Rev 7 page 12/15
STL8DN6LF3
Revision history
Date
11-Oct-2011
19-Jun-2012
26-Jun-2012
24-Oct-2013
20-Feb-2014
11-May-2017
04-Mar-2020
Revision
1
2
3
4
5
6
7
Table 8. Document revision history
Changes
•
•
•
•
•
•
•
•
•
First release.
Added Section 2.1: Electrical characteristics (curves) . Updated Section 4: Package mechanical data and title on the cover page.
Document status promoted from preliminary to production data.
Updated title and features in cover page
Modified: VGS(th) value in Table 4
Updated: Section 4: Package mechanical data and Section 5: Packaging mechanical data
Minor text changes
Added: Features in cover page
Added: note 1 in Table 1
Added: Table 20 and Table 9
Added: Figure 23
Minor text changes
Updated title and description on cover page.
Updated Figure 6: "Normalized V(BR)DSS vs. temperature" and Figure 11: "Normalized onresistance vs. temperature" .
Updated Section 4: "Package information"
Minor text changes
Updated Section 4 Package information .
Minor text changes.
DS8667 - Rev 7 page 13/15
STL8DN6LF3
Contents
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
PowerFLAT 5x6 double island WF type R package information . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
PowerFLAT 5x6 WF packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
DS8667 - Rev 7 page 14/15
STL8DN6LF3
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS8667 - Rev 7 page 15/15
