STL105DN4LF7AG
Automotive-grade dual Nchannel 40 V, 3.5 mΩ typ., 40 A
STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 DI
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code V
DS
R
DS(on)
max. I
D
STL105DN4LF7AG 40 V 4.5 mΩ
AEC-Q101 qualified
Among the lowest R
DS(on)
on the market
Excellent FoM (figure of merit)
Low C rss
/C iss
ratio for EMI immunity
High avalanche ruggedness
Wettable flank package
40 A
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching.
Order code
STL105DN4LF7AG
Marking
105DN4L
Table 1: Device summary
Package
PowerFLAT™ 5x6 double island
January 2018 DocID031358 Rev 1
This is information on a product in full production.
Packing
Tape and reel
1/16 www.st.com
Contents
Contents
STL105DN4LF7AG
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
PowerFLAT 5x6 double island WF type C package information ..... 10
Packing information ......................................................................... 13
5 Revision history ............................................................................ 15
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STL105DN4LF7AG
1 Electrical ratings
Symbol
V
DS
V
GS
I
D
(1)
I
D
(1)
I
DM
(2)
P
TOT
T j
T stg
Table 2: Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Operating junction temperature range
Storage temperature range
Electrical ratings
Value
40
±20
40
40
160
94
-55 to 175
Notes:
(1)
Drain current is limited by package, the current capability of the silicon is 105 A at 25 °C and 74 A at 100 °C.
(2)
Pulse width limited by safe operating area.
Symbol
Table 3: Thermal data
Parameter Value Unit
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
1.6
32
°C/W
°C/W
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s.
Unit
V
V
A
A
A
W
°C
DocID031358 Rev 1 3/16
Electrical characteristics
2 Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 4: On/Off states
Test conditions
V
(BR)DSS
I
DSS
Drain-source breakdown voltage
Zero gate voltage drain current
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
I
D
= 1 mA, V
GS
= 0 V
V
GS
= 0 V
V
DS
= 40 V
V
GS
= ±20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= 10 V, I
D
= 12 A
V
GS
= 4.5 V, I
D
= 12 A
Symbol Parameter
Table 5: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd t f
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time
Fall time
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 20 V, I
D
= 24 A,
V
GS
= 0 to 10 V (see Figure
14: "Test circuit for gate charge behavior" )
Table 6: Switching times
Test conditions
V
DD
= 32 V, I
D
= 12 A,
R
G
= 4.7 Ω, V
GS
= 10 V (see
Figure 13: "Test circuit for resistive load switching times" and Figure 18:
"Switching time waveform" )
STL105DN4LF7AG
Min. Typ. Max. Unit
40
10
V
µA
100 nA
1.5
3.5
5.3
2.5
4.5
8
V mΩ
Min. Typ. Max. Unit
-
-
1594
415
-
- pF
- 48 -
-
-
-
27.5
5.5
6.1
-
-
- nC
Min. Typ. Max. Unit
-
-
-
11
8.5
48.5
-
-
- ns
- 15 -
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STL105DN4LF7AG
Symbol Parameter
I
SD
(1)
Source-drain current
I
SDM
(2)
Source-drain current
(pulsed)
V
SD
(3)
Forward on voltage t rr
Reverse recovery time
I
Q rr
RRM
Table 7: Source-drain diode
Test conditions
Reverse recovery charge
Reverse recovery current
I
SD
= 40 A, V
GS
= 0 V
I
SD
= 24 A, di/dt = 100 A/µs,
V
DD
= 32 V
(see Figure 15: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
29.3
- 22.5
1.5
40
160
1.3
A
A
V ns nC
A
Notes:
(1)
Drain current is limited by package, the current capability of the silicon is 105 A at 25 °C.
(2)
Pulse width limited by safe operating area .
(3)
Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
DocID031358 Rev 1 5/16
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STL105DN4LF7AG
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
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STL105DN4LF7AG
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V
(BR)DSS
vs temperature
Figure 12: Source-drain diode forward characteristics
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Test circuits
3 Test circuits
Figure 13: Test circuit for resistive load switching times
STL105DN4LF7AG
Figure 14: Test circuit for gate charge behavior
Figure 15: Test circuit for inductive load switching and diode recovery times
Figure 16: Unclamped inductive load test circuit
Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
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STL105DN4LF7AG
4 Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID031358 Rev 1 9/16
Package information
4.1
STL105DN4LF7AG
PowerFLAT 5x6 double island WF type C package information
Figure 19 : PowerFLAT™ 5x6 double island WF type C package outline
10/16 DocID031358 Rev 1
826945_DI_WF_typeC_r16
STL105DN4LF7AG
Dim.
Package information
Table 8: PowerFLAT™ 5x6 double island WF type C mechanical data mm
Min. Typ. Max.
E3
E4
E5
E6
E7
E8
E9
E10
L
L1
K
ϴ
D4
D5
D6
D7 e
E
E2
C
D
D2
D3
A
A1
A2 b
0.80
0.02
0.55
4.00
3.55
0.90
0.175
1.05
0°
6.20
3.50
2.35
0.40
0.08
0.20
0.85
0.30
5.80
5.00
4.15
4.05
4.80
0.25
0.15
1.68
0.25
6.00
5.20
4.20
5.00
0.40
0.30
1.27
6.40
0.325
1.00
4.20
3.70
1.00
0.275
1.00
0.05
0.50
6.10
5.40
4.45
4.35
5.10
0.55
0.45
1.98
0.75
4.40
3.85
1.10
0.375
1.35
12°
6.60
3.70
2.55
0.60
0.28
0.45
1.15
DocID031358 Rev 1 11/16
Package information STL105DN4LF7AG
Figure 20
: PowerFLAT™ 5x6 double island recommended footprint (dimensions are in mm)
8256945_FP_std_R16
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STL105DN4LF7AG
4.2 Packing information
Package information
Figure 21
: PowerFLAT™ 5x6 WF tape (dimensions are in mm)
Figure 22
: PowerFLAT™ 5x6 package orientation in carrier tape
DocID031358 Rev 1 13/16
Package information STL105DN4LF7AG
Figure 23
: PowerFLAT™ 5x6 reel (dimensions are in mm)
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STL105DN4LF7AG
5
Revision history
Revision history
Date
10-Jan-2018
Table 9: Document revision history
Revision
1
Changes
First release.
DocID031358 Rev 1 15/16
STL105DN4LF7AG
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