STA510F
44 V, 5.5 A, quad power half-bridge
PSSO36 (slug up)
Features
• Minimum input/output pulse width distortion
• 150 m Ω R
DS(on)
complementary DMOS output stage
• CMOS compatible logic inputs
• Thermal protection
• Thermal warning output
• Undervoltage protection
• No power-on, power-off sequence required
Datasheet
-
production data
Description
The STA510F is a monolithic, quad, half-bridge stage in multipower BCD technology. The device can be used as dual-bridge or reconfigured, by connecting the CONFIG pin to the Vdd pin, as single-bridge with double current capability, and as half-bridge (binary mode).
The device is particularly designed to make the output stage of a stereo all-digital high-efficiency
(FFX) amplifier capable of delivering 100 W +
100 W output power into 6 Ω loads with
THD = 10% and V
CC
= 36 V. In single BTL configuration the device can deliver 200 W into a
3 Ω load with THD = 10% and V
CC
= 36 V.
The device is fully compatible with the FFX
® driver device.
The input pins have a threshold proportional to V
L pin voltage.
Order code
STA510FTR
Table 1. Device summary
Operating temp. range Package
0° to 70° C PSSO36 (slug up)
Packing
Tape and reel
December 2018
This is information on a product in full production.
DocID014268 Rev 5 1/26 www.st.com
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5
6
7
8
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2
3
Contents
Contents
STA510F
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
Theoretical filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2
Optimized filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks and other acknowledgments . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26 DocID014268 Rev 5
STA510F
PWM Out1_A
PWM Out2_A
STA311B
PWM Out1_B
PWM Out2_B
Figure 1. Typical application
Output Filter
IN 1A
IN 2A
IN 1B
STA510F
IN 2B
OUT 1A
OUT 1B
OUT 2A
OUT 2B
IN A
IN B
OUT A
OUT B
Output Filter
IN A
IN B
OUT A
OUT B
Vcc
PSU
GND
Application diagram
DocID014268 Rev 5 3/26
26
Pin description
4/26
V
CC
Sign
V
CC
Sign
V
SS
V
SS
IN2B
IN2A
IN1B
IN1A
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
V
L
VDD
VDD
GND-Reg
GND-Clean
25
24
23
22
21
20
19
31
30
29
28
36
35
34
33
32
27
26
Figure 2. Pin connections (top view)
12
13
14
15
16
17
18
10
11
6
7
8
9
1
2
3
4
5
OUT2A
OUT1B
OUT1B
V
CC
1B
GND1B
GND1A
V
CC
1A
OUT1A
OUT1A
N.C.
GND-SUB
OUT2B
OUT2B
V
CC
2B
GND2B
GND2A
V
CC
2A
OUT2A
Pin
1
2, 3
4
5
6
7
8, 9
10, 11
12
13
14
15
16, 17
18
Table 2. Pin list
Name
GND-SUB Substrate ground
OUT2B Output half-bridge 2B
Vcc2B
GND2B
GND2A
Vcc2A
OUT2A
OUT1B
Positive supply
Negative supply
Negative supply
Positive supply
Output half-bridge 2A
Output half-bridge 1B
Vcc1B
GND1B
GND1A
Vcc1A
OUT1A
NC
Positive supply
Negative supply
Negative supply
Positive supply
Output half-bridge 1A
Not connected
Description
DocID014268 Rev 5
STA510F
STA510F
Pin
26
27
28
29
30
31
32
33, 34
35, 36
19
20
21, 22
23
24
25
Name
Table 2. Pin list (continued)
Description
GND-clean Logical ground
GND-Reg Ground for regulator Vdd
V
DD
V
L
5-V regulator referred to ground
High logical state setting voltage
CONFIG Configuration
PWRDN Standby
TRI-STATE Hi-Z
FAULT Fault pin advisor
TH-WAR Thermal warning advisor
IN1A Input of half-bridge 1A
IN1B
IN2A
IN2B
Input of half-bridge 1B
Input of half-bridge 2A
Input of half-bridge 2B
Vss 5-V regulator referred to +V
CC
VCCSIGN Signal positive supply
Table 3. Pin values
FAULT
THWAR
(1)
TRI-STATE
PWRDN
CONFIG
(1)
(2)
0
1
0
1
0
1
0
1
0
1
Fault detected (short-circuit, or thermal)
Normal operation
All power stages in Hi-Z state
Normal operation
Low-power mode
Normal operation
Temperature of the IC = 130 °C
Normal operation
Normal operation
OUT1A = OUT1B, OUT2A = OUT2B
(IF IN1A = IN1B and IN2A = IN2B)
1.
The pin is open collector. To have the high logic value, it needs a pull-up resistor.
2.
CONFIG = 1 means connect pin 24 (CONFIG) to pins 21, 22 (V
DD
).
Pin description
DocID014268 Rev 5 5/26
26
Electrical specifications STA510F
Symbol
V
CC
V max
ESD
T op
T stg
, T j
Table 4. Absolute maximum ratings
Parameter
DC supply voltage (pin 4, 7, 12, 15)
Maximum voltage on pins 23 to 32
Max ESD on pins (HBM)
Operating temperature range
Storage and junction temperature
Value
44
5.5
±1000
0 to 70
-40 to 150
Unit
V
V
V
°C
°C
Symbol
T j-case
T jSD
T warn t hSD
Table 5. Thermal data
Parameter
Thermal resistance junction to case (thermal pad)
Thermal shut-down junction temperature
Thermal warning temperature
Thermal shutdown hysteresis
Min.
Typ.
Max.
Unit
1
150
130
25
2.5
°C/W
°C
°C
°C
The results in
Table 6
below are given for the conditions: V
L
T = 25 °C unless otherwise specified.
= 3.3 V, V
CC
= 37 V and
Symbol
R dsON
I dss g
N g
P
Dt_s
Dt_d t d ON
Parameter
Table 6. Electrical specifications
Conditions
Power P-channel/N-channel
MOSFET R
DS(on)
Power P-channel/N-channel leakage current
Id = 1 A
Power P-channel R
DS(on)
matching Id = 1 A
Power N-channel R
DS(on)
matching Id = 1 A
Low current deadtime (static) See test circuit
Figure 3
High current deadtime (dynamic)
L = 22 µH, C = 470 nF,
R
L
= 8 Ω , Id = 4.5 A,
see test circuit Figure 4
Turn-on delay time Resistive load
Min.
95
95
Typ.
150
10
Max.
Unit
200
100
20
50
100 m Ω ns ns
μ A
%
% ns
6/26 DocID014268 Rev 5
STA510F Electrical specifications
Symbol t d OFF t r t f
V
CC
Table 6. Electrical specifications (continued)
Parameter
Turn-off delay time
Rise time
Fall time
Supply voltage operating voltage
Conditions
Resistive load
Resistive load, as Figure 4
Resistive load, as Figure 4
Min.
V
IN-High
High level input voltage
10
V
L
/2 +
300 mV
Typ.
V
IN-Low
Low level input voltage
I
IN-H
I
IN-L
I
PWRDN-H
High level input current
Low level input current
V
V
Low
High
Pin voltage = V
L
Pin voltage = 0.3 V
High level PWRDN pin input current V
L
= 3.3 V
Low logical state voltage (pins
PWRDN, TRISTATE) (see
Table 7 )
V
L
= 3.3 V
High logical state voltage (pins
PWRDN, TRISTATE) (see
Table 7 )
V
L
= 3.3 V
I
VCC-
PWRDN
I
I
FAULT
VCC-hiz
I
VCC
Supply current from V
CC
in power down
Output current pins FAULT -TH-
WARN when FAULT CONDITIONS
PWRDN = 0
V
PIN
= 3.3 V
Supply current from V
CC
in tri-state Pin TRI-STATE = 0
Supply current from V
CC both channel switching)
in operation
Input pulse width duty cycle = 50%, switching frequency = 384 kHz, no LC filters;
I t
OUT-SH
V
UV pw_min
Overcurrent protection threshold I
SC
(short-circuit current limit)
Undervoltage protection threshold
Output minimum pulse width No load
1.7
5.5
25
1
1
35
1
22
70
7
7
Max.
Unit
100
25
25
40 ns ns ns
V
V
V
L
/2 –
300 mV
V
μ A
μ A
μ
A
0.8
V
3
9
40
V mA mA mA mA
A
V ns
DocID014268 Rev 5 7/26
26
Electrical specifications
V
L
2.7
3.3
5
Table 7. V low
, V high
threshold variation with V
L
V
Low
max.
V
High
min.
0.7
0.8
0.85
1.5
1.7
1.85
Unit
V
V
V
STA510F
TRI-STATE
0
1
1
1
1
INxA x
0
0
1
1
Table 8. Logic truth table
INxB Q1 Q2 Q3 x
0
1
0
1
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
ON
OFF
OFF
Q4
OFF
ON
OFF
ON
OFF
Output mode
Hi-Z
DUMP
NEGATIVE
POSITIVE
Not used
Duty cycle=A
DTin(A)
INxA
Figure 3. Test circuit for low current deadtime
OUTxY
Vcc
Low current dead time = MAX(DTr,DTf)
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
+Vcc t
Duty cycle = 50%
DTr DTf
M58
R 8
Ω
INxY
OUTxY
M57 gnd
+
-
V67 = vdc = Vcc/2
D03AU1458
Figure 4. Test circuit for high current deadtime
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
M58
M57
DTout(A)
Q1
OUTxA
Iout=4.5A
L67 22
μ
Q3 C69
470nF
Rload=8
Ω
C71 470nF
Q2
DTout(B)
L68 22
μ
Iout=4.5A
OUTxB
C70
470nF
Q4
M64
M63
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
Duty cycle=B
DTin(B)
INxB
D00AU1162
8/26 DocID014268 Rev 5
STA510F
Figure 5. STA311B connections with STA510F
Electrical specifications
DocID014268 Rev 5 9/26
26
Electrical specifications
Figure 6. Typical stereo BTL configuration
STA510F
Figure 7. Typical mono BTL configuration
10/26 DocID014268 Rev 5
STA510F
Figure 8. Typical quad half-bridge configuration
Electrical specifications
DocID014268 Rev 5 11/26
26
Characterization curves STA510F
Figure 9. THD+N vs. P
OUT
36 V 6 Ω BTL time slot 13, 0x03 = BB
*$066*
P P P P P P
:
Figure 10. THD+N vs. P
OUT
36 V 3 Ω SE
*$066*
12/26
P P P P P P
:
DocID014268 Rev 5
STA510F Characterization curves
Figure 11. THD+N vs. P
OUT
36V 3 Ω mono BTL
*$066*
P P P P P P
:
Figure 12. P
OUT
vs. V
CC
6 Ω BTL
*$066*
7+'
7+'
DocID014268 Rev 5 13/26
26
Characterization curves
Figure 13. P
OUT
vs. V
CC
3 Ω SE
STA510F
*$066*
7+'
7+'
Figure 14. P
OUT
vs. V
CC
3 Ω mono BTL
*$066*
7+'
7+'
14/26 DocID014268 Rev 5
STA510F
G
%
U
$
Figure 15. FFT 6 Ω BTL -6dBFs
Characterization curves
*$066*
N N
+]
Figure 16. FFT 6 Ω BTL -60dBFs
N N N
*$066*
G
%
U
$
+]
N N N N N
DocID014268 Rev 5 15/26
26
Characterization curves
Figure 17. FFT 3 Ω SE -6dBFs
STA510F
*$066*
G
%
U
$
+]
N N
Figure 18. FFT 3 Ω SE -60dBFs
N N N
*$066*
G
%
U
$
+]
N N N N N
16/26 DocID014268 Rev 5
STA510F
Figure 19. FFT 3 Ω mono BTL -6dBFs
Characterization curves
*$066*
G
%
U
$
+]
N N
Figure 20. FFT 3 Ω mono BTL -60dBFs
N N N
*$066*
G
%
U
$
+]
N N N N N
DocID014268 Rev 5 17/26
26
Characterization curves
Figure 21. Crosstalk 36 V 6 BTL Ω 1 W
STA510F
*$066*
G
%
+]
N N
Figure 22. Crosstalk 36 V 3 Ω SE 1 W
N N N
*$066*
G
%
+]
N N N N N
18/26 DocID014268 Rev 5
STA510F Output filter
The differential-mode damping of a hybrid filter under no-load conditions is not as good as a pure common-mode filter because most of the high-frequency current flows through the larger capacitor across the speaker terminals. Normally this isn't a problem because the speaker provides the differential-mode damping, but if the amplifier is operated without the speaker connected, for instance when doing testing in production line, then the damping will not be as good.
Care needs to be taken to insure that the damping of a hybrid filter is good enough to protect the amplifier under no-load conditions, thus avoiding peak of voltage that exceed the absolute maximum voltage of the amplifier.
Figure 23. Output filter frequency response with and without load connected to the amplifier
To allow the right filter selection both sets of coefficients are provided.
Perfect when using amplifiers always connected to speakers
Load impedance
3
4
6
8
Table 9. Theoretical table SE
LC Low-pass filter Damping network
LF
15 µH
22 µH
33 µH
47 µH
CF
1 µF
680 nF
470 nF
330 nF
CS
100 nF
100 nF
100 nF
100 nF
CP
100 nF
100 nF
100 nF
100 nF
RP
6.2 Ω
6.2
Ω
6.2 Ω
6.2
Ω
See
Figure 8 .
DocID014268 Rev 5 19/26
26
Output filter STA510F
Load
Impedance
3
4
6
8
See
Figure 6 .
Table 10. Theoretical table BTL
LC Low-Pass Filter Damping network
LF
10 µH
10 µH
15 µH
22 µH
CF
1 µF
1 µF
680 nF
470 nF
CS
220 nF
220 nF
100 nF
100 nF
CP
220 nF
220 nF
100 nF
100 nF
RP
3.3 Ω
3.3
Ω
4.7
Ω
6.2
Ω
Load
Impedance
6
8
3
4
See
Figure 7 .
Table 11. Theoretical table PBTL
LC Low-Pass Filter Damping network
LF
10 µH
10 µH
15 µH
22 µH
CF
1 µF
1 µF
680 nF
470 nF
CS
220 nF
220 nF
100 nF
100 nF
CP
220 nF
220 nF
100 nF
100 nF
RP
2.7
Ω
3.3
Ω
6.2
Ω
6.2 Ω
Suggest to avoid resonant peak when running amplifiers without load
Load impedance
3
4
6
8
Table 12. Filter optimized to minimize the peak SE
LC Low-pass filter Damping network
LF
15 µH
22 µH
33 µH
47 µH
CF
680 µF
470 nF
330 nF
220 nF
CS
100 nF
100 nF
100 nF
100 nF
CP
100 nF
100 nF
100 nF
100 nF
RP
6.2
Ω
6.2 Ω
6.2 Ω
6.2
Ω
See
Figure 8 .
20/26 DocID014268 Rev 5
STA510F Output filter
Load impedance
3
4
6
8
Table 13. Filter optimized to minimize the peak BTL
LC low-pass filter Damping network
LF
10 µH
10 µH
15 µH
22 µH
CF
680 nF
680 nF
470 nF
330 nF
CS
220 nF
220 nF
100 nF
100 nF
CP
220 nF
220 nF
100 nF
100 nF
RP
3.3 Ω
3.3
Ω
4.7
Ω
6.2
Ω
See
Figure 6 .
Load impedance
6
8
3
4
Table 14. Filter optimized to minimize the peak PBTL
LC low-pass filter Damping network
LF
10 µH
10 µH
15 µH
22 µH
CF
680 nF
680 nF
470 nF
330 nF
CS
220 nF
220 nF
100 nF
100 nF
CP
220 nF
220 nF
100 nF
100 nF
RP
2.7
Ω
3.3
Ω
6.2
Ω
6.2 Ω
See
Figure 7 .
DocID014268 Rev 5 21/26
26
Package information STA510F
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 24. PSSO36 (slug up) package outline
POA_7618147_A
22/26 DocID014268 Rev 5
STA510F Package information
Table 15. PSSO36 (slug up) mechanical data mm.
inch.
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
G
G1
H e e3
F
A
A2 a1 b c
D
(1)
E
(1)
2.15
2.15
0
0.18
0.23
10.10
7.4
0.50
8.50
2.3
2.47
2.40
0.075
0.36
0.32
10.50
7.6
0.084
0.084
0
0.007
0.009
0.398
0.291
0.020
0.035
0.090
O
Q
S
T
U h
L
M
N
10.10
0.55
4.3
10° (max.)
1.2
0.8
2.9
3.65
1.0
0.10
0.06
10.50
0.40
0.85
0.398
0.022
0.169
10° (max.)
0.047
0.031
0.114
0.144
0.039
0.004
0.002
0.413
0.016
0.033
X
Y
4.10
6.50
4.70
7.10
0.161
0.256
1.
“D and E” do not include mold flash or protrusion. Mold flash or protrusion shall not exceed 0.15 mm
(0.006”).
0.185
0.279
0.097
0.094
0.003
0.014
0.012
0.413
0.299
DocID014268 Rev 5 23/26
26
Trademarks and other acknowledgments
7 Trademarks and other acknowledgments
FFX is a STMicroelectronics proprietary digital modulation technology.
ECOPACK is a registered trademark of STMicroelectronics.
STA510F
24/26 DocID014268 Rev 5
STA510F Revision history
Date
13-Dec-2007
28-Jun-2011
02-Sep-2011
03-Jun-2014
11-Dec-2018
Revision
Table 16. Document revision history
Changes
1
2
3
4
5
Initial release.
Added part number STA510FTR to Table 1: Device summary
Updated ECOPACK
®
text in Section 6: Package information
Minor textual updates
Updated package to PowerSSO36 throughout datasheet
Corrected typographical error in Features
Updated Figure 1
Updated Figure 2
Updated Figure 21
Added:
– Figure 5 on page 9, Figure 6 on page 10, Figure 7 on page 10 and
Figure 8 on page 11
– Section 4: Characterization curves
– Section 5: Output filter
Updated Table 1: Device summary
DocID014268 Rev 5 25/26
26
STA510F
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26/26 DocID014268 Rev 5
