STA500
30V 3.5A QUAD POWER HALF BRIDGE
■
■
MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
200m Ω R dsON
COMPLEMENTARY DMOS
OUTPUT STAGE
■ CMOS COMPATIBLE LOGIC INPUTS
■
■
THERMAL PROTECTION
THERMAL WARNING OUTPUT
■ OVERVOLTAGE, UNDERVOLTAGE
PROTECTION
MULTIPOWER BCD TECHNOLOGY
PowerSO36
ORDERING NUMBER: STA500
DESCRIPTION
STA500 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability.
The device is particulary designed to make the output stage of a stereo All-Digital High Efficiency (DDX™) amplifier capable to deliver 30 + 30W output power on 8 Ω load and 60W on 8 Ω load in bridge BTL configuration or mono 60W on 4 Ω load. The input pins have threshold proportional to Ibias pin voltage.
AUDIO APPLICATION CIRCUIT (Dual BTL)
+V
CC V
CC
1A
IN1A 29 M3
15
IN1A
C30
1
µ
F
C55
1000
µ
F
17
L18 22 µ H
+3.3V
R57
10K
PWRDN
R59
10K
V L
CONFIG
PWRDN
FAULT
TRI-STATE
23
24
25
27
26
PROTECTIONS
&
LOGIC
M2
M5
16
14
12
OUT1A
OUT1A
GND1A
V
CC
1B
C52
330pF
R63
20
C20
100nF
R98
6
R100
6
C99
100nF
C23
470nF
C101
100nF
8
Ω
C58
100nF 11
C31
1
µ
F
TH_WAR 28 OUT1B
C21
100nF
TH_WAR 10
IN1B 30 OUT1B L19 22
µ
H
IN1B
M4
13 GND1B V
DD
V
DD
21
22
V
CC
SIGN
CC
2A Obsolete Product(s) - Obsolete Product(s)
100nF
C53
100nF
V
SS
V
SS
33
34
REGULATORS
M17
7 V
35
8
C32
1
µ
F
L113 22
µ
H
OUT2A
C110 C60 Obsolete Product(s) - Obsolete Product(s)
IN2A
IN2A
36
31
9
6 GND2A 330pF
100nF
R103
6
C107
100nF
8
Ω
GND-Reg
20 4 V
CC
2B
C108
470nF
R104
GND-Clean
R102
6
C106
19 M16
C33
1
µ
F
20
100nF
3
C111
OUT2B
IN2B 2
100nF
IN2B 32
OUT2B L112 22
µ
H
GNDSUB M14
1 5 GND2B
D00AU1148B
Rev. 7
1/11 January 2006
STA500
PIN FUNCTION
N° Pin
1
35 ; 36
15
GND-SUB Substrate ground
Vcc Sign Signal Positive supply
Vcc1A Positive Supply
OUT1A
OUT1B
OUT2A
OUT2B
IN1A
IN1B
IN2A
IN2B
Vdd
Vcc1B
Vcc2A
Vcc2B
GND1A
GND1B
GND2A
GND2B
16 ; 17
10 ; 11
8 ; 9
2 ; 3
29
30
31
32
21 ; 22
13
6
5
12
7
4
14
Positive Supply
Positive Supply
Positive Supply
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Output half bridge 1A
Output half bridge 1B
Output half bridge 2A
Output half bridge 2B
Input of half bridge 1A
Input of half bridge 1B
Input of half bridge 2A
Input of half bridge 2B
5V Regulator referred to ground
Description
33 ; 34
25
26
27
Vss
PWRDN
5V Regulator referred to +Vcc
Stand-by pin (Control input)
TRI-STATE Hi-Z pin (Control input)
FAULT Fault pin advisor (Open Collector Output)
24 CONFIG Configuration setting pin
28 TH-WAR Thermal warning advisor (Open Collector Output) Obsolete Product(s) - Obsolete Product(s)
19 GND-clean Logical ground
Obsolete Product(s) - Obsolete Product(s)
18 NC Not connected
20 GND-Reg Ground for Vdd regulator
2/11
STA500
FUNCTIONAL PIN STATUS
PIN NAME
FAULT
Logical value
0
IC -STATUS
Fault detected (Short circuit, or
Thermal ..)
Normal Operation
FAULT
(*) 1
TRI-STATE
TRI-STATE
PWRDN
PWRDN
0
1
0
1
All powers in Hi-Z state
Normal operation
Low absorpion
Normal operation
THWAR
THWAR
(*)
CONFIG
0
1
Temperature of the IC =130°C
Normal operation
0 Normal Operation
CONFIG
(**) 1
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**:) To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
OUT1A=OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
PIN CONNECTION
GND-SUB
OUT2B
OUT2B
V
CC
2B
GND2B
1
2
3
4
36
35
34
33
32
31
30
29
V
CC
Sign
V
CC
Sign
V
SS
V
SS
IN2B
GND2A
V
CC
2A
OUT2A
7
8
5
6 IN2A
IN1B
IN1A
OUT2A
OUT1B
9
10
11
28
27
26
TH_WAR
FAULT
TRI-STATE
12 25 V
CC
1B
13 24 GND1B
14
15
23
22
CONFIG Obsolete Product(s) - Obsolete Product(s)
VDD V
CC
1A
OUT1A 16 21 VDD
17 20 OUT1A GND-Reg
18 19 N.C.
GND-Clean
D00AU1133
3/11
STA500
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CE
V max
T op
T stg
, T j
Parameter
DC Supply Voltage (Pin 4,7,12,15)
Maximum Voltage on pins (23 to 32)
Operating Temperature Range
Storage and Junction Temperature
THERMAL DATA
Symbol Parameter
T j-case
T jSD
Thermal Resistance Junction to Case (thermal pad)
Thermal shut-down junction temperature
T warn
Thermal warning temperature t hSD
Thermal shut-down hysteresis
Value
40
5.5
0 to 70
-40 to 150
Min.
Typ.
Max.
2.5
150
130
25
Unit
°C/W
°C
°C
°C
Unit
V
V
°C
°C
ELECTRICAL CHARACTERISTCS
(Ibias = 3.3V; Vcc = 28V; T amb
= 25°C unless otherwise specified)
Symbol Parameter Test conditions
R
I dsON g g dss
N
P
Power Pchannel/Nchannel
MOSFET R dsON
Power Pchannel/Nchannel leakage I dss
Power Pchannel RdsON
Matching
(*)
Power Nchannel RdsON
Matching
(*)
Id=1A;
Vcc=35V
Id=1A
Id=1A
Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 1
Dt_d High current Dead Time (dinamic) L=22
µ
H; C = 470nF; Rl = 8
Ω
Id = 3.5A; see fig. 3
Min.
95
95
Typ.
200
10
Max.
270
50
20
50
Unit m
Ω
µ
A
%
% ns ns t d ON
Turn-on delay time t d OFF
Turn-off delay time t r
Rise time t f
Fall time
Resistive load
Resistive load
Resistive load; as fig. 1
Resistive load; as fig. 1
100
100
25
25 ns ns ns ns
V
CC
V
IN-H
V
OV
Supply voltage operating voltage
High level input voltage
9
Ibias/2
V
+300mV
V
V
IN-L
I
IN-H
V Low level input voltage Ibias/2 Obsolete Product(s) - Obsolete Product(s)
Hi level Input current Pin voltage=Ibias 1
µ
A
µ
A I
IN-L
Low level input current Pin voltage = 0.3V
1
µ
A I
PWRDN-H
Hi level PWRDN pin input current Ibias = 3.3V
35
V
L
Low logical state voltage VL (pin
PWRDN, TRISTATE) (note 1)
Ibias = 3.3V
0.8
V
V
H
High logical state voltage VH (pin
PWRDN, TRISTATE) (note 1)
Ibias = 3.3V
1.7
V
4/11
STA500
ELECTRICAL CHARACTERISTCS (continued)
(Ibias = 3.3V; Vcc = 28V; T amb
= 25°C unless otherwise specified)
Symbol Parameter Test conditions
I
VCC-
PWRDN
PWRDN = 0
I
FAULT
I
VCC-hiz
Supply current from Vcc in Power
Down
Output Current pins
FAULT -TH-WARN when
FAULT CONDITIONS
Supply current from Vcc in Tristate
Vpin = 3.3V
Tri-state=0
I
VCC
I
OUT-SH
V
OV
V
UV t pw_min
Supply current from Vcc in operation
(both channel switching)
Overcurrent Protection Threshold
(short circuit current limit) (note 2)
Overvoltage protection threshold
Undervoltage protection threshold
Output minimum pulse width
Input pulse width = 50% Duty;
Switching Frequency = 384Khz;
No LC filters;
No Load
Min.
Typ.
Max.
3
Unit mA
3.5
30
70
1
22
80
6
35
7
8
40
150 mA mA mA
A
V
V ns
Notes: 1. The following table explains the VL, VH variation with Ibias
Ibias VLmax VHmin Unit
2.7
3.3
5
0.7
0.8
0.85
1.5
1.7
1.85
V
V
V
Note 2: If used in single BTL configuration, the device may be not short circuit protected
LOGIC TRUTH TABLE (see fig. 2)
TRI-STATE
0
INxA
X
INxB
X
Q1
OFF
Q2
OFF
Q3
OFF
Q4
OFF
OUTPUT
MODE
Hi-Z
1
1
0
0
0
1
OFF
OFF
OFF
ON
ON
ON
ON
OFF
DUMP
NEGATIVE
1 1 0 ON OFF OFF ON POSITIVE Obsolete Product(s) - Obsolete Product(s)
1 1 1 ON ON OFF OFF Not used
Obsolete Product(s) - Obsolete Product(s)
5/11
STA500
Figure 1. Test Circuit.
Low current dead time = MAX(DTr,DTf)
Duty cycle = 50%
INxY
M58
M57 gnd
+Vcc
OUTxY
OUTxY t
DTr
R 8 Ω
DTf
+
-
V67 = vdc = Vcc/2
D03AU1458
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
Figure 2.
+V
CC
INxA
Q1
OUTxA
Q2
OUTxB
Q3 Q4
GND
D00AU1134
INxB
Figure 3.
DTin(A)
INxA
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=B
M58
M57
Q1
OUTxA
Iout=3.5A
L67 22
µ
Q3 C69
470nF
C71 470nF
Q2
DTout(B)
OUTxB
L68 22
µ
Iout=3.5A
C70
470nF
Q4
M64
M63
Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure D00AU1162
DTin(B)
INxB
6/11
STA500
Figure 4. Typical Quad Half Bridge Configuration
+3.3V
IN1A
IN1A
IBIAS
CONFIG
PWRDN PWRDN 25
29
23
24
R57
10K
R59
10K
FAULT
C58
100nF
TRI-STATE
TH_WAR
TH_WAR
C58
100nF
IN1B
IN1B
C53
100nF
C60
100nF
V
CC
SIGN
V
CC
SIGN
IN2A
IN2A
GND-Reg
V
DD
V
DD
V
SS
V
SS
GND-Clean
27
26
28
30
21
22
33
34
35
36
31
20
19
PROTECTIONS
&
LOGIC
REGULATORS
IN2B
IN2B
GNDSUB
32
1
M3
M2
M5
M4
M17
M15
M16
M14
V
CC
1P
15
17
16
OUTPL
14
OUTPL
PGND1P
12
11
10
V
CC
1N
C51
1 µ F
OUTNL
13
OUTNL
PGND1N
R41
20
C41
330pF
L11 22 µ H
C71
100nF
R51
6
C61
100nF
R42
20
C42
330pF
L12 22 µ H
C72
100nF
R52
6
7 V
CC
2P
8
9
6
OUTPR
OUTPR
PGND2P
3
2
4 V
CC
2N
C52
1 µ F
OUTNR
5
OUTNR
PGND2N
R43
20
C43
330pF
L13 22
µ
H
C73
100nF
R53
6
C62
100nF
R44
20
C44
330pF
L14 22 µ H
C74
100nF
R54
6
D03AU1474
R61
5K C31 820
µ
F
C81
100nF
R62
5K
C91
1
µ
F
C83
100nF
C84
100nF
R63
5K
C82
100nF
R64
5K
R67
5K
R68
5K
C32 820
µ
C92
1
µ
F
F
R65
5K C33 820
µ
F
R66
5K
C93
1
µ
F
C34 820
C94
1
µ
F
µ
F
+V
CC
C21
2200 µ F
Note:
The diagran showed below, have been obtained using the demonstration board described in the application
Note AN1456 (STA304 + STA500 Digital Audioprocessor evolution board evaluating manual - Jan 2002), refer to the schematic shown in fig. 1).
For the Quad Half Bridge Configuration (fig. 4), refers to the application note AN1661 (STA308 Half Bridge
Board - March 2003)
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
7/11
STA500
Figure 5. Distortion vs Output Power
(STA304A+STA500)
10
5
2
1
0.5
Vcc=30V
Rl=80hm f=1KHz
%
0.2
0.1
0.05
Eq .
0.02
0.01
700m 1 2 3 4 5 6
W
7 8 9 10 20 30 40 50
Figure 7. Output Power vs Supply Voltage
(STA304A+STA500)
50
Pout (W)
45
40
35
20
15
10
5
30
25
STA500
4 ohm load filter 22uH+ 0.47uF diff+
0.1uF common mode
THD = 10%
THD = 1%
0
+12 +12.5
+13 +13.5
+14 +14.5
+15 +15.5
Vdc
Vsupply (V)
+16 +16.5
+17 +17.5
+18
Figure 6. Tolal Power Dissipation & Efficiency vs Output Power
90
80
70
60
50
40
30
20
0
Pdiss
5
Efficiency
10 15
Pout (W)
STA304A+STA500
1channel
Vcc=25V
Rl=8ohm
F=1KHz
20 25
1
30
0
4
3
2
7
6
5
Figure 8. Output Power vs Supply Voltage
(STA304A+STA500)
50
Pout (W)
45
40
35
Rload = 8 ohm f = 1KHz THD = 10%
30
25
20
15
10
THD = 1%
5
+12 +13 +14 +15 +16 +17 +18 +19 +20
Vcc (V)
+21 +22 +23 +24 +25 +26 +27 +28
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
8/11
b c
D
D1
A a1 a2 a3
DIM.
E
E1
E2
E3 e e3 mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
3.60
0.1417
0.10
0.30
0.0039
3.30
0.10
0.0118
0.1299
0.0039
0
0.22
0.23
15.80
9.40
13.90
10.90
0.38
0.0087
0.32
0.0091
16.00 0.6220
9.80
0.3701
14.5
0.5472
11.10 0.4291
0.0150
0.0126
0.6299
0.3858
0.5709
0.4370
5.80
2.90
6.20
0.2283
0.1142
0.2441
0.65
11.05
0.0256
0.4350
h
L
G
H
0
15.50
0.10
15.90 0.6102
1.10
1.10
0.0315
0.0039
0.6260
0.0433
0.0433
0.8
N s
10˚ (max)
8˚ (max)
Note: “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions are "a3", "E" and "G".
OUTLINE AND
MECHANICAL DATA
STA500
PowerSO-36
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
0096119 C
9/11
STA500
Table 1. Revision History
Date Revision
July 2003
January 2006
6
7
Description of Changes
First Issue
Modified in the Electrical Characteristics table (page 4) the values of
V
IN-H
, V
IN-L
, V
L
& V
H
parameters.
Modified the notes 1( page 5).
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
10/11
STA500
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
Obsolete Product(s) - Obsolete Product(s) to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
Obsolete Product(s) - Obsolete Product(s)
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All other names are the property of their respective owners
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11/11
