STA508A
45V 4.5A QUAD POWER HALF BRIDGE
PRODUCT PREVIEW
1 FEATURES
■ MULTIPOWER BCD TECHNOLOGY
■
■
MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
200m
Ω
R dsON
COMPLEMENTARY DMOS
OUTPUT STAGE
■ CMOS COMPATIBLE LOGIC INPUTS
■ THERMAL PROTECTION
■ THERMAL WARNING OUTPUT
■ UNDER VOLTAGE PROTECTION
■ SHORT CIRCUIT PROTECTION
2 DESCRIPTION
STA508 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current
Figure 1. Package
PowerSO36
Table 1. Order Codes
Part Number
STA508A
Package
PowerSO36 capability, and as half bridge (Binary mode) with half current capability.The device is particularly designed to make the output stage of a stereo All-Digital High
Efficiency (DDX™) amplifier capable to deliver 80 +
80W @ THD = 10% at V cc
36V output power on 8
Ω load. In single BTL configuration is also capable to deliver a peak of 160W @THD = 10% at V
CC
= 36V on 4
Ω
load. The input pins have threshold proportional to V
L
pin voltage.
Figure 2. Audio Application Circuit (Dual BTL)
IN1A 29 M3
15
IN1A
C30
1 µ F
C55
1000 µ F
17
L18 22 µ H
V L 23
+3.3V
CONFIG 24 16
OUT1A
PROTECTIONS
&
LOGIC
C52
330pF
C20
100nF
R57
10K
PWRDN
R59
10K
PWRDN
FAULT
TRI-STATE
25
27
26
M2
M5
14
12
OUT1A
GND1A
V
CC
1B
R63
20
R98
6
R100
6
C99
100nF
C23
470nF
C101
100nF
8
Ω
C58
100nF 11
C31
1 µ F
TH_WAR 28 OUT1B
C21
100nF
TH_WAR 10
IN1B
V
SS
30 OUT1B L19 22 µ H
IN1B
V
DD
V
DD
21
22
34
M4
13
7
GND1B
Obsolete Product(s) - Obsolete Product(s)
V
SS
V
CC
2A
C58
100nF
C60
C53
100nF
100nF
IN2A
V
CC
V
CC
SIGN
IN2A
35
36
31
M17
M15
8
9
6
C32
1 µ F
OUT2A
OUT2A
GND2A
L113 22
µ
C109
330pF
6
H
C110
100nF
R103
C107
100nF
8 Ω
GND-Reg
20 4 V
CC
2B
C108
470nF
R104
GND-Clean
R102
C106
19 M16
C33
1 µ F
20
6
100nF
3
C111
OUT2B
IN2B 2
100nF
IN2B 32
OUT2B L112 22
µ
H
GNDSUB M14
V
CC
1A
1 5 GND2B
+V
CC
D00AU1148B
REV. 2
1/10 November 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
STA508A
13
14
15
16 ; 17
18
19
20
21 ; 22
23
24
25
2 ; 3
4
5
6
7
8 ; 9
10 ; 11
12
Table 2. Pin Function
N°
1
Pin
GND-SUB Substrate Ground
OUT2B
V
CC
2B
GND2B
GND2A
V
CC
2A
OUT2A
OUT1B
V
CC
1B
GND1B
GND1A
V
CC
1A
OUT1A
Output Half Bridge 2B
Positive Supply
Negative Supply
Negative Supply
Positive Supply
Output Half Bridge 2A
Output Half Bridge 1B
Positive Supply
Negative Supply
Negative Supply
Positive Supply
Output Half Bridge 1A
NC Not Connected
GND-clean Logical Ground
GND-Reg Ground for Regulator V dd
V dd
5V Regulator Referred to Ground
V
L
High Logical State Setting Voltage
PWRDN Stand-by pin
Description
26
27
28
29
TRI-STATE Hi-Z pin
FAULT Fault pin Advisor
TH-WAR
IN1A
IN1B
Thermal Warning Advisor
Input of Half Bridge 1A
Input of Half Bridge 1B
31
32
IN2A
IN2B
Input of Half Bridge 2A
Input of Half Bridge 2B
33 ; 34 V
SS
5V Regulator Referred to +V
CC
35 ; 36 V
CC
Sign Signal Positive Supply
2/10
STA508A
Table 3. Functional Pin Status
PIN NAME
FAULT
FAULT
(*)
TRI-STATE
TRI-STATE
PWRDN
PWRDN
THWAR
THWAR
(*)
CONFIG
CONFIG
(**)
Logical value
0
1
0
1
0
1
0
1
0
1
IC -STATUS
Fault detected (Short circuit, or Thermal ..)
Normal Operation
All powers in Hi-Z state
Normal operation
Low absorpion
Normal operation
Temperature of the IC =130°C
Normal operation
Normal Operation
OUT1A = OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
Table 4. Pin Connection
V
CC
Sign
V
CC
Sign
V
SS
V
SS
IN2B
IN2A
IN1B
IN1A
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
VL
36
35
34
33
32
31
30
29
28
27
26
25
1
6
7
8
9
10
11
12
2
3
4
5
GND-SUB
OUT2B
OUT2B
V
CC
2B
GND2B
GND2A
V
CC
2A
OUT2A
OUT2A
OUT1B
24
23
22
21
13
14
15
16
OUT1B
V
CC
1B
GND1B
GND1A
V
CC
1A
GND-Reg
GND-Clean
20
19
17
18
OUT1A
N.C.
D01AU1273
Table 5. Thermal Data
Symbol Description
R th j-case
Thermal Resistance Junction-case
Value max 1.5
Unit
°C/W
3/10
STA508A
Table 6. Absolute Maximum Ratings
Symbol
V
CC
V max
P tot
T op
T stg
, T j
Parameter
DC Supply Voltage (Pin 4,7,12,15)
Maximum Voltage on pins 23 to 32
Power Dissipation (T case
= 70°C)
Operating Temperature Range
Storage and Junction Temperature
Value
45
5.5
50
0 to 70
-40 to 150
W
°C
°C
Unit
V
V
Table 7. Electrical Characteristcs (V
L
= 3.3V; V
CC
= 30V; T amb
= 25°C; f sw
= 384KHz; unless othewise specified)
Test conditions Min.
Symbol
R dsON
Parameter
Power Pchannel/Nchannel
MOSFET RdsON
Id=1A
Typ.
200
Max.
270
Unit m
Ω
I dss
Power Pchannel/Nchannel leakage Idss
V
CC
=35V 50
µ
A g
N g
P
Power Pchannel RdsON Matching Id=1A
Power Nchannel RdsON
Matching
Id=1A
Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 4
Dt_d High current Dead Time (dinamic) L=22
µ
H; C = 470nF; R
L
= 8
Ω
Id=3.5A; see fig. 3 t d ON
Turn-on delay time Resistive load t d OFF
Turn-off delay time
Rise time t r t f
V
CC
V
IN-H
Fall time
Supply voltage operating voltage
High level input voltage
Resistive load
Resistive load; as fig.4
Resistive load; as fig. 4
95
95
10
10 20
50
100
100
25
25
40
%
% ns ns ns ns ns ns
V
V V
L
/2
+300mV
V V
IN-L
Low level input voltage V
L
/2 Obsolete Product(s) - Obsolete Product(s)
I
IN-H
I
IN-L
Pin Voltage = V
L
1
µ
A Hi level Input current Obsolete Product(s) - Obsolete Product(s)
Low level input current Pin Voltage = 0.3V
1
µ
A
µ
A I
PWRDN-H
High level PWRDN pin input current
V
L
= 3.3V
35
V
Low
Low logical state voltage VL (pin
PWRDN, TRISTATE) (note 1)
V
L
= 3.3V
0.8
V
4/10
STA508A
Table 7, (continued)
Symbol
V
High
Parameter Test conditions
High logical state voltage VH (pin
PWRDN, TRISTATE) (note 1)
V
L
= 3.3V
I
VCC-
PWRDN
I
FAULT
Supply CURRENT from Vcc in
Power Down
Output Current pins
FAULT -TH-WARN when
FAULT CONDITIONS
PWRDN = 0
Vpin = 3.3V
V
CC
= 30V; Tri-state = 0 I
VCC-hiz
Supply Current from Vcc in Tristate
I
VCC
Supply Current from Vcc in operation both channel switching)
V
CC
=30V;
Input Pulse width = 50% Duty;
Switching Frequency = 384KHz;
No LC filters;
I
VCC-q
Isc (short circuit current limit)
(note 2)
Undervoltage protection threshold V
UV t pw-min
Output minimum pulse width No Load
Min.
4.5
70
Typ.
Max.
1.7
Unit
V
1
22
50
6
7
3
9
150 mA mA mA mA
A
V ns
Table 8.
Notes: 1. The following table explains the VLow, VHigh variation with V
L
V
L
VLmin VHmax Unit
2.7
3.3
5
0.7
0.8
0.85
1.5
1.7
1.85
V
V
V
Note 2: See relevant Application Note AN1994
Table 9. Logic Truth Table (see fig. 5)
TRI-STATE INxA INxB Q1 Q2 Q3 Q4
OUTPUT
MODE
0 x x OFF OFF OFF OFF Hi-Z Obsolete Product(s) - Obsolete Product(s)
1 0 0 OFF OFF ON ON DUMP
Obsolete Product(s) - Obsolete Product(s)
1 1 0 ON OFF OFF ON POSITIVE
1 1 1 ON ON OFF OFF Not used
5/10
STA508A
Figure 3. Test Circuit.
Low current dead time = MAX(DTr,DTf)
Duty cycle = 50%
INxY
M58
M57 gnd
+Vcc
OUTxY
OUTxY t
DTr
R 8
Ω
DTf
+
-
V67 = vdc = Vcc/2
D03AU1458
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
Figure 4.
+V
CC
INxA
Q1
OUTxA
Q2
OUTxB
Q4 Q3
GND
D00AU1134
INxB
Figure 5.
DTin(A)
INA
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=B
M58
M57
Q1
Q3
OUTA
Iout=4.5A
L67 22
µ
C69
470nF
C71 470nF
DTout(B)
L68 22
µ
Iout=4.5A
OUTB
C70
470nF
Q4
M64
M63
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure D03AU1517
DTin(B)
INB
6/10
STA508A
Figure 6. Typical Single BTL Configuration
V
L
+3.3V
23
TH_WAR
10K nPWRDN
IN1A
IN1B
100nF
100nF
X7R
10K
100nF
100nF
X7R
GND-Clean
19
GND-Reg
20
V
DD
V
DD
CONFIG
21
22
24
TH_WAR
28
PWRDN
FAULT
25
27
26
TRI-STATE
IN1A
IN1B
IN2A
IN2B
V
SS
V
SS
33
34
29
30
31
32
V
CC
SIGN
35
100nF
X7R
Add.
V
CC
SIGN
GNDSUB
36
1
18 N.C.
17
16
OUT1A
OUT1A
11
10
OUT1B
OUT1B
OUT2A
OUT2A
9
8
3
2
OUT2B
OUT2B
15
V
CC
1A
12
V
CC
1B
V
CC
2A
7
6
5
4
14
13
V
CC
2B
GND1A
GND1B
GND2A
GND2B
1
µ
F
X7R
10 µ H
22
Ω
1/2W
330pF
10
µ
H
6.2
1/2W
6.2
1/2W
100nF
FILM
100nF
FILM
100nF
X7R
470nF
FILM
100nF
X7R
2200
µ
F
63V
32V
32V
1
µ
F
X7R
4
Ω
D03AU1514
Figure 7. Typical Quad Half Bridge Configuration
+V
CC V
CC
1P
IN1A 29 M3
15
IN1A
GNDSUB
1 5
R61
5K C31 820 µ F
17
R44
20
L11 22 µ H
+3.3V
VL
CONFIG
23
24 16
OUTPL
PWRDN PWRDN
R41
20
C71
100nF
C91
1
µ
F
FAULT
14
OUTPL
PGND1P
C41
330pF
R51
6
R62
5K
R57
10K
R59
10K
27
26
19
PROTECTIONS
&
LOGIC
12
C58
100nF
TRI-STATE
M5
11
C61
100nF
TH_WAR 28
C51
1 µ F
OUTNL
R63
5K
C32 820 µ F
TH_WAR
20
10
IN1B
IN1B 30 OUTNL
21
22
33
34
M4
13
7
PGND1N
V
CC
2P
R42
20
C42
330pF
C72
100nF
R52
6
C82
100nF
R64
5K
C92
1 µ F
4 Ω
V
DD
V
DD
V
SS
V
SS
REGULATORS
V
CC
SIGN
V
CC
SIGN
M17
L13 22
µ
H
C58
100nF
C53
100nF
IN2A
IN2A
35
36
31
M15
8
9
6
OUTPR
OUTPR
PGND2P
R43
20
C73
100nF
C83
100nF
C33 820
Obsolete Product(s) - Obsolete Product(s)
C43
330pF
R53
6
R65
5K
R66
5K
C93
1 µ F
µ
F
4
Ω
4 V
CC
2N
L12 22
µ
H
GND-Clean
V
CC
1N
M16
C52
1
µ
F
OUTNR
C62
100nF 3
2 L14 22
µ
H
C81
100nF
R67
5K C34 820
µ
F
IN2B
IN2B
25
32
M2
4 Ω
OUTNR
C74
100nF M14
PGND2N C94
1
µ
F
4
Ω
C21
2200
µ
F
R54
6
C84
100nF
R68
5K
C44
330pF
D03AU1474
For more information refer to the application notes AN1456 and AN1661
7/10
STA508A
Figure 8. PowerSO36 Mechanical Data & Package Dimensions
L
N s e e3
G
H h c
D
D1
D2
E
DI M.
mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
3.25
3.43
0.128
0.135
A
A2
A4
3.1
0.8
A5 a1 0.030
b 0.22
0.2
3.2
1
-0.040
0.38
0.122
0.031
0.0011
0.008
0.008
0.126
0.039
-0.0015
0.015
0.23
15.8
9.4
0.32
16
9.8
0.009
0.622
0.37
0.012
0.630
0.38
E1
E2
E3
E4
13.9
10.9
5.8
2.9
1
14.5
0.547
11.1
0.429
2.9
6.2
3.2
0.228
0.114
0.039
0.57
0.437
0.114
0.244
1.259
0.65
11.05
0.026
0.435
0
15.5
0.8
0.075
15.9
1.1
0
0.61
1.1
0.031
10˚
8 ˚
0.003
0.625
0.043
0.043
10˚
8˚
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
OUTLINE AND
MECHANICAL DATA
PowerSO36 (SLUG UP)
Obsolete Product(s) - Obsolete Product(s)
7183931 D
8/10
Table 10. Revision History
Date
August 2004
November 2004
Revision
1
2
Description of Changes
First Issue
Changed Vcc from 9 min to 10 min
STA508A
Obsolete Product(s) - Obsolete Product(s)
9/10
STA508A nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted Obsolete Product(s) - Obsolete Product(s) authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
Obsolete Product(s) - Obsolete Product(s)
All other names are the property of their respective owners
DDX is a trademark of Apogee tecnology inc.
© 2004 STMicroelectronics - All rights reserved
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10/10
