RHFLVDS31A
Rad-hard quad LVDS driver
Datasheet
-
production data
• Guaranteed up to 300 krad TID
• SEL immune up to 135 MeV.cm²/mg
• SET/SEU immune up to 67 MeV.cm²/mg
Ceramic Flat-16
The upper metallic lid is electrically connected to ground
Features
• LVDS output
• CMOS input
• Enable/Disable function with high-impedance
• ANSI TIA/EIA-644 compliant
• 400 Mbps (200 MHz)
• Cold spare on all pins
• 3.3 V operating power supply
• 4.8 V absolute rating
• Output voltage: 350 mV on 100-ohm load
• Power consumption: 55 mW at 3.3 V
• Hermetic package
Description
The RHFLVDS31A is a quad, low-voltage, differential signaling (LVDS) driver specifically designed, packaged, and qualified for use in aerospace environments in a low-power and fast point-to-point baseband data transmission standard.
Operating at 3.3 V power supply, the
RHFLVDS31A operates over a controlled impedance of 100-ohm transmission media that may be printed circuit board traces, back planes or cables.
The circuit features an internal fail-safe function to ensure a known state in case of floating input. All pins have cold spare buffers to ensure they are in high impedance when V
CC
is tied to GND.
Designed on ST's proprietary CMOS process with specific mitigation techniques, the RHFLVDS31A achieves “best in the class” for hardness to total ionisation dose and heavy ions.
The RHFLVDS31A can operate over a large temperature range of -55 °C to +125 °C and it is housed in an hermetic Ceramic Flat-16 package.
Reference SMD pin
Table 1. Device summary
Quality level Package
RHFLVDS31AK1 -
Engineering model
RHFLVDS31AK01V 5962F98651 QML-V
1. EPPL = ESA preferred part list
Ceramic
Flat-16
Lead finish
Gold
Mass
0.65 g
EPPL
-
(1)
Target
Temp. range
-55 °C to
125 °C
April 2017
This is information on a product in full production.
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Contents
Contents
RHFLVDS31A
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . 5
Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.1
Ceramic Flat-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Shipping information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15 DocID025370 Rev 4
RHFLVDS31A Functional description
G
4
12
G
1A
1
2A
7
3A
9
4A
15
Figure 1. Logic diagram and logic symbol
G
G
4
12
2
3
1Y
1Z
6
5
2Y
2Z
1A
1
2A
7
EN
10
3Y
11
3Z
14
13
4Y
4Z
CS05830
3A
9
4A
15
2
3
1Y
1Z
6
5
2Y
2Z
10
11
3Y
3Z
14
13
4Y
4Z
CS05860
Input
A
H
L
H
L
X
OPEN
OPEN
G
L
H
X
X
X
H
H
Table 2. Truth table
Enables
G
H
X
L
L
L
X
X
Y
Z
L
L
H
L
H
L
Outputs
Z
Z
H
H
L
H
L
H
Note: 1 The G input features an internal pull-up network. The G input features an internal pull-down network. If they are floating the circuit is enabled.
2 L = low level, H = high Level, X = irrelevant, Z = high impedance (off)
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Pin configuration
Figure 2. Pin connections (top view)
RHFLVDS31A
Pin number
1, 7, 9, 15
2, 6, 10, 14
3, 5, 11, 13
4
12
8
16
Table 3. Pin description
Symbol
1A to 4A
1Y to 4Y
1Z to 4Z
G
G
GND
V
CC
Name and function
Driver inputs
Driver outputs
Enable
Ground
Supply voltage
4/15 DocID025370 Rev 4
RHFLVDS31A
3
Maximum ratings and operating conditions
Maximum ratings and operating conditions
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Symbol
V
CC
V i
V
OUT
T stg
T j
R thjc
ESD
Table 4. Absolute maximum ratings
Parameter Value
Supply voltage
(1)
TTL inputs (operating or cold spare)
LVDS outputs (operating or coldspare)
Storage temperature range
Maximum junction temperature
Thermal resistance junction to case (2)
HBM: Human body model
– All pins except LVDS outputs
– LVDS outputs vs. GND
CDM: Charge device model
4.8
-0.3 to +4.8
-0.3 to +4.8
-65 to +150
+150
22
2
8
500
Unit
V
°C
°C/W kV
V
1. All voltages, except differential I/O bus voltage, are with respect to the network ground terminal.
2. Short-circuits can cause excessive heating. Destructive dissipation can result from short-circuits on the amplifiers.
Symbol
V
CC
V
IN
T
A
Table 5. Operating conditions
Parameter
Supply voltage
Driver DC input voltage (TTL inputs)
Ambient temperature range
Min.
3
0
-55
Typ.
3.3
Max.
3.6
3.6
+125
Unit
V
°C
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Radiation
4 Radiation
RHFLVDS31A
Total dose (MIL-STD-883 TM 1019)
The products guaranteed in radiation within the RHA QML-V system fully comply with the
MIL-STD-883 TM 1019 specification.
The RHFLVDS31A is RHA QML-V, tested and characterized in full compliance with the
MIL-STD-883 specification, between 50 and 300 rad/s only (full CMOS technology).
All parameters provided in Table 7: Electrical characteristics apply to both pre- and post-
irradiation, as follows:
• All test are performed in accordance with MIL-PRF-38535 and test method 1019 of
MIL-STD-883 for total ionizing dose (TID).
• The initial characterization is performed in qualification only on both biased and unbiased parts.
• Each wafer lot is tested at high dose rate only, in the worst bias case condition, based on the results obtained during the initial qualification.
Heavy ions
The behavior of the product when submitted to heavy ions is not tested in production.
Heavy-ion trials are performed on qualification lots only.
TID
Type
Heavy ions
Table 6. Radiation
Characteristics
High-dose rate (50 - 300 rad/sec) up to:
SEL immune up to:
(with a particle angle of 60 ° at 125 °C)
SEL immune up to:
(with a particle angle of 0 ° at 125 °C)
SET/SEU immune up to:
(at 25 °C)
Value
300
135
67
67
Unit krad
MeV.cm²/mg
6/15 DocID025370 Rev 4
RHFLVDS31A Electrical characteristics
In
Table 7
T amb specified
below, V
CC
= 3 V to 3.6 V, capa-load (CL) = 10 pF, typical values are at
= +25 °C, min. and max values are at T amb
= - 55 °C and + 125 °C unless otherwise
I
OS
I
O
V
IH
V
IL
I
IH
Symbol
I
CCL
I
CCZ
I
OFF
(1)
V
OH
V
OL
V
OD1
DV
OD1
V
OS
DV
OS
I
IL
C
IN
Parameter
Table 7. Electrical characteristics
Test conditions
Total enabled supply current, drivers enabled, not switching
Total disabled supply current, loaded or not loaded, drivers disabled
TTL input power-off leakage current
V
IN
Load = 100 Ω on all channels
V
IN
V
= 0 V or V
= 0 V or V
CC
= 0 V, V
IN
CC
CC
G = GND, G = V
CC
= 3.6 V
LVDS output power-off leakage current
V
CC
= 0 V, V
OUT
= 3.6 V
Output voltage high
Output voltage low
Differential output voltage
Change of magnitude of V
OD1 for complementary output states
Offset voltage
R
L
= 100 Ω
Change of magnitude of V
OS complementary output states for
Output short-circuit current
V
IN
V
IN
= 0 V and V
O(Z)
= V
CC and V
= 0 V or
O(Y)
= 0 V
High impedance output current Disabled, V
OUT
= 3.6 V or GND
Input voltage high
G, G, and TTL inputs
Input voltage low
High level input current
Low level input current
G, G, and TTL inputs
V
CC
= 3.6 V, V
IN
= V
CC
G, G and TTL inputs
V
CC
= 3.6 V, V
IN
= 0
Input capacitance
Min.
-10
-50
0.925
250
1.125
-9
-10
2
GND
-10
-10
Typ.
Max.
Unit
16.5
2.8
3
20
4
10
+50
1.65
400
10
1.45
15
10
V
CC
0.8
10
10 mA
µA
V mV
V mV mA
µA
V
µA pF
DocID025370 Rev 4 7/15
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Electrical characteristics RHFLVDS31A
Symbol
Table 7. Electrical characteristics (continued)
Parameter Test conditions Min.
Typ.
Max.
Unit t t t t t t t t t
PHLD
PLHD t t
r
f
SK1
SK2
SKD
PHZ
PLZ
PZH
PZL
Propagation delay time, high to low output
Propagation delay time, low to high output
Refer to Figure 4
Differential output signal rise time
Differential output signal fall time
Channel-to-channel skew
(2)
Chip-to-chip skew
(3)(4)
Differential skew
(5)
(t
PHLD
-t
PLHD
)
Propagation delay time, high level to high impedance output
Propagation delay time, low level to high impedance output
Propagation delay time, high impedance to high level output
Propagation delay time, high impedance to low level output
Load: refer to
Figure 4
0.5
0.5
0.8
0.8
1.5
1.5
0.28
0.7
0.3
2.8
2.8
2.5
2.5
ns ns
1. All pins except pin under test and V
CC
are floating.
2. t
SK1
is the maximum delay time difference between all outputs of the same device (measured with all inputs connected together).
3. t
SK2
is the maximum delay time difference between outputs of all devices when they operate with the same supply voltage, at the same temperature.
4. Guaranteed by design.
5. t
SKD
is the maximum delay time difference between t
PHLD
and t
PLHD
(
see Figure 4
).
Cold sparing
The RHFLVDS31A features a cold spare input and output buffer. In high reliability applications, cold sparing enables a redundant device to be tied to the data bus with its power supply at 0 V (V
CC
= GND) without affecting the bus signals or injecting current from the I/Os to the power supplies. Cold sparing also allows redundant devices to be kept powered off so that they can be switched on only when required. This has no impact on the application. Cold sparing is achieved by implementing a high impedance between the I/Os and V
CC
. ESD protection is ensured through a non-conventional dedicated structure.
Fail-safe
In many applications, inputs need a fail-safe function to avoid an uncertain output state when the inputs are not connected properly. In case of TTL floating inputs, the LVDS outputs remain in a stable logic-high state.
8/15 DocID025370 Rev 4
RHFLVDS31A Test circuit
Figure 3. Voltage and current definition
I I
V IN
LVDS
Driver
(Y) OUT+
V OD
(Z) OUT-
V
V
OZ
V
OY
OS
=(V
OZ
+V
OY
)/2
Figure 4. Test circuit, timing and voltage definitions for differential output signal
LVDS
Driver
CL=10pF
100ohm
CL=10pF
V
IN
Vcc/2 Vcc/2
V
OD t
PHLD
80%
20% tf t
PLHD
20%
80% tr
1. All input pulses are supplied by a generator with the following characteristics: t
Z
O
= 50 Ω , and duty cycle = 50%.
r
or t f
≤ 1 ns, f = 1 MHz,
2. The product is guaranteed in test with CL = 10 pF
DocID025370 Rev 4 9/15
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Test circuit
Figure 5. Enable and disable waveform
LVDS
Driver
OUT+
OUT-
V
OD
CL=10pF
50ohm
50ohm
1.2V
V OS
CL=10pF
RHFLVDS31A
G
G
50%
50%
T
PZH
V
OUT+ or V
OUT-
T
PZL
50%
V
OUT+ or V
OUT-
50%
1. All input pulses are supplied by a generator with the following characteristics: t f
G
or f
G
= 500 kHz, and pulse width G or G = 500 ns.
r
or t f
≤ 1 ns,
2. The product is guaranteed in test with CL = 10 pF
50%
50%
T
PHZ
T
PLZ
50%
50%
10/15 DocID025370 Rev 4
RHFLVDS31A Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID025370 Rev 4 11/15
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Package information RHFLVDS31A
Figure 6. Ceramic Flat-16 package mechanical drawing e b c
L
E3
16 9
E
1 8
E2
E3
L
S1 Q
D A
E
E2
E3 e c
D
A b
L
Q
S1
1. The upper metallic lid is electrically connected to ground.
Table 8. Ceramic Flat-16 package mechanical data
Dimensions
Ref.
Millimeters
Typ.
Min.
2.31
0.38
0.10
9.75
6.75
Max.
2.72
0.48
0.18
10.13
7.06
Min.
0.091
0.015
0.004
0.384
0.266
Inches
Typ.
0.76
6.35
0.66
0.13
4.32
1.27
7.36
1.14
0.030
0.250
0.026
0.005
0.170
0.050
Max.
0.107
0.019
0.007
0.399
0.278
0.290
0.045
12/15 DocID025370 Rev 4
RHFLVDS31A Ordering information
Note:
Order code
Table 9. Order codes
Description Temp. range Package Marking (1) Packing
RHFLVDS31AK1
Engineering model -55 °C to
125 °C
Ceramic
Flat-16
RHFLVDS31AK1
RHFLVDS31AK01V QML-V flight 5962F9865107VZC
1. Specific marking only. Complete marking includes the following:
- SMD pin (on QML-V flight only)
- ST logo
- Date code (date the package was sealed) in YYWWA (year, week, and lot index of week)
- QML logo (Q or V)
- Country of origin (FR = France).
Strip pack
Contact your ST sales office for information regarding the specific conditions for products in die form and QML-Q versions.
Date code
The date code is structured as follows:
• Engineering model: EM xyywwz
• QML flight model: FM yywwz
Where: x = 3 (EM only), assembly location Rennes (France) yy = last two digits of the year ww = week digits z = lot index of the week
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Revision history RHFLVDS31A
Date
29-Oct-2013
30-Oct-2014
04-Mar-2015
28-Apr-2017
Revision
Table 10. Document revision history
Changes
1
2
3
4
Initial release
– Updated production status and marking information relative to order code RHFLVDS31AK01V in Table 1: Device summary and Table 9:
Order codes.
– Changed title of Section 4 to “Radiation” and moved Electrical characteristics to Section 5.
Added V
OUT
to Table 4: Absolute maximum ratings.
Table 1: Device summary : added mass value
14/15 DocID025370 Rev 4
RHFLVDS31A
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