STC5NF20V
N-channel 20V - 0.030
Ω
- 5A - TSSOP8
2.7V-drive STripFET™ II Power MOSFET
Features
Type V
DSS
STC5NF20V 20V
R
DS(on)
< 0.040 Ω (@ 4.5 V)
< 0.045 Ω (@ 2.7 V)
I
D
5A
■
■
Ultra low threshold gate drive (2.7V)
Standard outline for easy automated surface mount assembly
Application
■ Switching applications
Description
This Power MOSFET is the latest development of
STMicroelectronics unique "single feature size" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility.
TSSOP8
Figure 1.
Internal schematic diagram
Table 1.
Device summary
Order code
STC5NF20V
Marking
5N20V
Package
TSSOP8
Packaging
Tape & reel
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October 2007 Rev 6 1/12 www.st.com
12
3
4
5
1
2
Contents
Contents
STC5NF20V
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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STC5NF20V Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(1)
P
TOT
T stg
Drain-source voltage (V
GS
Drain-gate voltage (R
GS
Gate-source voltage
= 0)
= 20K Ω )
Drain current (continuous) at T
Drain current (continuous) at T
Drain current (pulsed)
Total dissipation at T
Storage temperature
C
= 25°C
C
C
= 25°C
=100°C
T
J
Max. Operating junction temperature
1.
Pulse width limited by safe operating area
Table 3.
Thermal data
Symbol Parameter Value
R thJ-PBC
Thermal resistance junction-PBC Max 100
(1)
R thJ-PBC
Thermal resistance junction-PBC Max
1.
When Mounted on FR-4 board with 1 inch
2 pad, 2 oz. of Cu. and t = 10 sec.
2.
When Mounted on minimum recommended footprint
83.5
(2)
Value
20
20
± 12
5
3
20
1.5
–55 to 150
–55 to 150
Unit
A
W
A
A
V
V
V
°C
°C
Unit
°C/W
°C/W
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Electrical characteristics STC5NF20V
(T
CASE
=25°C unless otherwise specified)
Table 4.
Symbol
On/off states
Parameter
V
(BR)DSS
Drain-source breakdown voltage
V
I
I
DSS
GSS
GS(th)
Zero gate voltage drain current (V
GS
= 0)
Gate body leakage current
(V
DS
= 0)
Gate threshold voltage
R
DS(on)
Static drain-source on resistance
Test conditions
I
D
= 250
µ
A, V
GS
= 0
V
DS
= Max rating,
V
DS
= Max rating @125°C
V
GS
= ±12V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 4.5V, I
D
= 2.5A
V
GS
=2.7V, I
D
= 2.5A
Min.
Typ.
Max.
Unit
20
0.6
1
10
±100 nA
0.030
0.037
0.040
0.045
V
µA
µA
V
Ω
Ω
Table 5.
Symbol
Dynamic
Parameter Test conditions g fs
(1)
C
C
C iss oss rss
Forward transconductance
Input capacitance
Output capacitance
Reverse transfer capacitance
V
V
V
DS
GS
DS
= 15 V, I
D
= 2.5A
=15V, f = 1 MHz,
= 0
Q g
Q gs
Q gd
Total gate charge
Gate-source charge
Gate-drain charge
V
V
DD
GS
1.
Pulsed: pulse duration=300µs, duty cycle 1.5%
=10V, I
D
=4.5V
= 4.5A
Min.
Typ.
Max.
Unit
9.5
S
460
200
50 pF pF pF
8.5
1.8
2.4
11.5
nC nC nC
Table 6.
Symbol
Switching times
Parameter Test conditions Min.
Typ.
Max.
Unit
7 ns
V
DD
= 10V, I
D
= 2.5A, t r
Rise time 33 ns
R
G
=4.7
Ω,
V
GS
=4.5V
t d(off) t f
Turn-off delay time 27 ns
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Off-voltage rise time 26 ns t d(off) t f t c
Fall time
Vclamp =16V, I
D
= 5A
R
G
= 4.7
Ω, V
GS
= 4.5V
Figure 16 on page 8
Cross-over time
11
21 ns ns
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STC5NF20V Electrical characteristics
Table 7.
Symbol
I
SD
I
SDM
(1)
V
SD
(2) t rr
Q rr
I
RRM
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1.
Pulse width limited by safe operating area
2.
Pulsed: pulse duration=300µs, duty cycle 1.5%
Test conditions
I
SD
= 5A, V
GS
= 0
I
SD
= 5A, di/dt = 100A/µs,
V
DD
= 10V, T
J
= 150°C
Figure 16 on page 8
Min.
Typ.
Max Unit
5 A
20 A
1.2
V
26
13
1 ns
µC
A
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Electrical characteristics
Figure 2.
Safe operating area Figure 3.
Thermal impedance
STC5NF20V
Figure 4.
Output characteristics Figure 5.
Transfer characteristics
Figure 6.
Transconductance Figure 7.
Static drain-source on resistance
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STC5NF20V Electrical characteristics
Figure 8.
Gate charge vs. gate-source voltage Figure 9.
Capacitance variations
Figure 10. Normalized gate threshold voltage vs. temperature
Figure 11. Normalized on resistance vs. temperature
Figure 12. Source-drain diode forward characteristics
Figure 13.
Thermal resistance and max power
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Test circuit
3 Test circuit
Figure 14. Switching times test circuit for resistive load
Figure 15. Gate charge test circuit
STC5NF20V
Figure 16. Test circuit for inductive load switching and diode recovery times
Figure 17. Unclamped Inductive load test circuit
Figure 18. Unclamped inductive waveform
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STC5NF20V
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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Package mechanical data STC5NF20V
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STC5NF20V Revision history
Table 8.
Date
Document revision history
Revision
09-Sep-2004
03-Aug-2006
01-Feb-2007
25-Oct-2007
3
4
5
6
Changes
Initial electronic version
The document has been reformatted, SOA updated
Typo mistake on Table 2
.
Update marking on Table 1
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STC5NF20V
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