STF8NM50N
N-channel 500 V, 0.73
Ω
, 5 A MDmesh™II Power MOSFET in TO-220FP
Features
Order codes V
DSS
@T
JMAX
STF8NM50N 550 V
R
DS(on) max.
I
D
< 0.79 Ω 5 A
■
■
■
100% avalanche tested
Low input capacitances and gate charge
Low gate input resistance
Applications
■ Switching applications
Description
This device is an N-channel Power MOSFET developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
TO-220FP
1
2
3
Figure 1.
Internal schematic diagram
$
'
3
!-V
Table 1.
Device summary
Order codes
STF8NM50N
Marking
8NM50N
Packages
TO-220FP
Packaging
Tube
November 2011 Doc ID 022505 Rev 2 1/12 www.st.com
12
3
4
5
1
2
Contents
Contents
STF8NM50N
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12 Doc ID 022505 Rev 2
STF8NM50N Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
P
TOT dv/dt
(2)
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink
(t = 1 s; T C = 25 °C)
T stg
T j
Storage temperature
Max. operating junction temperature
1.
Limited by maximum junction temperature.
2.
I
SD
≤
7 A, di/dt
≤
400 A/µs, V
Peak
< V
(BR)DSS
, V
DS
= 80% V
(BR)DSS
Table 3.
Symbol
Thermal data
Parameter
R thj-case
Thermal resistance junction-case max
R thj-amb
Thermal resistance junction-ambient max
T l
Maximum lead temperature for soldering purpose
Table 4.
Symbol
I
AR
E
AS
Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by T j
max)
Single pulse avalanche energy
(starting T j
= 25°C, I
D
= I
AR
, V
DD
= 50 V)
Value
500
± 25
5
(1)
20
15
2500
- 55 to 150
150
Value
6.25
62.5
300
Value
2
140
Unit
A mJ
Unit
°C/W
°C/W
°C
V
°C
°C
Unit
V
V
A
W
V/ns
Doc ID 022505 Rev 2 3/12
Electrical characteristics STF8NM50N
4/12
(T
C
= 25 °C unless otherwise specified)
Table 5.
Symbol
On /off states
Parameter Test conditions
V
(BR)DSS
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Drain-source breakdown voltage
(V
GS
= 0)
Zero gate voltage drain current (V
GS
= 0)
I
D
= 1 mA
V
DS
= 500 V
V
DS
= 500 V, T
C
= 125 °C
Gate-body leakage current (V
DS
= 0)
V
GS
= ± 25 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 250 µA
Static drain-source on resistance
V
GS
= 10 V, I
D
= 2.5 A
Min.
Typ.
Max.
Unit
500
2
V
3
0.73
1
100
µA
µA
±100 nA
4
0.79
V
Ω
Table 6.
Symbol
Dynamic
Parameter Test conditions Min.
Typ.
Max.
Unit
C
C
C iss oss rss
Input capacitance
Output capacitance
Reverse transfer capacitance
C oss(eq)
(1)
Equivalent output capacitance time related
R
G
Intrinsic gate resistance
V
V
V
DS
GS
DS
= 50 V, f = 1 MHz,
= 0
= 0 to 50 V, V
GS f = 1 MHz open drain
= 0
-
-
-
364
33
1.2
147.5
5.4
-
-
pF pF pF pF
Ω
Q g
Q gs
Q gd
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
V
GS
= 400 V, I
= 10 V
(see
Figure 14
D
)
= 5 A,
-
14
3
7
-
1.
Coss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS nC nC nC
Table 7.
Symbol t d(on) t r t d(off) t f
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
V
DD
= 250 V, I
D
= 5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see
Figure 13
)
Min.
Typ.
Max Unit
-
7
4.4
25
8.8
ns ns ns ns
Doc ID 022505 Rev 2
STF8NM50N Electrical characteristics
Table 8.
Symbol
Source drain diode
Parameter Test conditions
I
SD
I
SDM
(1)
V
SD
(2) t rr
Q rr
I
RRM t rr
Q rr
I
RRM
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
I
I
SD
SD
V
DD
SD
= 5 A, V
1.
Pulse width limited by safe operating area.
2.
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
GS
= 0
= 5 A, di/dt = 100 A/µs
= 60 V (see
= 5 A, di/dt = 100 A/µs
V
DD
= 60 V, T j
(see Figure 18
= 150 °C
)
Figure 18
)
Min.
Typ.
Max.
Unit
-
-
5
20
1.5
-
-
187
1.3
14
224
1.5
13 ns
µC
A ns
µC
A
A
A
V
Doc ID 022505 Rev 2 5/12
Electrical characteristics STF8NM50N
Figure 2.
Safe operating area
I
D
(A)
AM07917v1
Figure 3.
Thermal impedance
10
1
0.1
0.01
0.1
a b y m s a re a
i s
D
S
(on) a x R
Oper
Limited
1
10 µs
100 µs
10
Tj=150°C
Tc=25°C
S inlge p u l s e
100 V
D S
(V)
1m s
10m s
Figure 4.
Output characteristics Figure 5.
Transfer characteristics
I
D
(A)
10
V G S =10V
AM07917v1
I
D
(A)
10
V
D S
= 20 V
AM0791 8 v1
7V
8 8
6V
6
4
6
4
5V
2
0
0
2
0
0 10 20 3 0 V
D S
(V) 2 4 6 8 V
G S
(V)
Figure 6.
Static drain-source on resistance Figure 7.
Gate charge vs gate-source voltage
R
D S (on)
(
Ω
)
0.77
0.76
0.75
0.74
0.7
3
0.72
0.71
0.7
0.69
0
V
G S
=10V
1 2 3 4
AM07919v1
5 I
D
(A)
6
4
2
0
0
V
G S
(V)
12
10
V
D S
8
5
V
DD
=400 V
I
D
=5 A
10 15
AM0 3 195v1
100
50
0
Q g
(nC)
400
3 50
3 00
250
200
150
6/12 Doc ID 022505 Rev 2
STF8NM50N Electrical characteristics
Figure 8.
Capacitance variations
C
(pF)
AM07921v1
Figure 9.
Output capacitance stored energy
AM07922v1
E
( µ J)
1000
Ci ss
2
100
Co ss
1
10
Cr ss
1
0 1 10 100 V
D S
(V)
0
0 100 200 3 00 400 500 V
D S
(V)
Figure 10. Normalized gate threshold voltage vs temperature
AM0792 3 v1
V G S (th)
(norm)
I
D
= 250 µ A
Figure 11. Normalized on resistance vs temperature
AM07924v1
R D S (on)
(norm)
2.1
I
D
= 2.5 A
1.00
1.7
0.90
1.
3
0.
8 0
0.70
-50 -25 0 25 50 75 100 T
J
(°C)
Figure 12. Normalized V
DS
vs temperature
AM0902 8 v1
V
D S
(norm)
I
D
=1mA
1.10
1.0
8
1.06
1.04
1.02
1.00
0.9
8
0.96
0.94
0.92
-50 -25 0 25 50 75 100 T
J
(°C)
0.9
0.5
-50 -25 0 25 50 75 100 T
J
(°C)
Doc ID 022505 Rev 2 7/12
Test circuits
3 Test circuits
STF8NM50N
Figure 13.
Switching times test circuit for resistive load
Figure 14.
Gate charge test circuit
V
DD
12V
47k
Ω
100nF
1k Ω
V
G S
V
D
R
G
R
L
D.U.T.
2200
µ
F
3 .
3
µ
F
V
DD
V i
=20V=V
GMAX
2200
µ F
I
G
=CON S T
2.7k
Ω
100
Ω
D.U.T.
V
G
P
W
47k
Ω
P
W
1k
Ω
AM0146 8 v1 AM01469v1
Figure 15.
Test circuit for inductive load switching and diode recovery times
Figure 16.
Unclamped inductive load test circuit
25 Ω
G
A
D
D.U.T.
S
B
R
G
A
FA S T
DIODE
A
B
B
G
D
S
L=100 µ H
3 .
3
µ F
1000
µ F
V
DD
V i
V
D
I
D
L
D.U.T.
2200
µ F
3 .
3
µ F
V
DD
P w
AM01470v1
Figure 17.
Unclamped inductive waveform
V
(BR)D SS
V
D
Figure 18.
Switching time waveform t on t off t r td on td off t f
AM01471v1
I
DM
90 %
90 %
10 %
I
D 0
10 % V
D S
V
DD
V
DD
90 %
V
G S
AM01472v1
0
10 %
AM0147 3 v1
8/12 Doc ID 022505 Rev 2
STF8NM50N
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Doc ID 022505 Rev 2 9/12
Package mechanical data
Table 9.
TO-220FP mechanical data
Dim.
L5
L6
L7
Dia
G1
H
L2
L3
L4
F
F1
F2
G
D
E
A
B
28.6
9.8
2.9
15.9
9
3
Figure 19.
TO-220FP drawing
Min.
0.75
1.15
1.15
4.95
4.4
2.5
2.5
0.45
2.4
10
L7
A
B
Di a
L6 mm
Typ.
16
L5
D
F1 F2
H
L4
10/12
L2
L 3
Doc ID 022505 Rev 2
E
STF8NM50N
F
G1
G
7012510_Rev_K
Max.
1
1.70
1.70
5.2
4.6
2.7
2.75
0.7
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
STF8NM50N Revision history
Table 10.
Document revision history
Date Revision
17-Nov-2011
18-Nov-2011
1
2
Changes
First release.
Updated dv/dt in
Table 2: Absolute maximum ratings
.
Doc ID 022505 Rev 2 11/12
STF8NM50N
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