STF5N60M2
Nchannel 600 V, 1.3 Ω typ., 3.5 A MDmesh™ M2
Power MOSFET in a TO-220FP package
Datasheet - production data
Features
Order code V
DS
@ T
Jmax
R
DS(on)
max. I
D
STF5N60M2 650 V 1.4 Ω 3.5 A
Extremely low gate charge
Excellent output capacitance (C
OSS
) profile
100% avalanche tested
Zener-protected
TO-220FP
Applications
Switching applications
Figure 1: Internal schematic diagram
Order code
STF5N60M2
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters.
Table 1: Device summary
Marking Package
5N60M2 TO-220FP
Packing
Tube
June 2016 DocID025320 Rev 2
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STF5N60M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
TO-220FP package information ...................................................... 10
5 Revision history ............................................................................ 12
2/13 DocID025320 Rev 2
STF5N60M2
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
I
D
(1)
Drain current (continuous) at T
C
= 100 °C
I
DM
(2)
Drain current (pulsed)
P
TOT
Total dissipation at T
C
= 25 °C
V
ISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; T
C
= 25 °C)
dv/dt (3)
Peak diode recovery voltage slope
dv/dt (4)
MOSFET dv/dt ruggedness
T stg
T j
Storage temperature range
Operating junction temperature range
Notes:
(1)
Limited by package.
(2)
Pulse width limited by safe operating area.
(3)
I
SD
≤ 3.5 A, di/dt ≤ 400 A/μs; V
DS
peak < V
(BR)DSS
, V
DD
= 400 V.
(4)
V
DS
≤ 480 V.
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case max.
Thermal resistance junction-ambient max.
Symbol
I
E
AR
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive
(pulse width limited by T jmax
)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
; V
DD
= 50 V)
Electrical ratings
Value
±25
3.5
2.2
14
20
2500
15
50
-55 to 150
Unit
V
A
A
W
V
V/ns
°C
Value
6.25
62.5
Value
0.5
80
Unit
°C/W
°C/W
Unit
A mJ
DocID025320 Rev 2 3/13
Electrical characteristics
2
4/13
STF5N60M2
Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On /off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 600 V
V
GS
= 0 V, V
DS
= 600 V,
T
C
= 125 °C (1)
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source on-resistance
V
DS
= 0 V, V
GS
= ±25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 1.7 A
Min. Typ. Max. Unit
600 V
1
100
µA
3
1.3
±10
μA
4 V
1.4 Ω
2
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C
oss eq.
(1)
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
V
V
DS
GS
= 100 V, f = 1 MHz,
= 0 V
Equivalent output capacitance
V
DS
= 0 to 480 V, V
GS
Intrinsic gate resistance f = 1 MHz open drain
= 0 V
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 480 V, I
D
= 3.5 A,
V
GS
= 10 V
(see Figure 15: "Test circuit for gate charge behavior" )
-
-
-
-
Min. Typ. Max. Unit
-
-
211
13
-
- pF
- 0.75 -
- 19.5
6.2
8
1.6
4.4
-
-
-
-
- pF
Ω nC
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
.
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
DD
= 300 V, I
D
= 1.7 A R
G
= 4.7
Ω,
V
GS
= 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19:
"Switching time waveform" )
-
-
-
-
12
3
70
15
-
-
-
- ns
DocID025320 Rev 2
STF5N60M2
Symbol Parameter
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Table 8: Source-drain diode
Test conditions
I
I
V
V
GS
SD
DD
= 0 V, I
SD
= 3.5 A
circuit for inductive load switching and diode recovery times"
SD
V
= 3.5 A, di/dt = 100 A/µs,
= 60 V (see Figure 16: "Test
= 3.5 A, di/dt = 100 A/µs,
DD
= 60 V, T j
= 150 °C (see
Figure 16: "Test circuit for inductive load switching and diode recovery times" )
)
Electrical characteristics
Min. Typ. Max. Unit
- 3.5 A
- 14 A
-
- 220
1.6 V ns
- 1.05 µC
-
-
-
-
9.5
314
1.5
9.5
A ns
µC
A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5 %.
DocID025320 Rev 2 5/13
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STF5N60M2
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/13 DocID025320 Rev 2
STF5N60M2
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Output capacitance stored energy
Figure 10: Normalized gate threshold voltage vs temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Normalized V
(BR)DSS
vs temperature
Figure 13: Source- drain diode forward characteristics
DocID025320 Rev 2 7/13
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STF5N60M2
Figure 15: Test circuit for gate charge behavior
8/13
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
DocID025320 Rev 2
STF5N60M2
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID025320 Rev 2 9/13
Package information
4.1 TO-220FP package information
Figure 20: TO-220FP package outline
STF5N60M2
10/13 DocID025320 Rev 2
STF5N60M2
Dim.
G1
H
L2
L3
L4
L5
L6
L7
Dia
F
F1
F2
G
A
B
D
E
Table 9: TO-220FP package mechanical data mm
Min. Typ.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
28.6
9.8
2.9
15.9
9
3
Package information
Max.
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
DocID025320 Rev 2 11/13
Revision history
5
STF5N60M2
Revision history
Date Revision
Table 10: Document revision history
Changes
30-Sep-2013
15-Jun-2016
1
2
First release.
Updated title, features and description in cover page.
Updated Section 1: "Electrical ratings"
and Section 2: "Electrical characteristics" .
Added Section 2.1: "Electrical characteristics (curves)" .
Minor text changes.
12/13 DocID025320 Rev 2
STF5N60M2
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