STMicroelectronics STFI20NM65N Datasheet
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STFI20NM65N
*
1
2
3
'
N-channel 650 V, 15 A, 0.250
Ω
typ., MDmesh™ II
Power MOSFET in a I²PAKFP package
Datasheet
-
production data
Figure 1. Internal schematic diagram
Features
Order code V
DSS
@T jmax
STFI20NM65N 710 V
R
DS(on)
max.
0.270
Ω
•
•
•
100% avalanche tested
Low input capacitance and gate charge
Low gate input resistance
I
D
15 A
•
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
6
$0Y
Order code
STFI20NM65N
Table 1. Device summary
Marking Packages
20NM65N I
2
PAKFP (TO-281)
Packaging
Tube
December 2013
This is information on a product in full production.
DocID025737 Rev 1 1/12 www.st.com
Contents
Contents
STFI20NM65N
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2/12 DocID025737 Rev 1
STFI20NM65N Electrical ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
V
DS
V
GS
I
D
I
D
I
DM
(2)
P
TOT dv/dt
(3)
Drain source voltage
Gate source voltage
Drain current continuous T
C
=25 °C
Drain current continuous T
C
=100 °C
Drain current pulsed
Total dissipation at T
C
=25 °C
Peak diode recovery voltage slope
V
ISO
T stg
T
J
Insulation withstand voltage (RMS) from all three leads to external heatsink
(t=1 s; T
C
= 25 °C)
Storage temperature
Max. operating junction temperature
1.
Limited only by maximum temperature allowed.
2.
Pulse width limited by safe operating area.
3.
I
SD
≤
15 A, di/dt
≤
400 A/ μ s, V
DS peak
≤
V
(BR)DSS
, V
DD
= 80% V
(BR)DSS
.
Value
2500
-55 to 150
150
650
± 25
15
(1)
9.45
60
30
15
Unit
V
V
A
A
A
W
V/ns
V
°C
Symbol
R thjc
R thja
Table 3. Thermal data
Parameters
Thermal resistance junction-case max.
Thermal resistance junction-ambient max.
Value
4.17
62.5
Unit
°C/W
°C/W
Symbol
I
AS
E
AS
Table 4. Avalanche characteristics
Parameters
Avalanche current, repetitive or not-repetitive (pulse width limited by T j max
)
Single pulse avalanche energy (starting T
J
= 25 °C,
I
D
= I
AR
, V
DD
= 50 V)
Value
4
115
Unit
A mJ
DocID025737 Rev 1 3/12
12
Electrical characteristics STFI20NM65N
4/12
(T
C
= 25 °C unless otherwise specified).
Symbol Parameter
Table 5. On/off states
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
I
D
= 1 mA, V
GS
= 0 l
DSS
Zero gate voltage drain current (V
GS
=0)
V
DS
= 650 V
V
DS
= 650 V, T
C
=0 l
GSS
Gate body leakage
(V
DS
=0)
V
GS
= ±25 V, V
DS
=0
V
GS(th)
Gate threshold voltage
I
D
= 250 μ A,
V
GS =
V
DS
R
DS(on)
Static drain-source on- resistance
I
D
=7.5 A, V
GS
=10 V
Min.
Typ.
Max.
Unit
650
1
100
V
μ A
μ A
100 nA
2 3 4 V
0.250
0.270
Ω
Symbol Parameter
Table 6. Dynamic
Test conditions Min.
Typ.
Max.
Unit
C iss
C oss
Input capacitance
Output capacitance
C rss
Reverse capacitance
C oss eq
(1)
Equivalent output capacitance
V
V
DS
DS
= 50 V, f = 1MHz, V
= 0 to V
GS
= 0
GS
= 0
-
-
-
1280
110
10
260 -
-
-
pF pF pF pF
R
G
Q g
Q gs
Q gd
Intrinsic gate resistance f = 1MHz, I
D
=0
Total gate charge
Gate source charge
Gate-drain charge
V
DD
= 520 V, I
D
= 15 A,
V
GS
= 10 V
-
-
-
4.8
44
8
22 -
-
-
-
1.
C oss eq
: defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80 % V
DSS
.
Ω nC nC nC
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Table 7. Switching times
Test conditions
V
DD
= 325 V, I
D
=7.5 A
R g
=4.7
Ω,
V
GS
=10 V
(see
(see
Min.
Typ.
Max.
Unit
-
-
-
-
15
13.5
75
21
-
-
-
ns ns ns ns
DocID025737 Rev 1
STFI20NM65N Electrical characteristics
Symbol Parameter
Table 8. Source drain diode
Test conditions
I
SD
Source drain current
I
SDM
(1)
Source drain current
(pulsed)
V
SD
(2) t rr
Forward on voltage
Q rr
I
SD
= 15 A, V
GS
= 0
Reverse recovery time
Reverse recovery charge
I
SD
= 15 A, di/dt = 100 A/ μ s
V
DD
Reverse recovery current I
RRM t rr
I
Q rr
RRM
Reverse recovery time
Reverse recovery charge
I
SD
=15 A, di/dt = 100 A/ μ s
V
DD
= 60 V, Tj = 150 °C
)
Reverse recovery current
1.
Pulse width limited by safe operating area.
2.
Pulsed: pulse duration = 300 μ s, duty cycle 1.5 %.
Min.
Typ.
Max.
Unit
15 A
-
-
-
-
-
-
-
-
455
5.5
24.5
710
8
24
60
1.6
A
V ns
μ C
A ns
μ C
A
DocID025737 Rev 1 5/12
12
Electrical characteristics STFI20NM65N
2.1
I
D
(A)
Electrical characteristics (curves)
Figure 2. Safe operating area Figure 3. Thermal impedance
AM09139v1
10
1
Oper
Limited b
DS(on)
Tj=150°C
Tc=25°C
Single pulse
10µs
100µs
1ms
10ms
0.1
0.1
1 10 100 V
DS
(V)
15
10
5
0
0
Figure 4. Output characteristics
AM09140v1
I
D
(A)
35
V
GS
=10V
30
6V
25
20
5 10 15
5V
20
4V
V
DS
(V)
10
5
0
0
30
25
20
15
Figure 5. Transfer characteristics
AM09141v1
I
D
(A)
35
V
DS
=19V
2 4 6 8 10 V
GS
(V)
Figure 6. Normalized V
(BR)DSS
vs temperature
AM09028v1
V
(BR)DSS
(norm)
I
D
=1mA
1.10
Figure 7. Static drain-source on-resistance
R
DS(on)
(
Ω
)
V
GS
=10V
AM09143v1
0.260
1.08
1.06
0.255
1.04
1.02
1.00
0.250
0.245
0.98
0.96
0.240
0.94
0.92
-50 -25 0 25 50 75 100 T
J
(°C)
0.235
0 2 4 6 8 10 12 14 I
D
(A)
6/12 DocID025737 Rev 1
STFI20NM65N Electrical characteristics
Figure 8. Gate charge vs gate-source voltage
V
GS
(V)
12
V
DS
V
DD
=520V
I
D
=15A
AM09144v1
V
DS
(V)
500
10
400
8
300
6
200
4
2
100
0
0 10 20 30 40 50
0
Q g
(nC)
Figure 10. Normalized gate threshold voltage vs temperature
AM09146v1
V
GS(th)
(norm)
1.10
1.00
0.90
0.80
I
D
=250µA
0.70
-50 -25 0 25 50 75 100 T
J
(°C)
Figure 12. Source-drain diode forward characteristics
AM09148v1
V
SD
(V)
1.6
T
J
=-50°C
1.4
T
J
=25°C
1.2
1.0
T
J
=150°C
0.8
0.6
0.4
0.2
0 2 4 6 8 10 12 14 16 I
SD
(A)
Figure 9. Capacitance variations
C
(pF)
1000
100
10
AM09145v1
Ciss
Coss
Crss
1
0.1
1 10 100 V
DS
(V)
Figure 11. Normalized on-resistance vs temperature
AM09147v1
R
DS(on)
(norm)
2.1
1.9
I
D
=7.5A
V
GS
=10V
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-50 -25 0 25 50 75 100 T
J
(°C)
DocID025737 Rev 1 7/12
12
Test circuits
3 Test circuits
STFI20NM65N
Figure 13. Switching times test circuit for resistive load
Figure 14. Gate charge test circuit
V
DD
12V
47k
Ω
100nF
1k Ω
V
GS
V
D
R
G
R
L
D.U.T.
2200
μ
F
3.3
μ
F
V
DD
V i
=20V=V
GMAX
2200
μ F
I
G
=CONST
2.7k
Ω
100 Ω
D.U.T.
V
G
P
W
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
47k
Ω
P
W
1k
Ω
AM01469v1
Figure 16. Unclamped inductive load test circuit
25 Ω
G
D
A
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
G
D
S
L=100 μ H
3.3
μ F
1000
μ F
V
DD
V i
AM01470v1
Figure 17. Unclamped inductive waveform
V
(BR)DSS
V
D
V
D
I
D
L
2200
μ F
3.3
μ F
V
DD
D.U.T.
P w
AM01471v1
Figure 18. Switching time waveform t on td on t r t off td off t f
I
DM
90%
90%
10%
I
D 0
10% V
DS
V
DD
V
DD
90%
V
GS
AM01472v1
0
10%
AM01473v1
8/12 DocID025737 Rev 1
STFI20NM65N
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
DocID025737 Rev 1 9/12
12
Package mechanical data
Figure 19. I
2
PAKFP (TO-281) drawing
STFI20NM65N
10/12
Dim.
L4
L5
L6
H
L1
L2
L3
E
F
F1
G
A
B
D
D1
ĆUHY$
4.95
10.00
21.00
13.20
10.55
2.70
0.85
7.30
Table 9. I
2
PAKFP (TO-281) mechanical data mm
Min.
Typ.
4.40
2.50
2.50
0.65
0.45
0.75
-
Max.
10.40
23.00
14.10
10.85
3.20
1.25
7.50
4.60
2.70
2.75
0.85
0.70
1.00
1.20
5.20
DocID025737 Rev 1
STFI20NM65N
Date
20-Dec-2013
Table 10. Revision history
Revision
1 Initial release.
Changes
Revision history
DocID025737 Rev 1 11/12
12
STFI20NM65N
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