STL11NH3LL
N-channel 30 V, 0.0078
Ω
, 11 A, PowerFLAT™ (3.3 x 3.3) ultra low gate charge STripFET™ Power MOSFET
Features
Type
STL11NH3LL
V
DSS
30 V
R
DS(on) max
I
D
< 0.0092
Ω
11 A
(1)
1.
The value is rated according Rthj-pcb
■
■
■
■
■
■
Improved die-to-footprint ratio
Very low profile package (1mm max)
Very low thermal resistance
Very low gate charge
Low threshold device
In compliance with the 2002/95/EC European directive
Application
■ Switching applications
Description
This application specific Power MOSFET is the latest generation of STMicroelectronics unique
“STripFET™” technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The chip-scaled PowerFLAT™ package allows a significant board space saving, still boosting the performance.
PowerFLAT™(3.3x3.3)
(Chip scale package)
Figure 1.
Internal schematic diagram
Table 1.
Device summary
Order code Marking Package
PowerFLAT™ (3.3 x 3.3)
Packaging
Obsolete Product(s) - Obsolete Product(s)
November 2008 Rev 2 1/13 www.st.com
13
3
4
5
1
2
Contents
Contents
STL11NH3LL
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/13
STL11NH3LL Electrical ratings
Table 2.
Absolute maximum ratings
Symbol Parameter
V
DS
V
GS
I
D
(1)
I
D
(1)
I
DM
(2)
P
TOT
(3)
P
TOT
(1)
Drain-source voltage (V
Gate-source voltage
GS
= 0)
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Total dissipation at T
C
= 25 °C
Derating factor
T
J
T stg
Operating junction temperature storage temperature
1.
The value is rated according Rthj-pcb
2.
Pulse width limited by safe operating area.
3.
The value is rated according Rthj-c
= 25 °C
=100 °C
Table 3.
Thermal resistance
Symbol Parameter
R thj-case
R thj-pcb
(1)
R thj-pcb
(2)
Thermal resistance junction-case (drain)
Thermal resistance junction-pcb
Thermal resistance junction-pcb
1.
When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec
2.
Steady state
Table 4.
Avalanche data
Symbol
I
AV
E
AS
Parameter
Not-repetitive avalanche current
(pulse width limited by Tj Max)
Single pulse avalanche energy
D
=I
AV
, V
DD
= 20 V, L=6 mH)
Value
30
± 16
11
6.9
44
50
2
0.4
-55 to 150
Unit
V
V
A
W
W
A
A
W/°C
°C
Value
2.5
42.8
63.5
Unit
°C/W
°C/W
°C/W
Value
9
150
Unit
A mJ
3/13
Electrical characteristics STL11NH3LL
(T
CASE
=25°C unless otherwise specified)
Table 5.
On/off states
Symbol Parameter Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
R
I
I
DSS
GSS
GS(th)
DS(on)
I
D
= 250 µA, V
GS
= 0
Zero gate voltage drain current (V
GS
= 0)
Gate body leakage current
(V
DS
= 0)
Gate threshold voltage
Static drain-source on resistance
V
V
DS
DS
= Max rating,
= Max rating
V
GS
= ±16 V
@125 °C
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 5.5 A
V
GS
= 4.5 V, I
D
= 5.5 A
Min.
Typ.
Max.
Unit
30
1
1
10
±
100
2.5
0.0078
0.009
0.0092
0.0115
V
µA
µA nA
V
Ω
Ω
Table 6.
Dynamic
Symbol Parameter
C iss
C oss
C rss
Input capacitance
Output capacitance
Reverse transfer capacitance
Q g
Q gs
Q gd
Total gate charge
Gate-source charge
Gate-drain charge
R
G
Gate input resistance
V
V
DS
GS
Test conditions
=25 V, f=1 MHz,
=0
V
DD
=15 V, I
D
= 11 A
V
GS
=4.5 V
(see Figure 16)
f=1 MHz Gate DC Bias = 0
Test signal level = 20mV
Open drain
0.8
Min.
Typ.
Max.
Unit
965
285
38 pF pF pF
9
3.7
3
1.5
12
2.5
nC nC nC
Ω
4/13
STL11NH3LL Electrical characteristics
Table 7.
Switching times
Symbol Parameter t d(on) t r t d(off) t f
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
V
DD
=15 V, I
D
= 5.5 A,
R
G
=4.7
Ω,
V
GS
=4.5 V
(see Figure 15)
Min.
Typ.
Max.
Unit
15
32
18
8.5
ns ns ns ns
Table 8.
Source drain diode
Symbol Parameter
I
SD
I
SDM
(1)
V
SD
(2)
Source-drain current
Source-drain current (pulsed)
Forward on voltage t rr
Q rr
I
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
1.
Pulse width limited by safe operating area
2.
Pulsed: pulse duration=300µs, duty cycle 1.5%
Test conditions
I
SD
=11 A, V
GS
=0
I
SD
=11 A, di/dt = 100 A/µs,
V
DD
=20 V, Tj=150 °C
(see Figure 20)
Min Typ.
Max Unit
11
44
A
A
1.3
V
24
17.4
1.45
ns nC
A
5/13
Electrical characteristics
Figure 2.
Safe operating area Figure 3.
Thermal impedance
STL11NH3LL
Figure 4.
Output characteristics Figure 5.
Transfer characteristics
Figure 6.
Normalized B
VDSS
vs temperature Figure 7.
Static drain-source on resistance
6/13
STL11NH3LL Electrical characteristics
Figure 8.
Gate charge vs gate-source voltage Figure 9.
Capacitance variations
Figure 10. Normalized gate threshold voltage vs temperature
Figure 11. Normalized on resistance vs temperature
Figure 12. Source-drain diode forward characteristics
Figure 13. Avalanche energy vs starting t j
7/13
Electrical characteristics
Figure 14. Allowable I av
vs time in avalanche
STL11NH3LL
The previous curve gives the single pulse safe operating area for unclamped inductive loads, under the following conditions:
P
D(AVE)
=0.5*(1.3*B
VDSS
*I
AV
)
E
AS(AR)
=P
D(AVE)
*t
AV
Where:
I
AV
is the allowable current in avalanche
P
D(AVE) is the average power dissipation in avalanche (single pulse) t
AV
is the time in avalanche
8/13
STL11NH3LL
3 Test circuit
Figure 15. Switching times test circuit for resistive load
Figure 16. Gate charge test circuit
Test circuit
Figure 17. Test circuit for inductive load switching and diode recovery times
Figure 18. Unclamped inductive load test circuit
Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform
9/13
Package mechanical data
4 Package mechanical data
STL11NH3LL
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
10/13
STL11NH3LL Package mechanical data
Dim
D2
E
E2 e
A
A 3 b
D
L
L1
Min
0.
9 50
0.2
9
3 .200
2.24
2.20
1.660
0.45
PowerFLAT™ ( 3.3 x 3.3) mechanical data mm
Typ
0.200
0.
3 4
3 .
3 00
2.2
9
3 .
3 0
1.710
0.650
0.40
0.50
Max
1.000
0.
39
3 .400
2.
3 4
3 .40
1.760
0.55
Min
0.0
3 7
0.011
0.126
0.0
88
0.0
8 6
0.065
0.017
inch
Typ
0.00
8
0.01
3
0.12
3
0.0
9 0
0.12
3
0.067
0.025
0.0157
0.01
9 6
Max
0.0
39
0.015
0.1
3 4
0.0
9 2
0.1
338
0.06
9
0.021
11/13
Revision history STL11NH3LL
Table 9.
Date
11-Oct-2006
04-Nov-2008
Document revision history
Revision
1
2
Changes
First release
Document status promoted from preliminary data to datasheet.
12/13
STL11NH3LL
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