STL20DNF06LAG
Automotive-grade dual N-channel 60 V, 27 mΩ typ., 20 A STripFET™ II
Power MOSFET in a PowerFLAT™ 5x6 double island package
Datasheet - production data
Features
Order code V
DS
R
DS(on)
max. I
D
P
TOT
STL20DNF06LAG 60 V 40 mΩ 20 A 75 W
Designed for Automotive applications and
AEC-Q101 qualified
PowerFLAT™ 5x6 double island with
wettable flanks
Logic level V
GS(th)
Maximum junction temperature: T
J
= 175 °C
Figure 1: Internal schematic diagram Applications
Switching applications
Description
This Power MOSFET series realized with
STMicroelectronics unique STripFET™ process is specifically designed to minimize input capacitance and gate charge. It is therefore ideal as a primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and
Computer applications. It is also suitable for any application with low gate charge drive requirements.
Order code
STL20DNF06LAG
Marking
20DNF06L
Table 1: Device summary
Package
PowerFLAT™ 5x6 double island
Packing
Tape and reel
September 2015 DocID028242 Rev 1
This is information on a product in full production.
1/15 www.st.com
Contents
Contents
STL20DNF06LAG
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
4.2
PowerFLAT™ 5x6 double island WF type R package information .... 9
PowerFLAT™ 5x6 WF packing information .................................... 12
5 Revision history ............................................................................ 14
2/15 DocID028242 Rev 1
STL20DNF06LAG
1 Electrical ratings
Symbol
V
DS
V
GS
I
D
(1)(2)
I
DM
(1)(3)
I
D
(4)
I
DM
P
TOT
P
TOT
T stg
T j
Table 2: Absolute maximum ratings
Parameter
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed)
Drain current (continuous) at T pcb
= 25 °C
Drain current (continuous) at T pcb
= 100 °C
Drain current (pulsed)
Total dissipation at T case
= 25 °C
Total dissipation at T pcb
= 25 °C
Storage temperature
Operating junction temperature
Notes:
(1)
This value is rated according to R thj-c
.
(2)
Current limited by package.
(3)
Pulse width is limited by safe operating area.
(4)
This value is rated according to R thj-pcb
.
Symbol
Table 3: Thermal data
Parameter
R thj-case
R
thj-pcb
(1)
Thermal resistance junction-case
Thermal resistance junction-pcb
Notes:
(1)
When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s.
Symbol
Table 4: Avalanche characteristics
Parameter
I
AV
E
AS
(1)
Avalanche current, not repetitive
Single pulse avalanche energy
Notes:
(1)
starting T j
= 25 °C, I
D
= I
AV
, per channel.
Electrical ratings
Value
7.4
5.2
29.6
75
4.8
60
±20
20
20
80
-55 to 175
A
A
W
Unit
V
V
A
A
°C
Value
2.0
31.3
Value
7.4
210
Unit
°C/W
Unit
A mJ
DocID028242 Rev 1 3/15
Electrical characteristics
2 Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: Static
Test conditions
V
(BR)DSS
I
DSS
Drain-source breakdown voltage
I
GSS
V
GS(th)
Gate threshold voltage
V
GS
= 0 V, I
D
= 250 µA
V
GS
= 0 V, V
DS
= 60 V
Zero gate voltage drain current
V
GS
= 0 V, V
DS
= 60 V,
T
C
= 125 °C
Gate-body leakage current V
DS
= 0 V, V
GS
= ±20 V
R
DS(on)
Static drain-source onresistance
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 4 A
V
GS
= 5 V, I
D
= 4 A
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
V
DD
= 25 V, I
D
= 7.4 A,
V
GS
= 10 V (see Figure 15:
"Gate charge test circuit" )
Symbol Parameter t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
Table 7: Switching times
Test conditions
V
DD
= 30 V, I
D
= 3.7 A
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 14: "Switching times test circuit for resistive load" and Figure
19: "Switching time waveform" )
STL20DNF06LAG
Min. Typ. Max. Unit
60
1
1
V
µA
27
32
100 µA
±100 nA
2.5
40
50
V mΩ
Min. Typ. Max. Unit
-
-
-
-
-
-
670
170
56
22.5
2.5
7
-
-
-
-
-
- pF nC
Min. Typ. Max. Unit
-
-
-
7
15.4
36.8
-
-
- ns
- 7.7 -
4/15 DocID028242 Rev 1
STL20DNF06LAG
Symbol
I
SD
Source-drain current
I
SDM
(1)
Source-drain current (pulsed)
V
SD
(2)
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
RRM
Parameter
Table 8: Source-drain diode
Test conditions
Reverse recovery current
I
V
GS
SD
= 0 V, I
= 7.4 A,
SD
= 7.4 A di/dt = 100 A/µs, V
DD
= 48 V
(see Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
-
28
31.6
2.26
7.4 A
29.6 A
1.5 V ns nC
A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
DocID028242 Rev 1 5/15
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STL20DNF06LAG
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
6/15 DocID028242 Rev 1
STL20DNF06LAG
Figure 8: Capacitance variations
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
Figure 10: Normalized on-resistance vs temperature (VGS = 5 V)
Figure 11: Normalized on-resistance vs temperature (VGS = 10 V)
Figure 12: Normalized V(BR)DSS vs temperature
Figure 13: Source-drain diode forward characteristics
DocID028242 Rev 1 7/15
Test circuits
3 Test circuits
Figure 14: Switching times test circuit for resistive load
STL20DNF06LAG
Figure 15: Gate charge test circuit
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
8/15 DocID028242 Rev 1
STL20DNF06LAG
4
4.1
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
PowerFLAT™ 5x6 double island WF type R package information
Figure 20
: PowerFLAT™ 5x6 double island WF type R package outline
DocID028242 Rev 1 9/15
Package information
Dim.
STL20DNF06LAG
Table 9: PowerFLAT™ 5x6 double island WF type R mechanical data mm
Min. Typ. Max.
D
D2
E
E2
A
A1
A2 b
E4
E5
E6
E7 e
L
L1
K
0.80
0.02
0.30
5.00
1.68
6.20
3.50
0.55
0.08
2.35
0.40
0.70
1.275
0.25
5.20
6.40
1.27
0.275
0.75
0.28
2.55
0.60
1.00
0.05
0.50
5.40
1.88
6.60
3.70
0.90
1.575
10/15 DocID028242 Rev 1
STL20DNF06LAG Package information
Figure 21
: PowerFLAT™ 5x6 double island recommended footprint (dimensions are in mm)
DocID028242 Rev 1 11/15
Package information
4.2 PowerFLAT™ 5x6 WF packing information
Figure 22
: PowerFLAT™ 5x6 WF tape
STL20DNF06LAG
Figure 23:
PowerFLAT™ 5x6 package orientation in carrier tape
12/15 DocID028242 Rev 1
STL20DNF06LAG
Figure 24
: PowerFLAT™ 5x6 reel
Package information
DocID028242 Rev 1 13/15
Revision history
5
STL20DNF06LAG
Revision history
Date
29-Sep-2015
Table 10: Document revision history
Revision
1
Changes
First release.
14/15 DocID028242 Rev 1
STL20DNF06LAG
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DocID028242 Rev 1 15/15
