STMicroelectronics TSU112IY Datasheet
STMicroelectronics TSU112IY is an automotive-grade, nanopower (920 nA), high accuracy (150 μV) 5 V CMOS operational amplifier. It offers ultra-low power consumption and can be efficiently supplied by a coin-type Lithium battery or a regulated voltage in low-power applications. The TSU112IY is ideal for sensor signal conditioning, battery management systems, on-board chargers, wireless chargers, and other applications requiring low power consumption and high accuracy.
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TSU112IY
Datasheet
Automotive grade, nanopower (920 nA), high accuracy (150 μV) 5 V CMOS operational amplifier
Product status link
TSU112IY
Related products
See TSU101 ,
TSU102 and
TSU104
See TSZ121 ,
TSZ122 and
TSZ124
For further power savings
For increased accuracy
Features
• AEC-Q100 qualified
• Sub-micro ampere current consumption: I cc
= 920 nA typ. at 25 °C
• Low offset voltage: 150 µV max. at 25 °C, 400 µV max. over full temperature range (-40 to 125 °C)
• Low noise over 0.1 to 10 Hz bandwidth: 4.6 µVpp
• Low supply voltage: 1.5 V to 5.5 V
• Rail-to-rail input and output
• Gain bandwidth product: 9 kHz typ.
• Low input bias current: 10 pA max. at 25 °C
• High tolerance to ESD: 4 kV HBM
• More than 25 years of typical equivalent lifetime supplied by a 220 mA.h
CR2032 coin type Lithium battery
• High accuracy without calibration
• Tolerance to power supply transient drops
Applications
• Battery management system: ultra-low power op-amp detects when battery is charging/discharging and wakes up CPU
• On-board chargers
• Signal conditioning for energy harvesting
• Wireless chargers
Description
The TSU112IY operational amplifier (op-amp) offers an ultra low-power consumption per channel of 920 nA typical and 1.3 µA maximum when supplied by 3.3 V.
Combined with a supply voltage range of 1.5 V to 5.5 V, these features allow the
TSU112IY to be efficiently supplied by a coin type Lithium battery or a regulated voltage in low-power applications.
The high accuracy of 150 µV max. and 9 kHz gain bandwidth make the TSU112IY ideal for sensor signal conditioning, battery management system, on-board (OBC) and wireless chargers.
DS13616 - Rev 2 - July 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Package pin connections
Figure 1. Pin connections for each package (top view)
TSU112IY
Package pin connections
MiniSO8
DFN8 2x2
1.
The exposed pad of the DFN8 2x2 can be connected to V
CC-
or left floating.
DS13616 - Rev 2 page 2/31
2
TSU112IY
Absolute maximum ratings and operating conditions
Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol
V
CC
V id
V in
I in
T stg
T j
Differential input voltage
Input current
Storage temperature
Parameter
Maximum junction temperature
Value
6
±V
CC
(V
CC -
) - 0.2 to (V
CC +
) + 0.2
10
-65 to 150
150
Unit
V mA
°C
R thja
ESD
Thermal resistance junction-to-ambient
HBM: human body model
CDM: charged device model
DFN8 2x2
MiniSO8
57
190
4000
1500
200
°C/W
V mA
1. All voltage values, except the differential voltage, are with respect to the network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. (V
CC+
) - V in
must not exceed 6 V, V in
- (V
CC-
) must not exceed 6 V.
4. The input current must be limited by a resistor in-series with the inputs.
5. R th
are typical values.
6. Short-circuits can cause excessive heating and destructive dissipation.
7. HBM test according to the standard AEC-Q100-002 and related to ESDA/JEDEC JS-001-2017.
8. The test CDM is performed in accordance with the standard AEC-Q100-011 and related to ESDA/JEDEC JS-002-2018.
9. Related to JEDEC JESD78E Apr. 2016.
Symbol
V
CC
V icm
T oper
Table 2. Operating conditions
Parameter
Supply voltage
Common-mode input voltage range
Operating free-air temperature range
Value
1.5 to 5.5
(V
CC-
) - 0.1 to (V
CC+
) + 0.1
-40 to 125
Unit
V
°C
DS13616 - Rev 2 page 3/31
TSU112IY
Electrical characteristics
3 Electrical characteristics
Table 3. Electrical characteristics at (V
CC+
) = 1.8 V with (V
CC-
) = 0 V, V icm
= V
CC connected to V
CC
/2 (unless otherwise specified)
/2, T amb
= 25 °C, and R
L
= 1 MΩ
Symbol Parameter Min.
Typ.
Max.
Unit
V io
ΔV io
/ΔT
I io
I ib
CMR
Input offset voltage
Input offset voltage drift
Input offset current
Input bias current
Common mode rejection ratio,
20 log (ΔV icm
/ΔV io
),
V icm
= 0 to 1.8 V
Conditions
DC performance
T = 25 °C
-40 °C < T< 125 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
76
71
1
1
99
150
400
2.5
10
50
10
50
µV
μV/°C pA dB
A vd
V
OH
V
OL
Large signal voltage gain,
V out
= 0.2 V to (V
CC+
) - 0.2 V
High-level output voltage,
(drop from V
CC
+)
Low-level output voltage
R
L
= 100 kΩ, T = 25 °C
R
L
= 100 kΩ,
-40 °C < T< 125 °C
R
L
= 10 kΩ, T = 25 °C
R
L
= 10 kΩ,
-40 °C < T< 125 °C
R
L
= 10 kΩ, T = 25 °C
R
L
= 10 kΩ,
-40 °C < T< 125 °C
T = 25 °C
95
82
2.8
120
11
9
5
25
40
25
40 mV
I out
I
CC
Output sink current,
V out
= V
CC
,
V
ΙD
= -200 mV
Output source current,
V out
= 0 V,
V
ΙD
= 200 mV
Supply current (per channel), no load,
V out
= V
CC
/2
-40 °C < T< 85 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
1.5
2
1.5
4
840 1300
1580 mA nA
AC performance
GBP
F u
Φ m
G m
Gain bandwidth product
Unity gain frequency
Phase margin
Gain margin
R
L
= 1 MΩ, C
L
= 60 pF
9
5.5
70
30 kHz degrees dB
SRp Slew rate (10 % to 90 %)
R
L
= 1 MΩ, C
L
= 60 pF,
V out
= 0.3 V to (V
CC+
) - 0.3 V
0.8
1.8
V/ms
DS13616 - Rev 2 page 4/31
Symbol t t
SRn e ʃe rec rec n n
P
P
Parameter
Slew rate (10 % to 90 %)
Conditions
R
L
= 1 MΩ, C
L
= 60 pF,
V out
= 0.3 V to (V
CC+
) - 0.3 V f = 100 Hz Equivalent input noise voltage
Low-frequency, peak-to-peak input noise
Overload recovery time (from positive rail)
Overload recovery time (from negative rail)
Bandwidth: f = 0.1 to 10 Hz
100 mV from rail in comparator,
R
L
= 100 kΩ,
V
ΙD
= ±1 V, -40 °C < T< 125 °C
100 mV from rail in comparator,
R
L
= 100 kΩ,
V
ΙD
= ±1 V, -40 °C < T< 125 °C
1. Guaranteed by design
Min.
1.2
Typ.
3.0
220
4.6
220
430
TSU112IY
Electrical characteristics
Max.
Unit
V/ms nV/√Hz
µV pp
µs
µs
Table 4. Electrical characteristics at (V
CC+
) = 3.3 V with (V connected to V
CC
CC-
) = 0 V, V icm
= V
CC
/2, T
/2 (unless otherwise specified) amb
= 25 °C, and R
L
= 1 MΩ
Symbol Min.
Typ.
Max.
Unit
V io
ΔV io
/ΔT
I io
I ib
CMR
A vd
V
OH
V
OL
I out
Parameter
Input offset voltage
Conditions
DC performance
T = 25 °C
-40 °C < T< 125 °C
Input offset voltage drift -40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
Input bias current
Common mode rejection ratio,
20 log (ΔV icm
/ΔV io to 3.3 V
), V icm
= 0
Large signal voltage gain,
V out
= 0.2 V to
(V
CC+
) - 0.2 V
R
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
L
= 100 kΩ, T = 25 °C
R
L
= 100 kΩ, -40 °C < T< 125 °C
High-level output voltage,
(drop from V
CC
+)
Low-level output voltage
R
L
= 10 kΩ, T = 25 °C
R
L
= 10 kΩ, -40 °C < T< 125 °C
R
L
= 10 kΩ, T = 25 °C
R
L
= 10 kΩ, -40 °C < T< 125 °C
T = 25 °C Output sink current,
V out
= V
CC
,
V
ΙD
= -200 mV
Output source current,
V out
= 0 V,
V
ΙD
= 200 mV
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
81
76
100
88
12
6
9
5
1
1
102
128
11
9
22
17
25
40
25
40
150
400
2.5
10
50
10
50
µV
μV/°C pA dB mV mA
DS13616 - Rev 2 page 5/31
Symbol
I
CC
Parameter
Supply current (per channel), no load,
V out
= V
CC
/2
Conditions
T = 25 °C
-40 °C < T< 125 °C
AC performance t t
GBP
F u
Φ m
G m
SRp
SRn e ʃe rec rec n n
P
N
Gain bandwidth product
Unity gain frequency
Phase margin
Gain margin
R
L
= 1 MΩ, C
L
= 60 pF
Slew rate (10 % to 90 %)
Slew rate (10 % to 90 %)
R
L
= 1 MΩ, C
L
= 60 pF,
V out
= 0.3 V to (V
CC+
) - 0.3 V
R
L
= 1 MΩ, C
L
= 60 pF,
V out
= 0.3 V to (V
CC+
) - 0.3 V f = 100 Hz Equivalent input noise voltage
Low-frequency, peak-to-peak input noise
Bandwidth: f = 0.1 to 10 Hz
Overload recovery time (from positive rail)
Overload recovery time (from negative rail)
100 mV from rail in comparator,
R
L
= 100 kΩ,
V
ΙD
= ±1 V, -40 °C < T< 125 °C
100 mV from rail in comparator,
R
L
= 100 kΩ,
V
ΙD
= ±1 V, -40 °C < T< 125 °C
1. Guaranteed by design
Min.
0.9
1.5
Typ.
920
3.0
200
4.6
9
5.5
70
30
1.8
420
880
TSU112IY
Electrical characteristics
Max.
1300
1650
Unit nA kHz degrees dB
V/ms
V/ms nV/√Hz
µV pp
µs
µs
Table 5. Electrical characteristics at (V
CC+
) = 5 V with (V
CC-
) = 0 V, V icm
= V
CC
/2, T to V
CC
/2 (unless otherwise specified) amb
= 25 °C, and R
L
= 1 MΩ connected
Symbol Parameter Conditions Min. Typ. Max.
Unit
ΔV
V
CMR Common mode rejection ratio, 20 log (ΔV icm
/ΔV io
A
I
I io io io ib
/ΔT
SVR vd
Input offset voltage
Input offset voltage drift
Input bias current
Supply voltage rejection ratio, V
(V
V icm
CC+
= 0 V
Large signal voltage gain, V
) - 0.2 V
CC out
DC performance
), V
= 1.5 to 5.5 V,
= 0.2 V to icm
= 0 to 5 V
T = 25 °C
-40 °C < T< 125 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
1
1
85 106
80
89 107
-40 °C < T< 125 °C 84
R
L
= 100 kΩ, T = 25 °C 105
R
L
= 100 kΩ, -40 °C < T< 125 °C 92
132
150
400
µV
2.5
μV/°C
10
50
10
50 pA dB
DS13616 - Rev 2 page 6/31
TSU112IY
Electrical characteristics
Symbol t t
V
V
I
I
OH out
CC
GBP
F u
Φ m
G m
SRp
SRn e ʃe
OL rec rec n n
P
N
Parameter
High-level output voltage, (drop from V
CC
Low-level output voltage
Output sink current, V out
Output source current, V
= V out
CC
, V
ΙD
= 0 V, V
= -200 mV
ΙD
Supply current (per channel), no load, V
= 200 mV out
+)
= V
CC
/2
AC performance
Conditions
R
L
= 10 kΩ, T = 25 °C
R
L
= 10 kΩ, -40 °C < T< 125 °C
R
L
= 10 kΩ, T = 25°C
R
L
= 10 kΩ, -40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
T = 25 °C
-40 °C < T< 125 °C
Gain bandwidth product
Unity gain frequency
R
L
= 1 MΩ, C
L
= 60 pF
Phase margin
Gain margin
Slew rate (10 % to 90 %)
Slew rate (10 % to 90 %)
Equivalent input noise voltage
Low-frequency, peak-to-peak input noise
Overload recovery time (from positive rail)
Overload recovery time (from negative rail)
R
L
= 1 MΩ, C
L
= 60 pF,
V out
= 0.3 V to (V
CC+
) - 0.3 V
R
L
= 1 MΩ, C
L
= 60 pF,
V out
= 0.3 V to (V
CC+
) - 0.3 V f = 100 Hz
Bandwidth: f = 0.1 to 10 Hz
100 mV from rail in comparator,
R
L
= 100 kΩ,
V
ΙD
= ±1 V -40 °C < T< 125 °C
100 mV from rail in comparator,
R
L
= 100 kΩ,
V
ΙD
= ±1 V, -40 °C < T< 125 °C
1. Guaranteed by design
Min. Typ. Max.
Unit
12 25
10
40
25 mV
40
30 45
15
9
18
39
1000 1400
2000 mA nA
0.9
1.5
9
6
70
30
1.9
3.1
220
4.6
650
1300 kHz degrees dB
V/ms
V/ms nV/√Hz
µV
µs
µs pp
DS13616 - Rev 2 page 7/31
4
TSU112IY
Electrical characteristic curves
Electrical characteristic curves
Figure 2. Supply current vs. supply voltage at low
V
ICM
Figure 3. Supply current vs. supply voltage at high
V
ICM
Figure 4. Supply current vs. supply voltage at mid
V
ICM
Figure 5. Supply current vs. input common-mode voltage
DS13616 - Rev 2 page 8/31
Figure 6. Input offset voltage vs. input commonmode voltage
TSU112IY
Electrical characteristic curves
Figure 7. Input offset voltage distribution
Figure 8. Input offset voltage temperature coefficient distribution from -40 °C to 25 °C
Figure 9. Input offset voltage temperature coefficient distribution from 25 °C to 125 °C
DS13616 - Rev 2 page 9/31
TSU112IY
Electrical characteristic curves
Figure 10. Input offset voltage vs. temperature at
3.3 V
Figure 11. Input bias current vs. temperature at mid
V
ICM
Figure 12. High level output voltage (drop from
V
CC
+) Figure 13. Low level output voltage
DS13616 - Rev 2 page 10/31
TSU112IY
Electrical characteristic curves
Figure 14. Output characteristics at 1.5 V supply voltage
Figure 15. Output characteristics at 1.8 V supply voltage
Figure 16. Output characteristics at 3.3 V supply voltage
Figure 17. Output characteristics at 5 V supply voltage
DS13616 - Rev 2 page 11/31
TSU112IY
Electrical characteristic curves
Figure 18. Output characteristics at 5.5 V supply voltage
Figure 19. Output saturation with a sinewave on the input
Figure 20. Output saturation with a square wave on the input
Figure 21. Phase reversal free
DS13616 - Rev 2 page 12/31
TSU112IY
Electrical characteristic curves
Figure 22. Recovery time from negative saturation vs. supply voltage
Figure 23. Recovery time from positive saturation vs. supply voltage
Figure 24. Slew rate vs. supply voltage
Figure 25. Output swing vs. input signal frequency
DS13616 - Rev 2 page 13/31
Figure 26. Triangulation of a sine wave
TSU112IY
Electrical characteristic curves
Figure 27. Large signal response at 3.3 V supply voltage
Figure 28. Small signal response at 3.3 V supply voltage
Figure 29. Overshoot vs. capacitive load at 3.3 V supply voltage
DS13616 - Rev 2 page 14/31
DS13616 - Rev 2
TSU112IY
Electrical characteristic curves
Figure 30. Over/under shoot vs supply voltage
Figure 31. Bode diagram at 1.5 V supply voltage
Figure 32. Bode diagram at 1.8 V supply voltage Figure 33. Bode diagram at 3.3 V supply voltage
Figure 34. Bode diagram at 5 V supply voltage Figure 35. Bode diagram at 5.5 V supply voltage page 15/31
TSU112IY
Electrical characteristic curves
Figure 36. In series resistor Riso vs. capacitive load
Figure 37. Noise amplitude on 0.1 to 10 Hz freq.
range
Figure 38. Noise vs. frequency for different common mode input voltages
Figure 39. Noise vs. frequency for different power supply voltages
DS13616 - Rev 2 page 16/31
TSU112IY
Electrical characteristic curves
Figure 40. Gain bandwidth product vs. input common mode voltage
DS13616 - Rev 2 page 17/31
5
5.1
5.1.1
TSU112IY
Application information
Application information
Nanopower applications
The TSU112IY can operate from 1.5 V to 5.5 V. The parameters are fully specified at 1.8 V, 3.3 V, and 5 V supply voltages and are very stable in the full V
CC
range. Additionally, the main specifications are guaranteed on the industrial temperature range from -40 to 125 °C.
Schematic optimization aiming for nanopower
To benefit from the full performance of the TSU112IY, the impedances must be maximized so that current consumption is not lost where it is not required.
For example, an aluminum electrolytic capacitance can have significantly high leakage. This leakage may be greater than the current consumption of the op-amp. For this reason, ceramic type capacitors are preferred.
For the same reason, big resistor values should be used in the feedback loop. However, there are two main limitations to be considered when choosing a resistor.
1.
Noise generated: a 100 kΩ resistor generates 40 nV/√Hz, a bigger resistor value generates even more noise.
2.
Leakage on the PCB: leakage can be generated by moisture. This can be improved by using a specific coating process on the PCB.
DS13616 - Rev 2 page 18/31
5.1.2
TSU112IY
Rail-to-rail input
PCB layout considerations
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins.
Minimizing the leakage from sensitive high impedance nodes on the inputs of the TSU112IY can be performed with a guarding technique. The technique consists of surrounding high impedance tracks by a low impedance track (the ring). The ring is at the same electrical potential as the high impedance node.
Therefore, even if some parasitic impedance exists between the tracks, no leakage current can flow through them as they are at the same potential (see Figure 1).
Figure 41. Guarding on the PCB
5.2
5.3
Rail-to-rail input
The TSU112IY is built with two complementary PMOS and NMOS input differential pairs. Thus, the device has a rail-to-rail input, and the input common mode range is extended from (V
CC-
) - 0.1 V to (V
CC+
) + 0.1 V.
The TSU112IY has been designed to prevent phase reversal behavior.
Input offset voltage drift overtemperature
The maximum input voltage drift variation overtemperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using
.
Equation 1
∆V io
∆T
= max
V io
T – V io
( 25 °C )
Where T = -40 °C and 125 °C.
The TSU112IY datasheet maximum values are guaranteed by measurements on a representative sample size ensuring a C pk
(process capability index) greater than 1.3.
DS13616 - Rev 2 page 19/31
5.4
TSU112IY
Long term input offset voltage drift
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
•
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2 .
Equation 2
A
FV
= e
β .
( V
S
– V
U
)
Where:
A
FV
is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
V
S
is the stress voltage used for the accelerated test
V
U
is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3 .
Equation 3
A
FT
= e
E k
.
1
T
U
–
1
T
S
Where:
A
FT
is the temperature acceleration factor
E a
is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10
-5
eV.K
-1
)
T
U
is the temperature of the die when V
U
is used (°K)
T
S
is the temperature of the die under temperature stress (°K)
The final acceleration factor, A
F
, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor ( Equation 4 ).
Equation 4
A
F
= A
FT
× A
FV
A
F is calculated using the temperature and voltage defined in the mission profile of the product. The A
F
value can then be used in
to calculate the number of months of use equivalent to 1000 hours of reliable stress duration.
Equation 5
Months = A
F
× 1000 h × / ( × 365.25 days )
To evaluate the op amp reliability, a follower stress condition is used where V
CC
is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The V io
drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement
Equation 6
V
CC
= maxV op
with V icm
= V
CC
/ 2
The long term drift parameter (ΔV io
), estimating the reliability performance of the product, is obtained using the ratio of the V io
).
Equation 7
∆V io
=
V io drift
( month s )
Where V io
drift is the measured drift value in the specified test conditions after 1000 h stress duration.
DS13616 - Rev 2 page 20/31
5.5
5.6
5.7
5.8
TSU112IY
Using the TSU112IY with sensors
Using the TSU112IY with sensors
The TSU112IY has MOS inputs, thus input bias currents can be guaranteed down to 10 pA maximum at ambient temperature. This is an important parameter when the operational amplifier is used in combination with high impedance sensors.
The TSU112IY is perfectly suited for trans-impedance configuration. This configuration allows a current to be converted into a voltage value with a gain set by the user. It is an ideal choice for portable electrochemical gas sensing or photo/UV sensing applications. The TSU112IY, using trans-impedance configuration, is able to provide a voltage value based on the physical parameter sensed by the sensor.
Fast desaturation
When the TSU112IY goes into saturation mode, it takes a short period of time to recover, typically 420/880 µs.
When recovering after saturation, the TSU112IY does not exhibit any voltage peaks that could generate issues
(such as false alarms) in the application (see
We can observe that this circuit still exhibits good gain even close to the rails i.e. A vd
greater than 88 dB for V cc
=
3.3 V with V out
varying from 200 mV up to a supply voltage minus 200 mV. With a trans-impedance schematic, a voltage reference can be used to keep the signal away from the supply rails.
Using the TSU112IY in comparator mode
The TSU112IY can be used as a comparator. In this case, the output stage of the device always operates in saturation mode. In addition,
shows that the current consumption is not higher and even decreases smoothly close to the rails. The TSU112IY is obviously an operational amplifier and is therefore optimized for use in linear mode. We recommend using the TS88 series of nanopower comparators if the primary function is to perform a signal comparison only.
ESD structure of the TSU112IY
The TSU112IY is protected against electrostatic discharge (ESD) with dedicated diodes (see
). These diodes must be considered at application level especially when signals applied on the input pins go beyond the power supply rails (V
CC+
) or (V
CC-
).
Figure 42. ESD structure
-
TSU112IY
+
5.9
Current through the diodes must be limited to a maximum of 10 mA as stated in Table 1. A serial resistor on the inputs can be used to limit this current.
EMI robustness of nanopower devices
Nanopower devices exhibit higher impedance nodes and consequently they are more sensitive to EMI. To improve the natural robustness of the TSU112IY device, we recommend to add three capacitors of around 22 pF each between the two inputs, and between each input and ground. These capacitors lower the impedance of the input at high frequencies and therefore reduce the impact of the radiation
DS13616 - Rev 2 page 21/31
6
6.1
TSU112IY
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
DFN8 2x2 package information
Figure 43. DFN8 2x2 package outline
DS13616 - Rev 2 page 22/31
Note:
TSU112IY
DFN8 2x2 package information
Ref.
A
A1 b
D
D1
E
E1 e
F
G aaa
Min.
0.70
0.20
1.95
0.80
1.95
1.50
0.25
Table 6. DFN8 2x2 package mechanical data
Dimensions
Millimeters
Typ.
0.75
0.10
0.25
2.00
0.90
2.00
1.60
0.50
0.05
0.30
0.10
Max.
0.80
0.30
2.05
1.00
2.05
1.70
0.35
Min.
0.70
0.20
1.95
0.80
1.95
1.50
0.25
Inches
Typ.
0.75
0.10
0.25
2.00
0.90
2.00
1.60
0.50
0.05
0.30
010
The terminal 1 corner must be identified on the top surface by using a laser marking dot.
Figure 44. DFN8 2x2 recommended footprint
Max.
0.80
0.30
2.05
1.00
2.05
1.70
0.35
DS13616 - Rev 2 page 23/31
6.2
MiniSO8 package information
Figure 45. MiniSO8 package outline
TSU112IY
MiniSO8 package information
DS13616 - Rev 2 page 24/31
Note:
TSU112IY
MiniSO8 package information
Dim.
D
E b c
E1 e
A
A1
A2
A3
L
L1 k ccc
0
0.75
0.30
0.22
0.08
2.80
4.65
2.80
Min.
0.40
Table 7. MiniSO8 package mechanical data
Millimeters
Typ.
Inches
Min.
0.85
0.35
3.00
4.90
3.00
0.65
0.60
0.95
Max.
1.10
0.15
0.95
0.40
0.40
0.23
3.20
5.15
3.10
0.80
0.40
0.05
0.75
0.30
0.28
0.15
2.90
4.70
2.90
0 8
0.10
0
Typ.
0.85
0.35
3.00
4.90
3.00
0.65
0.95
Max.
1.10
0.15
0.95
0.40
0.36
0.19
3.10
5.10
3.10
0.70
8
0.10
TSSOP stands for thin shrink small outline package. Dimensions "D" and "E1" do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
Figure 46. MiniSO8 recommended footprint
DS13616 - Rev 2 page 25/31
7
TSU112IY
Ordering information
Ordering information
Table 8. Order code
Order code
TSU112IYQ3T
TSU112IYST
Temperature range
Package
DFN8 2x2
Marking
K30
1. All devices are delivered in tape and reel packing.
2. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 &
Q002 or equivalent.
3. This package is under qualification.
DS13616 - Rev 2 page 26/31
Revision history
Date
01-Mar-2021
09-Jul-2021
Revision
1
2
Table 9. Document revision history
Changes
Initial release
Updated the first row features on the cover page.
TSU112IY
DS13616 - Rev 2 page 27/31
TSU112IY
Contents
Contents
DS13616 - Rev 2 page 28/31
TSU112IY
List of tables
List of tables
Table 3. Electrical characteristics at (V
Table 4. Electrical characteristics at (V
Table 5. Electrical characteristics at (V
DS13616 - Rev 2 page 29/31
TSU112IY
List of figures
List of figures
Figure 2. Supply current vs. supply voltage at low V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Supply current vs. supply voltage at high V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Supply current vs. supply voltage at mid V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 11. Input bias current vs. temperature at mid V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12. High level output voltage (drop from V
+). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DS13616 - Rev 2 page 30/31
TSU112IY
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13616 - Rev 2 page 31/31
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