STMicroelectronics RHR64 Datasheet
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RHR61, RHR64
Rad-hard, low-power, rail-to-rail CMOS operational amplifiers
Datasheet - production data
Parameter
Quality level
Package, mass
Temp. range
Notes:
(1)
SMD: standard microcircuit drawing
(2)
EPPL = European preferred part list
Features
•
Single and quad CMOS operational amplifiers (op amp)
•
Unity gain stable on 100 pF load
•
Very low power supply: 1.5 V to 5.5 V
•
Very low consumption: 60 µA max
•
Low offset voltage: 1 mV max
•
Low input bias: 1 pA
•
Input and output rail-to-rail
•
100 krad TID (high-dose rate)
•
SEL immune at 120 MeV.cm²/mg
•
SET characterized
Description
The RHR61 and RHR64 devices are pure CMOS single and quad op amps respectively. The
RHR61 is packaged in a flat hermetic 8-lead and the RHR64 in a flat hermetic 14-lead. Both devices are guaranteed in radiation and over the temperature range -55 °C to 125 °C. They are for general use in any space application.
Table 1: Device summary
RHR64K1 RHR61K01V RHR64K01V RHR61K1
—
Engineering model
Flat-8, 0.50 g Flat-14, 0.70 g
5962R1620401VXC 5962R1620501VXC
QML-V flight model
Flat-8, 0.50 g Flat-14, 0.70 g
—
-55 °C to 125 °C
October 2017 DocID027171 Rev 3
This is information on a product in full production.
1/20 www.st.com
Contents
Contents
RHR61, RHR64
1 Pin description ................................................................................ 3
2 Absolute maximum ratings and operating conditions ................. 4
3 Electrical characteristics ................................................................ 5
4 Electrical characteristic curves ...................................................... 9
6 Package information ..................................................................... 14
Ceramic Flat-8 package information ............................................... 15
Ceramic Flat-14 package information ............................................. 16
7 Ordering information ..................................................................... 17
8 Shipping information .................................................................... 18
9 Revision history ............................................................................ 19
2/20 DocID027171 Rev 3
RHR61, RHR64
1 Pin description
Pin description
Figure 1: Pin connections of Ceramic Flat-8 and Ceramic Flat-14 (top view)
DocID027171 Rev 3 3/20
Absolute maximum ratings and operating conditions
2
4/20
RHR61, RHR64
Absolute maximum ratings and operating conditions
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
Symbol
Table 2: Absolute maximum ratings
Parameter Value Unit
V
CC
V id
V in
T stg
T j
Differential input voltage (2)
Storage temperature
Maximum junction temperature
6
±V
CC
(V
CC-
) - 0.2 to (V
CC+
) +
0.2
-65 to 150
150
125
V
°C
R thja
Thermal resistance junction-to-
Ceramic Flat-8
Ceramic Flat-14 120
40
°C/W
R thjc
ESD
Thermal resistance junction-to-
Ceramic Flat-8
Ceramic Flat-14
RHR61
22
4
300
700 kV
V
RHR64 1300
Latch-up immunity 200 mA
Notes:
(1)
All voltage values, except differential voltage are measured with respect to network ground terminal
(2)
Differential voltages are the non-inverting input terminal with respect to the inverting input terminal
(3)
V
CC
- V in
must not exceed 6 V
(4)
Short circuits can cause excessive heating and destructive dissipation
(5)
R th
are typical values
(6)
Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating.
(7)
Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5
Ω). This is done for all couples of connected pin combinations while the other pins are floating.
(8)
Charged device model: all pins and package are charged together to the specified voltage and then discharged directly to ground through only one pin. This is done for all pins.
Symbol
Table 3: Operating conditions
Parameter Value Unit
V
CC
V icm
Supply voltage
Common-mode input voltage
T amb
Operating free-air temperature range
1.5 to 5.5
(V
CC-
) - 0.1 to (V
CC+
) +
0.1
-55 to 125
V
°C
DocID027171 Rev 3
RHR61, RHR64 Electrical characteristics
3
Symbol
V io
DV io
I io
I ib
CMR
A vd
V
OH
V
OL
I out
I
CC
Electrical characteristics
Table 4: VCC+ = 1.8 V, VCC- = 0 V, Vicm = 0.9 V, Tamb = 25 °C, and load (RL) connected to
0.9 V (unless otherwise specified)
Parameter Conditions
Min
.
Typ. Max. Unit
DC performance
Offset voltage
1
3 mV
Input offset voltage drift
Input offset current
(V out
= 0.9 V)
Input bias current
(V out
= 0.9 V)
Common mode rejection ratio
20 log (ΔV ic
/ΔV io
)
Large signal voltage gain
High-level output voltage
Low-level output voltage
I sink
I source
Supply current (per channel)
GBP Gain bandwidth product ɸm
G m
SR e n
Phase margin
Gain margin
Slew rate
Equivalent input noise voltage
-55 °C < T
-55 °C < T amb amb
< 125 °C
< 125 °C
-55 °C < T amb
< 125 °C
0 V to 0.9 V, V out
= 0.9 V
-55 °C < T amb
< 125 °C
0 V to 1.8 V, V out
= 0.9 V
-55 °C < T amb
< 125 °C
R
L
= 10 kΩ, V out
= 0.5 V to 1.3 V
-55 °C < T amb
< 125 °C
R
L
= 10 kΩ
-55 °C < T amb
< 125 °C
R
L
=
10 kΩ
-55 °C < T amb
< 125 °C
V ο = 1.8 V
-55 °C < T amb
< 125 °C
V ο = 0 V
-55 °C < T amb
< 125 °C
No load, V out
= 0.9 V
-55 °C < T amb
< 125 °C
AC performance
R
L
= 2 kΩ, C
L
= 100 pF
-55 °C < T amb
< 125 °C
R
L
=
2 kΩ, C
L
= 100 pF
R
L
=
2 kΩ, C
L
= 100 pF
V
IN
= 0.5 V to V
CC
-0.5V, 10 % to
90 %, R
L
=
2 kΩ, C
L
= 100 pF, Av
= 1
6
4
95
5
4
12
-10
50
600 740
300
48
11
0.2 0.27
70
67
56
53
83
78
35
50
4
1
1
1
1
74
-55 °C < T amb
< 125 °C
0.1
5 f = 1 kHz f = 10 kHz
65
50
-6
-4
60
62
35
50
70
150
70
150
μV/°C pA dB mV mA
µA kHz
Degrees dB
V/μs nV/√Hz
DocID027171 Rev 3 5/20
Electrical characteristics
Symbol
RHR61, RHR64
Table 5: VCC+ = 3.3 V, VCC- = 0 V, Vicm = 1.65 V, Tamb = 25 °C, and load (RL) connected to
1.65 V (unless otherwise specified)
Parameter Conditions Min.
Typ
.
Max. Unit
DC performance
V io
Offset voltage
-55 °C < T amb
< 125 °C
1
3 mV
DV io
I io
I ib
CMR
A vd
V
OH
V
OL
I out
I
CC ɸm
G m
SR e n
Input offset voltage drift
Input offset current
Input bias current
Common mode rejection ratio
20 log (ΔV ic
/ΔV io
)
Large signal voltage gain
High-level output voltage
Low-level output voltage
I sink
I source
Supply current (per channel)
GBP Gain bandwidth product
Phase margin
Gain margin
Slew rate
Equivalent input noise voltage
-55 °C < T amb
< 125 °C
-55 °C < T amb
< 125 °C
0 V to 1.65 V, V out
= 1.65 V
-55 °C < T amb
< 125 °C
0 V to 3.3 V, V out
= 1.65 V
-55 °C < T amb
< 125 °C
R
L
= 10 kΩ, V out
= 0.5 V to 2.8 V
-55 °C < T amb
< 125 °C
R
L
= 10 kΩ
-55 °C < T amb
< 125 °C
R
L
=
10 kΩ
-55 °C < T amb
< 125 °C
V ο = 3.3 V
-55 °C < T amb
< 125 °C
V ο = 0 V
-55 °C < T amb
< 125 °C
No load, V out
= 1.75 V
-55 °C < T amb
< 125 °C
AC performance
R
L
= 2 kΩ, C
L
= 100 pF
-55 °C < T amb
< 125 °C
R
L
=
2 kΩ, C
L
= 100 pF
R
L
=
2 kΩ, C
L
= 100 pF
V
IN
= 0.5 V to V
CC
-0.5V, 10 % to
90 %, R
L
=
2 kΩ, C
L
= 100 pF, Av
= 1
-55 °C < T amb
< 125 °C f = 1 kHz f = 10 kHz
30
25
75
72
60
56
87
82
35
50
98
6
7
45
-45
55
610 820
310
50
11
0.22
0.17
4
1
1
1
1
79
0.2
9
65
50
-30
-25
64
66
35
50
70
150
70
150
μV/°C pA dB mV mA
µA kHz
Degrees dB
V/μs nV/√Hz
6/20 DocID027171 Rev 3
RHR61, RHR64 Electrical characteristics
Table 6: VCC+ = 5 V, VCC- = 0 V, Vicm = 2.5 V, Tamb = 25 °C, and RL connected to 2.5 V
(unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
1
3 mV
I
I
V
A
V
V ɸm
G e io
DV
I
I io ib
CMR
SVR vd
OH
OL out
CC
GBP m
SR n io
THD+e n
I
I
Offset voltage
Input offset voltage drift
Input offset current
(V out
= 2.5 V)
Input bias current
(V out
= 2.5 V)
Common mode rejection ratio
20 log (ΔV ic
/ΔV io
)
Supply voltage rejection ratio
20 log (ΔV
Phase margin
Gain margin
Equivalent input noise voltage
CC
/ΔV io
)
Large signal voltage gain
High-level output voltage
Low-level output voltage sink source
Supply current (per channel)
Gain bandwidth product
Slew rate
Total harmonic distortion
-55 °C < T
-55 °C < T amb amb
< 125 °C
< 125 °C
-55 °C < T amb
< 125 °C
0 V to 2.5 V, V out
= 2.5 V
-55 °C < T amb
< 125 °C
0 V to 5.0 V, V out
= 2.5 V
-55 °C < T amb
< 125 °C
V
CC
= 1.8 to 5 V
-55 °C < T amb
< 125 °C 70
R
L
= 10 kΩ, V out
= 0.5 V to 4.5 V 88
-55 °C < T amb
< 125 °C
R
L
=
10 kΩ
83
35
-55 °C < T amb
< 125 °C
R
L
=
10 kΩ
-55 °C < T amb
< 125 °C
50
V ο = 5 V
-55 °C < T amb
< 125 °C
40
35
V ο = 0 V
T min
< T amb
< T max
No load, V out
= 2.5 V
-55 °C < T amb
< 125 °C
74
63
58
75
77
AC performance
R
L
=
2 kΩ, C
L
= 100 pF
-55 °C < T amb
< 125 °C
R
L
=
2 kΩ, C
L
= 100 pF
R
L
=
2 kΩ, C
L
= 100 pF
V
IN
= 0.5 V to V
CC
-0.5V, 10 % to 90 %, R
L
= 2 kΩ, C
L
= 100 pF, Av = 1
-55 °C < T amb
< 125 °C f = 1 kHz f = 10 kHz
G = 1, f = 1 kHz, R
L
=
100 kΩ,
V out
= 2 V pp
630
330
0.25
0.20
1
1
1
83
4
1
102
98
7
6
69
-69
59
920
50
12
0.34
65
50
0.002
35
50
70
150
70
150
-40
-35
69
72
μV/°C pA dB mV mA
µA kHz
Degrees dB
V/μs nV/√Hz
%
DocID027171 Rev 3 7/20
Electrical characteristics
Symbol
RHR61, RHR64
Table 7: Electrical characteristics after 100 krad, VCC+ = 1.8 V, VCC- = 0 V, Vicm = 0.9 V, Tamb
= 25 °C, and load (RL) connected to VCC/2 (unless otherwise specified). Min. and max. values obtained on a sample size of 10 parts from 2 different lots (2x5). Non listed parameters are not impacted by the dose.
Parameter Conditions Min. Typ. Max. Unit
V io
A vd
I source
I
CC
Output voltage
Common mode rejection ratio 20 log
(ΔV ic
/ΔV io
)
Large signal voltage gain
Output source current
Supply current (per channel)
0 V to 1.8 V, V out
= 0.9 V
0 V to 0.9 V, Vout = 0.9 V
R
L
= 10 kΩ, V out
= 0.5 V to
1.3 V
V
O
= 0 V
No load, V out
= 0.9 V
51
61
81
—
1.7 mV dB
-1.5 mA
110 µA
Notes:
(1)
The CMR from 0 V to V
CC
/2 has not been characterized in radiation
Symbol
Table 8: Electrical characteristics after 100 krad, VCC+ = 5 V, VCC- = 0 V, Vicm = 2.5 V, Tamb =
25 °C, and load (RL) connected to VCC/2 (unless otherwise specified). Min. and max. values obtained on a sample size of 10 parts from 2 different lots (2x5). Non listed parameters are not impacted by the dose.
Parameter Conditions Min. Typ. Max. Unit
V io
I ib
SVR
Output voltage
Input bias current
Common mode rejection ratio 20 log
(ΔV ic
/ΔV io
)
Supply voltage rejection ratio 20 log
(ΔV
CC
/ΔV io
)
Vout = 2.5 V
0 V to 5 V, V out
= 2.5 V
V
CC
= 1.8 V to 5 V
220
62
71
—
1.5 mV pA dB
A vd
I sink
I source
I
CC
Large signal voltage gain
Output sink current
Output source current
Supply current (per channel)
R
L
= 10 kΩ, V out
= 0.5 V to
4.5 V
V
O
= 5 V
V
O
= 0 V
No load, V out
= 2.5 V
87
35
-32 mA
150 µA
Notes:
(1)
The CMR from 0 V to V
CC
/2 has not been characterized in radiation
8/20 DocID027171 Rev 3
RHR61, RHR64 Electrical characteristic curves
4
Figure 2: Supply current vs supply voltage
40
35
30
Electrical characteristic curves
Vicm=Vcc/2
T=125°C T=25°C
Figure 3: Input offset voltage vs input commonmode voltage at VCC = 1.5 V
400
Vcc=1.5V
200
25 0
20 T=-40°C T=-55°C
-200
15
-400
10
T=125°C T=25°C T=-40°C T=-55°C
5 -600
0
0 1 2 3
Supp ly Voltage (V)
4 5
-800
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Input Common Mode Voltage (V)
Figure 4: Input offset voltage vs input commonmode voltage at VCC = 5 V
400
Vcc=5V
200
0
-200
-400
0
T=125°C
T=25°C
T=-40°C
T=-55°C
1 2 3 4
Input Common Mode Voltage (V)
5
Figure 5: Input offset voltage vs output voltage at
VCC = 1.5 V
0
-25
-50
-75
-100
-125
-150
-175
-200 T=-55°C T=-40°C T=25°C T=125°C
-225
Vcc=1.5V
Rl=2k
Ω
-250
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00
Output Voltage (V)
DocID027171 Rev 3 9/20
Electrical characteristic curves
Figure 6: Input offset voltage vs output voltage at VCC = 5 V
125
100
75
50
25
0
-25
-50
-75
-100
-125
-150
T=-55°C T=-40°C T=25°C
-175
-200
Vcc=5V
Rl=2k
Ω
-225
0.5
1.0
1.5
2.0
2.5
3.0
3.5
T=125°C
4.0
4.5
Output Voltage (V)
Figure 8: VOL vs supply voltage
40
35
30
25
20
15
10
T=-55°C T=-40°C T=25°C T=125°C
5
Rl=2k
Ω
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcc (V)
60
Figure 10: Bode diagram at VCC = 1.5 V
40
Phase
20
Gain
0
-20
-40
1k
Vcc=1.5V
Vicm=0.75V
Rl=2k
Ω
Cl=100pF
Gain=100
10k 100k
Frequency(Hz)
T=-55°C
T=-40°C
T=25°C
T=125°C
1M
-180
-210
-240
-270
-300
0
-30
-60
-90
-120
-150
RHR61, RHR64
Figure 7: VOH vs supply voltage
45
40
35
30
25
20
15
T=-55°C T=-40°C T=25°C T=125°C
10
5 Rl=2k
Ω
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcc (V)
Figure 9: Output current vs output voltage at
VCC = 5 V
Sink
Vid=-1V
Vcc=5V
T=125°C T=25°C T=-40°C T=-55°C
Source
Vid=1V
0.0 0.5 1.0 1.5 2.0
2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
60
40
Figure 11: Bode diagram at VCC = 5 V
0
Phase
T=-55°C
T=-40°C
T=25°C
T=125°C
-60
20
Gain
0
-20
-40
1k
Vcc=5V
Vicm=2.5V
Rl=2k
Ω
Cl=100pF
Gain=100
10k 100k
Frequency(Hz)
1M
-120
-180
-240
-300
10/20 DocID027171 Rev 3
RHR61, RHR64
Figure 12: Slew rate vs supply voltage
0.5
0.3
0.1
-0.1
-0.3
T=125°C T=25°C T=-40°C T=-55°C
Vicm=Vcc/2
Vload=Vcc/2
Rl=2k
Ω
Cl=100pF
-0.5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
Figure 14: Positive slew rate vs supply voltage
3
2
1
0
-1
-2
-3
0
T=125°C
T=25°C
T=-40°C
T=-55°C
10
Time (µs)
20
Vcc=5V
Vicm=Vcc/2
Rl=2k
Ω
Cl=100pF
30
Figure 16: Phase margin vs output current at
VCC = 5 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Electrical characteristic curves
Figure 13: Negative slew rate vs supply voltage
3
2
1
T=-55°C
T=-40°C
T=25°C
T=125°C
Vcc=5V
Vicm=Vcc/2
Rl=2k
Ω
Cl=100pF
0
-1
-2
-3
0 5
Time (µs)
10 15
Figure 15: Phase margin vs output current at
VCC = 1.5 V
100
90
80
70
60
50
40
30
20
10
0
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1000
Figure 17: Noise vs frequency
Vcc=5V
T=25°C
Vicm=2.5V
100
10
10
Vicm=4.5V
100 1000
Frequency (Hz)
10000 100000
DocID027171 Rev 3 11/20
Electrical characteristic curves
Figure 18: Small step
RHR61, RHR64
Figure 19: Power supply rejection ratio vs frequency
100
PSRR
+
80
Vcc=5V
Vicm=2.5V
Rl=2k
Ω
Cl=100pF
T=25°C
60
40
20
0
10
Vcc=5V
Vicm=2.5V
Gain=1
Rl=2k
Ω
Cl=100pF
Vosc=100mV
PP
T=25°C
100
PSRR
-
1k
Frequency (Hz)
10k -1 0 1 2
Time (µs)
3 4 5
Figure 20: Total harmonic distortion and noise vs frequency and Rload
1
0.1
Vicm=Vcc/2
Gain=1
Vin=1Vpp
BW=80kHz
T=25°C
Vcc=1.5V
Rl=2k
Ω
Vcc=5.5V
Rl=2k
Ω
100k
Figure 21: Total harmonic distortion and noise vs frequency and input voltage
1
Vin=200mVpp
Vin=50mVpp
0.1
Vcc=1.5V
Rl=10k
Ω
0.01
Vcc=5.5V
Rl=10k
Ω
1E-3
100 1000
Frequency (Hz)
10000
Figure 22: Total harmonic distortion and noise vs output voltage at Rload = 2 kΩ
1
0.01
1E-3
Vin=3Vpp
100 1000
Frequency (Hz)
Vicm=Vcc/2
Gain=1
Vin=1Vpp
BW=80kHz
Rl=2k
Ω
T=25°C
10000
Figure 23: Total harmonic distortion and noise vs output voltage at Rload = 100 kΩ
1
12/20
0.1
0.01
1E-3
0.01
Vicm=Vcc/2
Gain=1 f=1kHz
BW=22kHz
Rl=2k
Ω
T=25°C
1.8V
3.3V
5V
0.1
1
Output Voltage (Vpp)
5.5V
10
0.1
1.8V
3.3V
5V
5.5V
0.01
1E-3
0.01
Vicm=Vcc/2
Gain=1 f=1kHz
BW=22kHz
Rl=100k
Ω
T=25°C
0.1
1
Output Voltage (Vpp)
DocID027171 Rev 3
10
RHR61, RHR64
5 Radiations
Radiations
Total ionizing dose (MIL-STD-883 TM 1019)
The products guaranteed by radiation within the RHA QML-V system, fully comply with the
MIL-STD-883 TM 1019 specification.
The RHR61 and RHR64 are RHA QML-V tested and characterized in full compliance with the MIL-STD-883 specification, condition B (between 10 and 100 mrad/s).
All parameters provided in Table 4 ,
apply to pre-irradiation, Table 7 and Table 8 apply to post-irradiation as follows:
•
All tests are performed in accordance with MIL-PRF-38535 and the test method 1019 of the MIL-STD-883 for total ionizing dose (TID).
•
The initial characterization is performed in qualification only on both biased and unbiased parts.
•
Each wafer lot is tested in the worst bias case condition, based on the results obtained during the initial qualification.
Heavy ions
The behavior of the product when submitted to heavy ions is not tested in production.
Heavy ion trials are performed on qualification lots only.
Table 9: Radiations
Type Characteristics Value Unit
TID Low-dose rate (36 to 360 rad/h) up to: 100 krad
Heavy ions
SEL immunity up to:
(with a particle angle of 60 ° at 125 °C)
SEL immunity up to:
(with a particle angle of 0 ° at 125 °C)
SET immunity (at 25 °C)
120
60
Characterized
MeV.cm²/mg
DocID027171 Rev 3 13/20
Package information
6 Package information
RHR61, RHR64
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com.
ECOPACK ® is an ST trademark.
14/20 DocID027171 Rev 3
RHR61, RHR64
6.1 Ceramic Flat-8 package information
Figure 24: Ceramic Flat-8 package outline
Package information
E
E2
E3 e
A b c
D
L
Q
S1
N
The upper metallic lid is electrically connected to pin 5. No other pin is electrically connected to the metallic lid nor to the IC die inside the package.
Ref
Table 10: Ceramic Flat-8 package mechanical data
Dimensions
Min.
Millimeters
Typ. Max. Min.
Inches
Typ.
2.24
0.38
0.10
6.35
6.35
4.32
0.88
2.44
0.43
0.13
6.48
6.48
4.45
1.01
1.27
2.64
0.48
0.16
6.61
6.61
4.58
1.14
0.088
0.015
0.004
0.250
0.250
0.170
0.035
0.096
0.017
0.005
0.255
0.255
0.175
0.040
0.050
6.51
0.66
0.92
0.79
1.12
08
7.38
0.92
1.32
0.256
0.026
0.036
0.031
0.044
08
Max.
0.104
0.019
0.006
0.260
0.260
0.180
0.045
0.291
0.036
0.052
DocID027171 Rev 3 15/20
Package information
6.2 Ceramic Flat-14 package information
Figure 25: Ceramic Flat-14 package outline b e c
RHR61, RHR64
16/20
L
E
14
1
8
7
E3
E2
E3
L
S1 Q
D A
E2
E3 e
L
Q
S1
A b c
D
E
The upper metallic lid is electrically connected to pin 11 (VCC-) only.
Ref.
Min.
2.31
0.38
0.10
9.27
6.19
Table 11: Ceramic Flat-14 package mechanical data
Dimensions
Millimeters
Typ.
Inches
Typ. Max.
2.72
0.48
0.18
9.73
6.50
Min.
0.091
0.015
0.004
0.365
0.244
0.76
6.86
0.66
0.13
3.68
1.27
7.62
1.14
0.030
0.145
0.050
0.250
0.026
0.005
0.300
0.045
Max.
0.107
0.019
0.007
0.383
0.256
DocID027171 Rev 3
RHR61, RHR64 Ordering information
7
Order code
Ordering information
Description
Table 12: Order codes
Temperature range Package
RHR61K1
RHR64K1
Engineering model
Ceramic Flat-8
Ceramic Flat-14
RHR61K01V
-55 °C to 125 °C
Ceramic Flat-8
QML-V flight model
RHR64K01V Ceramic Flat-14
RHR61K1
RHR64K1
5962R1620401
VXC
5962R1620501
VXC
Packing
Strip pack
Notes:
(1)
Specific marking only. Complete marking includes the following: ST logo, Date code (date the package was sealed) in YYWWA
(year, week, and lot index of week), Country of origin (FR = France).
DocID027171 Rev 3 17/20
Shipping information
8 Shipping information
Date code
The date code is structured as shown below:
•
EM xyywwz where:
• x (EM only) = 3 and the assembly location is Rennes, France
• yy = last two digits of the year
• ww = week digits
• z = lot index in the week
RHR61, RHR64
18/20 DocID027171 Rev 3
RHR61, RHR64
9
Revision history
Revision history
Date
Table 13: Document revision history
Revision Changes
11-May-2016
21-Apr-2017
05-Oct-2017
1
2
3
Initial release
Removed pinout diagrams from cover image to Section 1:
"Pin description", updated footnotes. Description: added order codes RHR61K01V and RHR64K01V, updated EPPL abbreviation. Table 2: "Absolute maximum ratings": updated
Rthjc value for Ceramic Flat-14. Table 4, Table 5, and Table
6: updated Isource values Table 7 and Table 8: updated
Isource and ICC values Table 12: "Order codes": updated table title and added order codes RHR61K01V and
RHR64K01V.
DocID027171 Rev 3 19/20
RHR61, RHR64
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
20/20 DocID027171 Rev 3
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