STMicroelectronics STGIB8CH60TS-E Datasheet

STGIB8CH60TS-E

Datasheet

SLLIMM - 2 nd series IPM, 3-phase inverter, 12 A, 600 V, short-circuit rugged IGBT

26

Marking area

1

17

1

18

26

SDIP2B-26L type E

17

18

Product status link

STGIB8CH60TS-E

Product summary

Order code STGIB8CH60TS-E

Marking

Package

Packing

GIB8CH60TS-E

SDIP2B-26L type E

Tube

Features

• IPM 12 A, 600 V, 3-phase IGBT inverter bridge including 2 control ICs for gate driving and freewheeling diodes

• 3.3 V, 5 V TTL/CMOS inputs with hysteresis

• Internal bootstrap diode

• Undervoltage lockout of gate drivers

• Smart shutdown function

• Short-circuit protection

• Shutdown input/fault output

• Separate open emitter outputs

• Built-in temperature sensor

• Comparator for fault protection

• Short-circuit rugged TFS IGBTs

• Very fast, soft recovery diodes

• 85 kΩ NTC, UL 1434, CA 4 recognized

• Fully isolated package

• Isolation rating of 1600 Vrms/min

• UL recognition: UL 1557, file E81734

Applications

• 3-phase inverters for motor drives

• Washing machines

• Dryer

• Industrial fans

• Pumps

Description

This second series of SLLIMM (small low-loss intelligent molded module) provides a compact, high-performance AC motor drive in a simple, rugged design. It combines new ST proprietary control ICs (one LS and one HS driver) with an improved shortcircuit rugged trench gate field-stop (TFS) IGBT, making it ideal for motor drives operating up to 20 kHz in hard-switching circuitries.

DS11862 - Rev 5 - September 2021

For further information contact your local STMicroelectronics sales office.

www.st.com

1

STGIB8CH60TS-E

Internal schematic and pin description

Internal schematic and pin description

Figure 1. Internal schematic diagram and pin configuration

NC(1 )

VbootU(2)

VbootV(3)

VbootW(4)

HinU(5)

HinV(6)

HinW(7)

VccH(8)

GND(9)

LinU(10)

LinV(11)

LinW(12)

VccL(13)

SD/OD(14)

Cin(15)

GND(16)

TSO(17)

H-side

L-side

(26)T1

(25)T2

(24)P

(23)U

(22)V

(21)W

(20)NU

(19)NV

(18)NW

GIPG120520140842FSR

DS11862 - Rev 5 page 2/23

DS11862 - Rev 5

14

15

16

17

18

9

10

11

12

13

4

5

6

7

8

Pin

1

2

3

19

20

21

22

23

24

25

26

GND

LINu

LINv

LINw

VCCL

SD/OD

CIN

GND

TSO

NW

Symbol

NC

VBOOTu

VBOOTv

VBOOTw

HINu

HINv

HINw

VCCH

NV

NU

W

V

U

P

T2

T1

STGIB8CH60TS-E

Internal schematic and pin description

Table 1. Pin description

Description

-

Bootstrap voltage for U phase

Bootstrap voltage for V phase

Bootstrap voltage for W phase

High-side logic input for U phase

High-side logic input for V phase

High-side logic input for W phase

High-side low voltage power supply

Ground

Low-side logic input for U phase

Low-side logic input for V phase

Low-side logic input for W phase

Low-side low voltage power supply

Shutdown logic input (active low) / open-drain (comparator output)

Comparator input

Ground

Temperature sensor output

Negative DC input for W phase

Negative DC input for V phase

Negative DC input for U phase

W phase output

V phase output

U phase output

Positive DC input

NTC thermistor terminal 2

NTC thermistor terminal 1 page 3/23

2

STGIB8CH60TS-E

Absolute maximum ratings

Absolute maximum ratings

T

J

= 25 °C unless otherwise noted.

Symbol

V

PN

V

PN(surge)

V

CES

± I

C

± I

CP

P

TOT t scw

Table 2. Inverter part

Parameter

Supply voltage among P -N

U

, -N

V

, -N

W

Supply voltage surge among P -N

U

, -N

V

, -N

W

Collector-emitter voltage each IGBT

Continuous collector current each IGBT (T

C

= 25 °C)

Continuous collector current each IGBT (T

C

= 80 °C)

Peak collector current each IGBT (less than 1 ms)

Total power dissipation at T

C

= 25 °C each IGBT

Short-circuit withstand time, V

CE

V

IN

= 0 to 5 V

= 300 V, T

J

= 125 °C, V

CC

= V boot

= 15 V,

Symbol

V

CC

V

BOOT

V

OUT

V

CIN

V

IN

V

SD/OD

I

SD/OD

V

TSO

I

TSO

Table 3. Control part

Parameter

Supply voltage between V

CCH

-GND,

V

CCL

-GND

Bootstrap voltage

Output voltage among U, V, W and GND

Comparator input voltage

Logic input voltage applied among HINx, LINx and GND

Open-drain voltage

Open-drain sink current

Temperature sensor output voltage

Temperature sensor output current

Min.

-0.3

-0.3

V

BOOT

- 21

-0.3

-0.3

-0.3

-0.3

Max.

20

619

V

BOOT

+ 0.3

20

15

7

10

5.5

7

12

8

24

50

Value

450

500

600

5

Unit

V

V

V

V

V

V mA

V mA

Unit

V

V

V

A

A

W

μs

Symbol

V

ISO

T

J

T

C

Table 4. Total system

Parameter

Isolation withstand voltage applied between each pin and heat sink plate

(AC voltage, t = 60 s)

Power chip operating junction temperature range

Module operation case temperature range

Value

1600

-40 to 175

-40 to 125

Unit

Vrms

°C

°C

DS11862 - Rev 5 page 4/23

2.1

Thermal data

Symbol

R thJC

Table 5. Thermal data

Parameter

Thermal resistance, junction-to-case, single IGBT

Thermal resistance, junction-to-case, single diode

STGIB8CH60TS-E

Thermal data

Value

3

6

Unit

°C/W

DS11862 - Rev 5 page 5/23

3

3.1

STGIB8CH60TS-E

Electrical characteristics

Electrical characteristics

T

J

= 25 °C unless otherwise specified.

Inverter part

Table 6. Static

Symbol

V

I

CES

CE(sat)

V

F

Parameter

Collector cut-off current

Collector-emitter saturation voltage

Diode forward voltage

Test conditions

V

CE

= 600 V, V

CC

= V boot

= 15 V

V

CC

= V boot

= 15 V, V

IN

(1) = 0 to 5 V,

I

C

= 8 A

V

CC

= V boot

= 15 V, V

IN

(1) = 0 to 5 V,

I

C

= 12 A

V

IN

= 0 V, I

C

= 8 A

V

IN

= 0 V, I

C

= 12 A

1. Applied among HINx, LINx and GND for x = U, V, W.

-

-

-

Min.

-

-

1.91

1.55

1.70

Typ.

Max.

100

Unit

µA

1.68

2.18

V

2.10

V

V

Table 7. Inductive load switching time and energy

Symbol t on

(1)

t c(on)

(1)

t off

(1)

t c(off)

(1)

t rr

E on

E off

E rr t on

(1)

t c(on)

(1)

t off

(1)

t c(off)

(1)

t rr

E on

E off

E rr

Parameter

Turn-on time

Crossover time on

Turn-off time

Crossover time off

Reverse recovery time

Turn-on switching energy

Turn-off switching energy

Reverse recovery energy

Turn-on time

Crossover time on

Turn-off time

Crossover time off

Reverse recovery time

Turn-on switching energy

Turn-off switching energy

Reverse recovery energy

V

V

V

V

DD

IN

(2)

DD

IN

(2)

Test conditions

= 300 V, V

CC

= V

= 0 to 5 V, I

C

= 300 V, V

CC

= 8 A

= V

= 0 to 5 V, I

C boot boot

= 12 A

= 15 V,

= 15 V,

Min.

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Typ.

280

142

400

85

215

201

102

8.1

300

175

380

85

220

340

160

10.2

Max.

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Unit ns

µJ ns

µJ

1. t on

and t off

include the propagation delay times of the internal drive. t

C(on) and t

C(off)

are the switching times of the IGBT itself under the internally given gate driving conditions.

2. Applied among HINx, LINx and GND for x = U, V, W.

DS11862 - Rev 5 page 6/23

DS11862 - Rev 5

Vcc

5 V

0 V

Input

+5V

STGIB8CH60TS-E

Inverter part

Rsd

Figure 2. Switching time test circuit

I c

VCC

HIN

GND

BOOT

HVG

OUT

VCC

LIN

SD

CIN

GND

LVG

+

Vce

-

L

C

-

+

Vdd

V

Figure 3. Switching time definition

100% I

C t rr

100% I

C

CE

I

C

I

C

V

CE

V

IN

V

IN(ON) t

ON

10% I

C t

C(ON)

90% I

C

10% V

CE

(a) turn-on

V

IN t

OFF

V

IN(OFF)

10% V

CE t

C(OFF)

10% I

C

(b) turn-off

AM09223V1 page 7/23

3.2

STGIB8CH60TS-E

Control/protection parts

Control/protection parts

Table 8. High- and low-side drivers

Symbol Parameter Test condition

I

I

V il

V ih

INh

INl

Low logic level voltage

High logic level voltage

IN logic “1” input bias current

IN logic “0” input bias current

IN x

= 15 V

IN x

= 0 V

High-side

V

V

V

V

V

V

CC_hys

CCH_th(on)

CCH_th(off)

BS_hys

BS_th(on)

BS_th(off)

I

I

I

QBSU

QBS qccu

V

CC

UV hysteresis

V

CCH

UV turn-on threshold

V

CCH

UV turn-off threshold

V

BS

UV hysteresis

V

BS

UV turn-on threshold

V

BS

UV turn-off threshold

Under voltage V

BS

quiescent current

V

BS

quiescent current

Under voltage quiescent supply current

V

V

V

BS

CC

CC

= 9 V, HINx

(1)

= 15 V, HINx

= 9 V, HINx

= 5 V

(1)

(1)

= 5 V

= 0 V

I qcc

R

DS(on)

Quiescent current

BS driver ON resistance

V

CC

= 15 V, HINx (1) = 0 V

Low-side

V

CC_hys

V

CCL_th(on)

V

CCL_th(off)

V

CC

UV hysteresis

V

CCL

UV turn-on threshold

V

CCL

UV turn-off threshold

I

I qccu qcc

Under voltage quiescent supply current

Quiescent current

V

CC

= 10 V,

SD pulled to 5 V through R

SD

= 10 kΩ,

CIN = LINx

(1)

= 0 V

V

CC

= 15 V, SD= 5 V,

CIN = LINx

(1)

= 0 V

V

SSD

I

SDh

I

SDl

Smart SD unlatch threshold

SD logic “1” input bias current

SD logic “0” input bias current

SD = 5 V

SD = 0 V

1. Applied between HINx, LINx and GND for x = U, V, W.

Min.

Typ.

Max.

Unit

2

0.8

V

V

80 150 200

1

µA

µA

1.2

11

1.4

11.5

1.7

12

9.6

10.1

10.6

0.5

1 1.6

10.1

9.1

11

10

11.9

10.9

55 75

125 170

190 250

560 730

150

µA

µA

V

V

V

V

V

V

µA

µA

Ω

1.1

1.4

1.6

10.4

11.6

12.4

9.0

10.3

11

V

V

V

600 800 µA

0.5

25

700 900 µA

0.6

50

0.75

70

1

V

µA

µA

DS11862 - Rev 5 page 8/23

DS11862 - Rev 5

STGIB8CH60TS-E

Control/protection parts

Symbol

V

TSO

I

TSO_SNK

I

TSO_SRC

Table 9. Temperature sensor output

Parameter

Temperature sensor output voltage

Temperature sensor sink current capability

Temperature sensor source current capability

T

J

= 25 °C

Test condition Min.

Typ.

Max.

Unit

0.974

1.16

1.345

V

0.1

4 mA mA

Symbol

I

CIN

V ref

V

OD t

CIN_SD

SR

SD

Table 10. Sense comparator (V

CC

= 15 V, unless otherwise is specified)

Test condition Parameter

CIN input bias current

Internal reference voltage

Open-drain low level output voltage

V

CIN

= 1 V

I od

= 5 mA

Min.

Typ.

Max.

Unit

-0.2

460 510

0.2

560

µA mV

500 mV

C

IN

comparator delay to SD

SD fall slew rate

SD pulled to 5 V through R

SD

= 10 kΩ; measured applying a voltage step 0-1 V to pin CIN;

50% CIN to 90% SD

SD pulled to 5 V through R

SD

= 10 kΩ;

C

L

= 1 nF through SD and ground;

90% SD to 10% SD

240 320 410

25 ns

V/µs

The comparator stays enabled even if V

CC

is in the UVLO condition but higher than 4 V.

page 9/23

4

STGIB8CH60TS-E

Fault management

Fault management

The device integrates an open-drain output connected to the SD pin. As soon as a fault occurs, the open-drain is activated and the LVGx outputs are forced low. Two types of fault can be identified:

•

•

Overcurrent (OC) sensed by the internal comparator (see more detail in Section 4.1 Smart shutdown function );

Undervoltage on supply voltage (V

CC

)

Each fault enables the SD open drain for a different time, as described in the following table.

Table 11. Fault timing

Symbol

OC

UVLO

Parameter

Over-current event

Under-voltage lockout event

1. Typical value (-40 °C ≤ T

J

≤ +125 °C).

2. Without contribution of the RC network on SD.

Event time

(1)

≤ 24 μs

> 24 µs

≤ 70 μs

> 70 µs until the VCC_LS exceeds the

VCC_LS UV turn ON threshold

SD open-drain enable time result (1) (2)

24 μs

OC time

70 µs

UVLO time

Actually, the device remains in a fault condition (SD at low logic level and LVGx outputs disabled) for a time also depending on the RC network connected to the SD pin. The network generates a time contribution that is added to the internal value.

Figure 4. Overcurrent timing (without contribution of the RC network on SD)

DS11862 - Rev 5

GIPG120520141638FSR page 10/23

STGIB8CH60TS-E

Fault management

Figure 5. UVLO timing (without contribution of the RC network on SD)

GIPG120520141644FSR

DS11862 - Rev 5 page 11/23

4.1

STGIB8CH60TS-E

Smart shutdown function

Smart shutdown function

The device integrates a comparator committed to the fault sensing function. The comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function.

The output signal of the comparator is fed to an integrated MOSFET with the open drain output available on the

SD input. When the comparator triggers, the device is set in shutdown state and its outputs are all set to low level.

Figure 6. Smart shutdown timing waveforms in case of overcurrent event comp

Vref

CIN

PROTECTION t

CIN_SD

LIN

LVG

SD l open-drain gate

(internal) t

1 t

OC real disable time

Fast shutdown: the driver outputs are set in SD state immediately after comparator triggering even if the SD signal has not yet reached the lower input threshold

SHUTDOWN CIRCUIT

FROM / TO

CONTROLLER

V

BIAS

R

SD

SD

C

SD

R

PD_SD

R

ON_OD

SMART

SD

LOGIC t t where:

1

2 t

2

R

ON_OD

= V

OD

/5 mA, see

Table 10. Sense comparator (V

CC

= 15 V, unless otherwise is specified) ;

R

PD_SD

(typ.) = 5 V/I

SDh

DS11862 - Rev 5 page 12/23

STGIB8CH60TS-E

Smart shutdown function

In common overcurrent protection designs, the comparator output is usually connected to the SD input and an RC network is connected to this SD line in order to provide a mono-stable circuit which implements a protection time that follows the fault condition.

As opposed to common fault detection systems, the device smart shutdown architecture allows the immediate turn-off of output gates driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual switching off of the outputs. In fact, the time delay between the fault and the turning off of the outputs is no longer dependent on the RC value of the external network connected to the pin.

In the smart shutdown circuitry, the fault signal has a preferential path which directly switches off the outputs after the comparator triggering.

At the same time, the internal logic turns on the open-drain output and holds it on until the SD voltage goes below the V

SSD

threshold and the t oc

time is elapsed.

The driver outputs restart following the input pins as soon as the voltage at the SD pin reaches the higher threshold of the SD logic input.

The smart shutdown system provides the possibility to increase the time constant of the external RC network (i.e., the disable time after the fault event) up to very high values without increasing the delay time of the protection.

DS11862 - Rev 5 page 13/23

5

5.1

5.2

STGIB8CH60TS-E

Temperature monitoring solutions

Temperature monitoring solutions

TSO output

The device integrates a temperature sensor. A voltage proportional to the die temperature is available on the TSO pin. When this function is not used, the pin can be left floating.

Figure 7. V

TSO

output characteristics vs LVIC temperature

V

TSO

(V)

IGBT110820161234TSO

2.8

Min

2.2

1.6

1.0

0.4

0

Max

Typ

25 50 75 100 T (°C)

NTC thermistor

Symbol

R

25

R

125

B

T

Parameter

Resistance

Resistance

B-constant

Operating temperature range

Table 12. NTC thermistor

Test condition

T = 25 °C

T = 125 °C

T = 25 to 100 °C

Min.

-40

Typ.

85

2.6

4092

Max.

125

Unit kΩ kΩ

K

°C

DS11862 - Rev 5 page 14/23

DS11862 - Rev 5

R(kΩ)

30

25

20

15

10

5

0

50

STGIB8CH60TS-E

NTC thermistor

Figure 8. NTC resistance vs temperature

R(kΩ)

3000

2500

2000

1500

1000

500

0

-50

Typ

-25

Min

Max

0 25 50 75

GIPG120520142249FSR

100 125 T(°C)

Figure 9. NTC resistance vs temperature - zoom

GIPG120520141304FSR

60

Typ

Max

Min

70 80 90 100 110 120 T(°C) page 15/23

6

Application circuit example

Figure 10. Application circuit example

STGIB8CH60TS-E

Application circuit example

DS11862 - Rev 5

MICROCONTROLLER

Application designers are free to use a different scheme based on the device specifications.

page 16/23

6.1

STGIB8CH60TS-E

Guidelines

Guidelines

1.

Input signals HIN, LIN are active-high logic. A 100 kΩ (typ.) pull-down resistor is built-in for each input pin.

To prevent input signal oscillations, the wiring of each input should be as short as possible and the use of

RC filters (R

1

, C

1

) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins.

2.

The use of a bypass capacitor C

VCC

(aluminum or tantalum) can reduce the transient circuit demand on the power supply. Besides, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C

2

(100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to each V cc

pin and in parallel with the bypass capacitor.

3.

The use of an RC filter (R

SF

, C

SF

) prevents protection circuit malfunctions. The time constant (R

SF

x C

SF

) should be set to 1 µs and the filter must be placed as close as possible to the CIN pin.

4.

The SD is an input/output pin (open-drain type if it is used as output). It should be pulled up to a power supply (i.e., MCU bias at 3.3/5 V) by a resistor value, which can keep the I od

no higher than 5 mA (V

OD

≤

500 mV when open-drain MOSFET is ON). The filter on SD should be sized to get a desired re-starting time after a fault event and placed as close as possible to the SD pin.

5.

A decoupling capacitor C

TSO

between 1 nF and 10 nF can be used to increase the noise immunity of the

TSO thermal sensor; a similar decoupling capacitor C

OT

(between 10 nF and 100 nF) can be implemented if the NTC thermistor is available and used. In both cases, their effectiveness is improved if these capacitors are placed close to the MCU.

6.

The decoupling capacitor C

3

U,V,W and V boot

(100 to 220 nF with low ESR and low ESL) in parallel with each C boot high-frequency disturbances. Both C boot

and C

3

filters

(if present) should be placed as close as possible to the

pins. Bootstrap negative electrodes should be connected to the U,V,W terminals directly and separated from the main output wires.

7.

To prevent overvoltage on the V

CC

pin, a Zener diode (Dz1) can be used. Similarly on the V boot

pin, a Zener diode (Dz2) can be placed in parallel with each C boot

.

8.

The use of the decoupling capacitor C

4

(100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor C

Vdc

prevents surge destruction. Both capacitors C

4

and C

Vdc

should be placed as close as possible to the IPM (C

4

has priority over C vdc

).

9.

By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an optocoupler is possible.

10. Low inductance shunt resistors should be used for phase leg current sensing.

11. In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible.

12. The connection of the SGN_GND to the PWR_GND at one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation.

These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note.

Symbol

V

PN

V

CC

V

BS t dead f

PWM

T

C

Table 13. Recommended operating conditions

Parameter

Supply voltage

Control supply voltage

High-side bias voltage

Test conditions

Applied between P-Nu, N

V

, N w

Applied between V

CC

-GND

Applied between V

BOOTi

-OUT i for i = U, V, W

Blanking time to prevent arm-short For each input signal

PWM input signal

-40 °C < T

C

< 100 °C

-40 °C < T

J

< 125 °C

Case operation temperature

Min.

13.5

13

1.0

Typ.

300

15

Max.

400

18

Unit

V

V

18 V

µs

20

100 kHz

°C

DS11862 - Rev 5 page 17/23

STGIB8CH60TS-E

Electrical characteristics (curves)

7

Electrical characteristics (curves)

Figure 11. Output characteristics

I

C

(A)

20

IGBT141220151035OC25

V

CC

= 18 V

15 V 13 V

16

12

8

4

0

0.0

0.5

1.0

1.5

2.0

2.5

V

CE

(V)

I

C

(A)

12

Figure 13. I

C

vs case temperature

GADG150420191028CCT

V

CC

≥ 15 V, T

J

≤ 175 °C

10

8

6

4

2

0

0 25 50 75 100 125 150 T

C

(°C)

Figure 15. E on

switching energy vs collector current

E on

(mJ)

IGBT110820161224SLC

1.2

V

DD

= 300 V

V

CC

= V boot

= 15 V

0.9

T

J

= 175 °C

0.6

0.3

0.0

0 4 8

T

J

= 25 °C

12 16 20 I

C

(A)

Figure 12. V

CE(sat)

vs collector current

V

CE(sat)

(V)

3.2

IGBT141220151055VCEC

V

CC

= 15 V

2.8

2.4

2.0

1.6

1.2

0.8

0 4 8

T

J

= 175 °C

12

T

J

= 25 °C

16 20 I

C

(A)

Figure 14. Diode V

F

vs forward current

V

F

(V)

2.0

IGBT141220151056DVF

T

J

= 25 °C

1.6

T

J

= 175 °C

1.2

0.8

0.4

0.0

0 4 8 12 16 20 I

F

(A)

Figure 16. E off

switching energy vs collector current

E off

(mJ)

0.5

IGBT110820161231SLG

V

DD

= 300 V

V

CC

= V boot

= 15 V

0.4

T

J

= 175 °C

0.3

0.2

T

J

= 25°C

0.1

0.0

0 4 8 12 16 20 I

C

(A)

DS11862 - Rev 5 page 18/23

K

Figure 17. Thermal impedance

GIPD290720151032FSR

10 -1

10 -2

10 -5 10 -4 10 -3 10 -2 10 -1 10 0 t p

(s)

STGIB8CH60TS-E

Electrical characteristics (curves)

DS11862 - Rev 5 page 19/23

8

8.1

STGIB8CH60TS-E

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

SDIP2B-26L type E package information

Figure 18. SDIP2B-26L type E package outline

DS11862 - Rev 5

8450802_7_type_E page 20/23

DS11862 - Rev 5

Ref.

e e1 e2 e3 e4

C

C1

C2

D

D1

B

B1

B2

B3

B4

A

A1

A2

A3 c

F

F1

R

T

V

E

E1

E2 f f1

STGIB8CH60TS-E

SDIP2B-26L type E package information

Table 14. SDIP2B-26L type E package mechanical data

28.45

2.725

3.356

1.578

7.42

13.90

28.70

33.20

3.30

5.00

9.00

4.88

2.34

11.90

3.45

Min.

37.50

0.97

0.97

34.70

1.45

23.50

0.45

0.35

1.95

0.95

1.55

0.375

0°

Dimensions (mm)

Typ.

3.556

1.778

7.62

5.08

2.54

3.50

5.50

9.50

28.95

3.025

24.00

12.00

14.40

29.20

33.70

38.00

1.22

1.22

35.00

1.50

12.40

3.75

1.80

0.60

0.50

2.10

1.10

1.575

0.40

29.45

3.325

3.756

1.978

7.82

14.90

29.70

34.20

3.70

6.00

10.00

5.28

2.74

12.90

4.05

0.75

0.65

2.25

1.25

1.60

0.425

5°

Max.

38.50

1.47

1.47

35.30

1.55

24.50

page 21/23

STGIB8CH60TS-E

Revision history

Date

12-Oct-2016

16-May-2018

25-Jun-2018

21-May-2019

09-Sep-2021

2

3

4

5

Table 15. Document revision history

Revision

1

Changes

First release.

Removed maturity status indication from cover page.

Updated features list on cover page.

Updated Table 11. Fault timing .

Updated Section 9.1 SDIP2B-26L type E package information .

Minor text changes

Updated Section 2 Absolute maximum ratings.

Updated Section 7 Guidelines.

Minor text changes

Added Figure 13. I

C

vs case temperature

Minor text changes.

Updated features in cover page and Table 4. Total system

.

DS11862 - Rev 5 page 22/23

STGIB8CH60TS-E

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of

Purchasers’ products.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2021 STMicroelectronics – All rights reserved

DS11862 - Rev 5 page 23/23