STF40N65M2
Nchannel 650 V, 0.087 Ω typ., 32 A MDmesh™ M2
Power MOSFET in a TO-220FP package
Datasheet - production data
1
2
3
TO-220FP
Figure 1: Internal schematic diagram
D(2)
G(1)
Features
Order code
STF40N65M2
V
DS
650 V
R
DS(on)
max.
0.099 Ω
I
D
32 A
•
Extremely low gate charge
•
Excellent output capacitance (C
OSS
) profile
•
100% avalanche tested
•
Zener-protected
Applications
•
Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters.
Order code
STF40N65M2
S(3)
AM15572v1_no_tab
Table 1: Device summary
Marking Package
40N65M2 TO-220FP
Packaging
Tube
February 2015 DocID027442 Rev 1
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STF40N65M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.2
Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1
TO-220FP package information ...................................................... 10
5 Revision history ............................................................................ 12
2/13 DocID027442 Rev 1
STF40N65M2
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
D
(1)
I
D
(1)
I
DM
(2)
P
TOT
dv/dt
(3) dv/dt
(4)
V
ISO
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; T
C
= 25 °C)
T stg
T j
Storage temperature
Max. operating junction temperature
Notes:
(1)
Limited by maximum junction temperature.
(2)
Pulse width limited by safe operating area.
(3)
I
SD
≤ 32 A, di/dt ≤ 400 A/µs; V
DS peak
< V
(BR)DSS
, V
DD
= 400 V
(4)
V
DS
≤ 520 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case max
Thermal resistance junction-ambient max
Symbol
I
AR
E
AS
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetetive or not repetetive (pulse width limited by T jmax
)
Single pulse avalanche energy (starting T j
= 25 °C, I
D
= I
AR
,
V
DD
= 50 V)
Electrical ratings
Value
± 25
32
20
128
25
15
50
2500
- 55 to
150
150
Value
3.13
62.50
Unit
°C/W
°C/W
Value
3
820
Unit
V
A
A
A
W
V/ns
V/ns
V
°C
Unit
A mJ
DocID027442 Rev 1 3/13
Electrical characteristics
2 Electrical characteristics
STF40N65M2
(T
C
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: On/off states
Test conditions
V
(BR)DSS
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero gate voltage Drain current
V
GS
= 0 V, V
DS
= 650 V
V
GS
= 0 V, V
DS
= 650 V,
T
C
= 125 °C
I
GSS
Gate-body leakage current V
DS
= 0 V, V
GS
= ± 25 V
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 16 A
Symbol
Drain-source breakdown voltage
Parameter
Table 6: Dynamic
Test conditions
C
C
C
R oss
Q
Q
Q iss rss
G g gs gd
C
oss eq.
(1)
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V f = 1 MHz open drain
V
DD
= 520 V, I
D
= 32 A,
V
GS
= 10 V (see Figure 15:
"Gate charge test circuit" )
Min. Typ. Max. Unit
650
2 3
1
-
-
V
µA
100 µA
±10 µA
4 V
0.087 0.099
Ω
Min. Typ. Max. Unit
- 2355
- 102
-
- pF pF
V
DS
= 0 V to 520 V, V
GS
= 0 V -
-
-
-
-
-
2.7
380
4.5
56.5
8
24
-
-
-
- pF pF
Ω nC nC nC
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
4/13 DocID027442 Rev 1
STF40N65M2
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Table 7: Switching times
Test conditions
V
DD
= 325 V, I
D
= 16 A
R
G
= 4.7
Ω, V
GS
= 10 V (see
Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
15
10
- 96.5
- 12
-
-
-
- ns ns ns ns
Symbol
I
RRM
Parameter
I
SD
Source-drain current
I
SDM
(1)
Source-drain current
(pulsed)
V
SD
(2)
Forward on voltage t rr
Reverse recovery time
Q rr
Reverse recovery charge
Table 8: Source drain diode
Test conditions
Reverse recovery current
V
GS
I
SD
= 0 V, I
SD
= 32 A
= 32 A, di/dt = 100 A/µs,
V
DD
= 60 V (see Figure 16: "
Test circuit for inductive load switching and diode recovery times" )
Min. Typ. Max. Unit
- 32 A
- 128 A
-
-
-
468
8.7
1.6 V ns
µC
- 37.5 A t rr
Q rr
I
RRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 32 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C (see
Figure 16: " Test circuit for inductive load switching and diode recovery times" )
- 610
- 11.7
- 39 ns
µC
A
Notes:
(1)
Pulse width is limited by safe operating area
(2)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%
DocID027442 Rev 1 5/13
Electrical characteristics
2.2 Electrical characteristics (curves)
Figure 2: Safe operating area
STF40N65M2
K
Figure 3: Thermal impedance
GC20521
δ = 0.5
10 -1
10 -2
δ = 0.2
δ = 0.1
δ = 0.02
δ = 0.01
δ = 0.05
SINGLE PULSE
Z th
= K*R thj-c
δ = t p
/ Ƭ
40
30
20
10
0
0
I
D
(A)
70
Figure 4: Output characteristics
GIPG300120151500ALS
V
GS
= 6,7,8,9,10 V
V
GS
= 5 V
60
50
4 8
V
GS
= 4 V
12 16 20 24
Figure 6: Normalized gate threshold voltage vs temperature
10 -3
10 -4 10 -3 10 -2 10 -1 t p Ƭ
10 0 T p
(s)
60
50
40
30
Figure 5: Transfer characteristics
I
D
(A)
70
GIPG300120151715ALS
V
GS
= 20 V
20
10
0
0 2 4 6 8 V
GS
(V)
Figure 7: Normalized V
(BR)DSS
vs temperature
6/13 DocID027442 Rev 1
STF40N65M2
Figure 8: Static drain-source on-resistance
Electrical characteristics
Figure 9: Normalized on-resistance vs. temperature
Figure 10: Gate charge vs. gate-source voltage
Figure 11: Capacitance variations
Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics
DocID027442 Rev 1 7/13
Test circuits
3 Test circuits
Figure 14: Switching times test circuit for resistive load
STF40N65M2
Figure 15: Gate charge test circuit
12 V 47 k
Ω
100 nF
1 k
Ω
V
DD
V i
≤ V
GS
2200 μ F
I
G
= CONST
2.7 k
Ω
47 k
Ω
1 k
Ω
P
W
100 Ω
D.U.T.
V G
AM01469v 1
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
25
Ω
G
A
D
D.U.T.
S
B
R
G
A
FAST
DIODE
A
B
B
L=100 µH
G
D
D.U.T.
S
3.3
µF
1000
µF
V
DD
V
DD
AM01470v1
Figure 18: Unclamped inductive waveform
V
(BR)DSS
V
D
I
D
I
DM
V
DD
0
Figure 19: Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
10%
V
DS
V
GS
90%
AM01472v 1
0
10% AM01473v 1
8/13 DocID027442 Rev 1
STF40N65M2
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
DocID027442 Rev 1 9/13
Package information
4.1 TO-220FP package information
Figure 20: TO-220FP package outline
STF40N65M2
10/13 DocID027442 Rev 1
7012510_Rev_K_B
STF40N65M2
Dim.
L2
L3
L4
L5
F2
G
G1
H
A
B
D
E
F
F1
L6
L7
Dia
Table 9: TO-220FP mechanical data mm
Typ. Min.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
28.6
9.8
2.9
15.9
9
3
Package information
Max.
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
DocID027442 Rev 1 11/13
Revision history
5
STF40N65M2
Revision history
Date
09-Feb-2014
Table 10: Document revision history
Revision
1
Changes
First release.
12/13 DocID027442 Rev 1
STF40N65M2
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DocID027442 Rev 1 13/13
