STMicroelectronics STF12N65M2 Datasheet
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تبلیغات
STF12N65M2
Nchannel 650 V, 0.42 Ω typ., 8 A MDmesh™ M2
Power MOSFET in a TO-220FP package
Datasheet - production data
TO-220FP
Figure 1: Internal schematic diagram
D(2)
G(1)
Features
Order code V
DS
R
DS(on)
max. I
D
STF12N65M2 650 V 0.50 Ω 8 A
Extremely low gate charge
Excellent output capacitance (C
OSS
) profile
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters.
Order code
STF12N65M2
S(3)
AM15572v1_no_tab
Table 1: Device summary
Marking Package
12N65M2 TO-220FP
Packing
Tube
June 2017 DocID027318 Rev 3
This is information on a product in full production.
1/13 www.st.com
Contents
Contents
STF12N65M2
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
Electrical characteristics (curves) ...................................................... 6
4 Package information ....................................................................... 9
TO-220FP package information ...................................................... 10
5 Revision history ............................................................................ 12
2/13 DocID027318 Rev 3
STF12N65M2
1
Electrical ratings
Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
V
GS
I
I
P
TOT
V
ISO
T stg
T j
Gate-source voltage
Drain current (continuous) at T case
= 25 °C
Drain current (continuous) at T case
= 100 °C
Drain current (pulsed)
Total dissipation at T case
= 25 °C
Peak diode recovery voltage slope
MOSFET dv/dt ruggedness
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; T
C
= 25 °C)
Storage temperature range
Operating junction temperature range
2.5
-55 to 150
Value
±25
8
5
32
25
15
50
Notes:
(1)
Limited by package.
(2)
Pulse width is limited by safe operating area.
(3)
I
SD
≤ 8 A, di/dt = 400 A/μs; V
DS(peak)
< V
(BR)DSS
, V
DD
= 400 V
(4)
V
DS
≤ 520 V
Symbol
Table 3: Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Symbol
I
AR
E
Table 4: Avalanche characteristics
Parameter
Avalanche current, repetitive or not repetitive (pulse width limited by T jmax.
)
Single pulse avalanche energy (starting T j
= 25 °C,
I
D
= I
AR
; V
DD
= 50 V)
Value
5
62.5
Value
1.6
250
Notes:
(1)
Starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V.
kV
°C
Unit
°C/W
Unit
A mJ
Unit
V
A
A
W
V/ns
DocID027318 Rev 3 3/13
Electrical characteristics
2 Electrical characteristics
(T case
= 25 °C unless otherwise specified)
Symbol Parameter
Table 5: Static
Test conditions
V
(BR)DSS
Drain-source breakdown voltage
V
GS
= 0 V, I
D
= 1 mA
I
DSS
Zero-gate voltage drain current
V
GS
= 0 V, V
DS
= 650 V
V
GS
= 0 V, V
DS
= 600 V,
T case
I
GSS
Gate-body leakage current
V
GS(th)
Gate threshold voltage
R
DS(on)
Static drain-source onresistance
V
DS
= 0 V, V
GS
= ±25 V
V
DS
= V
GS
, I
D
= 250 µA
V
GS
= 10 V, I
D
= 4 A
STF12N65M2
Min. Typ. Max. Unit
650 V
1
µA
100
±10 µA
3 4 V
0.42 0.50
Ω
2
Notes:
(1)
Defined by design, not subject to production test.
Symbol Parameter
Table 6: Dynamic
Test conditions
C iss
C oss
C rss
C oss
R
G
Q g
Q gs
Q gd
Input capacitance
Output capacitance
Reverse transfer capacitance
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
V
DS
= 100 V, f = 1 MHz,
V
GS
= 0 V
V
DS
= 0 to 520 V, V
GS
= 0 V f = 1 MHz, I
D
= 0 A
V
DD
= 520 V, I
D
= 8 A, V
GS
= 0
to10 V (see Figure 15: "Test circuit for gate charge behavior" )
-
-
-
-
-
Min. Typ. Max. Unit
-
-
535
25
-
- pF
- 1.1 -
144
7
16.7
2.6
8.6
-
-
-
-
- pF
Ω nC
Notes:
(1)
C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to 80% V
DSS
.
Symbol Parameter
Table 7: Switching times
Test conditions Min. Typ. Max. Unit t d(on)
Turn-on delay time t r
Rise time t d(off)
Turn-off delay time t f
Fall time
V
DD
= 325 V, I
D
= 4 A
R
G
= 4.7
Ω, V
GS
= 10 V (see
-
-
-
-
9
7
34
13.5
-
-
-
- ns
4/13 DocID027318 Rev 3
STF12N65M2
Symbol Parameter
I
Source-drain current
I
Source-drain current
(pulsed)
V
Forward on voltage t rr
Q rr
Reverse recovery time
Reverse recovery charge
I
I
RRM t
Q rr rr
RRM
Table 8: Source-drain diode
Test conditions
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
V
GS
= 0 V, I
SD
= 8 A
I
SD
= 8 A, di/dt = 100 A/µs,
V
DD
"Test circuit for inductive load switching and diode recovery times" )
I
SD
= 8 A, di/dt = 100 A/µs,
V
DD
= 60 V, T j
= 150 °C (see
Figure 16: "Test circuit for inductive load switching and diode recovery times" )
Electrical characteristics
Min. Typ. Max. Unit
-
-
-
-
-
-
-
-
-
313
2.7
17
462
4.1
17.5
8
32
1.6
A
A
V ns
µC
A ns
µC
A
Notes:
(1)
Limited by package.
(2)
Pulse width is limited by safe operating area.
(3)
Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
DocID027318 Rev 3 5/13
Electrical characteristics
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
STF12N65M2
Figure 3: Thermal impedance
Figure 4: Output characteristics Figure 5: Transfer characteristics
6/13
Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
GIPD161220141813MT
R
DS(on)
(Ω)
V GS = 10V
0.44
0.43
0.42
0.41
0.40
0 2 4 6 8 I D (A)
DocID027318 Rev 3
STF12N65M2
C
(pF)
Figure 8: Capacitance variations
GIPD161220141823MT
Ciss
1000
100
Coss
10
Crss
1
0.1
0.1
1 10 100 V DS (V)
Figure 10: Normalized on-resistance vs temperature
Electrical characteristics
Figure 9: Normalized gate threshold voltage vs temperature
GIPD180920141442FSR
V GS(th)
(norm)
I D = 250 µ A
1.1
1.0
0.9
0.8
0.7
0.6
-75 -25 25 75 125 T j (°C)
Figure 11: Normalized V
(BR)DSS
vs temperature
GIPD180920141448FSR
V (BR)DSS
(norm)
1.08
I D = 1m A
1.04
1.00
0.96
0.92
0.88
-75 -25 25 75 125 T j (°C)
Figure 12: Output capacitance stored energy
GIPD171220141020MT
E
(µJ)
4
3
2
1
0
0 100 200 300 400 500 600 V
DS
(V)
0.8
0.7
0.6
0.5
0
Figure 13: Source- drain diode forward characteristics
GIPD161220141847MT
V SD
(V)
1.1
T j = -50°C
1
0.9
T j
= 25°C
2 4 6
T j = 150°C
8 I
SD
(A)
DocID027318 Rev 3 7/13
Test circuits
3 Test circuits
Figure 14: Test circuit for resistive load switching times
STF12N65M2
Figure 15: Test circuit for gate charge behavior
8/13
Figure 16: Test circuit for inductive load switching and diode recovery times
Figure 17: Unclamped inductive load test circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
DocID027318 Rev 3
STF12N65M2
4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID027318 Rev 3 9/13
Package information
4.1 TO-220FP package information
Figure 20: TO-220FP package outline
STF12N65M2
10/13 DocID027318 Rev 3
7012510_Rev_12_B
STF12N65M2
Dim.
G1
H
L2
L3
L4
L5
L6
L7
Dia
F
F1
F2
G
A
B
D
E
Table 9: TO-220FP package mechanical data mm
Min. Typ.
4.4
2.5
2.5
0.45
0.75
1.15
1.15
4.95
2.4
10
16
28.6
9.8
2.9
15.9
9
3
Package information
Max.
4.6
2.7
2.75
0.7
1
1.70
1.70
5.2
2.7
10.4
30.6
10.6
3.6
16.4
9.3
3.2
DocID027318 Rev 3 11/13
Revision history
5
STF12N65M2
Revision history
Date Revision
Table 10: Document revision history
Changes
16-Dec-2014
11-Mar-2015
06-Jun-2017
1
2
3
First release.
Updated features in cover page. Minor text changes
Updated Section 1: "Electrical ratings" ,
Section 2: "Electrical characteristics"
and Section 2.1: "Electrical characteristics (curves)" .
12/13 DocID027318 Rev 3
STF12N65M2
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DocID027318 Rev 3 13/13
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